STFI15N95K5
Nchannel 950 V, 0.41 Ω typ., 12 A MDmesh™ K5
Power MOSFET in a I²PAKFP package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2)
G(1)
Order code
STFI15N95K5
1 2
3
I 2 PAKFP
(TO-281)
S(3)
Features
Order code V
DS
R
DS(on)
max. I
D
P tot
STFI15N95K5 950 V 0.50 Ω 12 A 30 W
Fully insulated and low profile package with increased creepage path from pin to heatsink plate
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOS FET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
AM15572v1_no_tab
Table 1: Device summary
Marking Package
15N95K5 I²PAKFP (TO-281)
Packing
Tube
July 2016 DocID029528 Rev 1
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STFI15N95K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package information ..................................................................... 10
4.1
I2PAKFP (TO-281) package information ......................................... 10
5 Revision history ............................................................................ 12
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STFI15N95K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
Gate-source voltage
I
D
(1)
Drain current (continuous) at T
C
= 25 °C
I
D
(1)
Drain current (continuous) at T
C
= 100 °C
I
DM
(2)
Drain current pulsed
P
TOT
Total dissipation at T
C
= 25 °C
ESD Gatesource human body model (R= 1,5 kΩ, C = 100 pF)
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s;T
C
=25 °C)
dv/dt (3)
Peak diode recovery voltage slope
dv/dt (4)
MOSFET dv/dt ruggedness
T j
T stg
Operating junction temperature range
Storage temperature range
Notes:
(1)
Limited by maximum junction temperature.
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 12 A, di/dt ≤ 100 A/μs, V
DS
(peak) ≤ V
(BR)DSS
(4)
V
DS
≤ 760 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
E
AR
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting Tj = 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
- 55 to 150
Value
4.2
62.5
124
Value
± 30
12
7.6
48
30
2
2500
4.5
50
Value
4
V/ns
°C
Unit
°C/W
°C/W mJ
Unit
V
A
A
A
W kV
V
Unit
A
DocID029528 Rev 1 3/13
Electrical characteristics
2
4/13
STFI15N95K5
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
DS
= 950 V, V
GS
= 0 V
I
DSS
Zero gate voltage drain current V
DS
= 950 V, V
T
C
= 125 °C (1)
GS
= 0 V
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
V
GS
DS
= ± 20 V, V
= V
GS
, I
D
DS
= 0 V
= 100 µA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 6 A
Min. Typ. Max. Unit
950 V
1 µA
50 µA
±10 µA
4 5 V
0.41 0.50
Ω
3
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
GS
= 0 V, V
DS
= 0 to 760 V f = 1 MHz open drain
V
DD
= 760 V, I
D
= 12 A
V
GS
= 10 V
(see Figure 16: "Test circuit for gate charge behavior" )
-
-
-
Min. Typ. Max. Unit
-
-
-
855
65
1
-
-
- pF pF pF
-
-
104
38
6
30
5
22
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol t f
Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time
Fall time
Table 7: Switching times
Test conditions
V
DD
= 475 V, I
D
= 6 A, R
G
= 4.7 Ω
V
GS
= 10 V
(see Figure 15: "Test circuit for resistive load switching times" and Figure 18: "Unclamped inductive load test circuit" )
Min. Typ. Max. Unit
-
-
-
-
23
20
62
11
-
-
-
- ns ns ns ns
DocID029528 Rev 1
STFI15N95K5
Symbol
I
SD
Source-drain current
I
SDM
Source-drain current
(pulsed)
V
SD
(1)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM t rr
Q rr
I
RRM
Parameter
Table 8: Source-drain diode
Test conditions
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
SD
SD
= 12 A, V
GS
= 0 V
= 12 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 17: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 12 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see Figure 17: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 12 A
- 48 A
-
-
-
444
7
1.5 V ns
µC
-
-
-
-
32
630
9.2
29
A ns
µC
A
Notes:
(1)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min Typ. Max Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1 mA, I
D
= 0 A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
DocID029528 Rev 1 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STFI15N95K5
Figure 3: Thermal Impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
6/13
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
W
DocID029528 Rev 1
STFI15N95K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Output capacitance stored energy
µ
Figure 10: Normalized gate threshold voltage vs temperature
µ
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Normalized VDS vs temperature
Figure 13: Source-drain diode forward characteristics
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Electrical characteristics
Figure 14: Maximum avalanche energy vs starting TJ
STFI15N95K5
8/13 DocID029528 Rev 1
STFI15N95K5
3 Test circuits
Figure 15: Test circuit for resistive load switching times
Test circuits
Figure 16: Test circuit for gate charge behavior
Figure 17: Test circuit for inductive load switching and diode recovery times
Figure 18: Unclamped inductive load test circuit
Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform
DocID029528 Rev 1 9/13
Package information
4
4.1
Package information
STFI15N95K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
I2PAKFP (TO-281) package information
Figure 21: I²PAKFP (TO-281) package outline
10/13 DocID029528 Rev 1
8291506 Re v. C
STFI15N95K5
Dim.
H
L1
L2
L3
L4
L5
L6
E
F
F1
G
A
B
D
D1
Table 10: I²PAKFP (TO-281) mechanical data mm
Min. Typ.
4.40
2.50
2.50
0.65
0.45
0.75
4.95
10.00
21.00
13.20
10.55
2.70
0.85
7.50 7.60
Package information
Max.
10.40
23.00
14.10
10.85
3.20
1.25
7.70
4.60
2.70
2.75
0.85
0.70
1.00
1.20
5.20
DocID029528 Rev 1 11/13
Revision history
5
STFI15N95K5
Revision history
Date
29-Jul-2016
Table 11: Document revision history
Revision
1 First release.
Changes
12/13 DocID029528 Rev 1
STFI15N95K5
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