STFI10LN80K5
Nchannel 800 V, 0.55 Ω typ., 8 A MDmesh™ K5
Power MOSFET in a I²PAKFP package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2)
G(1)
1 2
3
I 2 PAKFP
(TO-281)
Order code
STFI10LN80K5
S(3)
Features
Order code V
DS
R
DS(on)
max. I
D
STFI10LN80K5 800 V 0.63 Ω 8 A
Fully insulated and low profile package with increased creepage path from pin to heatsink plate
Industry ’s R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed us ing MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
AM15572v1_no_tab
Table 1: Device summary
Marking
10LN80K5
Package
I²PAKFP
Packing
Tube
February 2016 DocID028981 Rev 1
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STFI10LN80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package information ..................................................................... 10
4.1
I2PAKFP (TO-281) package information ......................................... 10
5 Revision history ............................................................................ 12
2/13 DocID028981 Rev 1
STFI10LN80K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
Electrical ratings
V
GS
I
D
(1)
I
D
(1)
I
D
(2)
Gate-source voltage
Drain current (continuous) at T
Drain current (continuous) at T
Drain current pulsed
P
TOT
Total dissipation at T
C
= 25 °C
C
C
= 25 °C
= 100 °C
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1s; T
C
=25°C)
dv/dt
(3)
Peak diode recovery voltage slope
dv/dt
(4)
MOSFET dv/dt ruggedness
T j
T stg
Operating junction temperature range
Storage temperature range
Notes:
(1)
Limited by maximum junction temperature.
(2)
Pulse width limited by safe operating area
(3)
I
SD
≤ 8 A, di/dt≤100 A/μs; V
DS peak ≤ V
(BR)DSS
(4)
V
DS
≤ 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
Value
6.25
62.5
Value
2.7
240
Value Unit
± 30
8
5
32
20
V
A
A
A
W
V 2500
4.5
50
- 55 to
150
V/ns
°C
Unit
°C/W
°C/W
Unit
A mJ
DocID028981 Rev 1 3/13
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V
T
C
= 125 °C
(1)
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
DS
= 0 V, V
GS
V
DS
= V
GS
, I
D
= ±20 V
= 100 µA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 4 A
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V,
V
GS
= 0 V f = 1 MHz , I
D
= 0 A
V
DD
= 640 V, I
D
= 8 A
V
GS
= 10 V
(see Figure 16: "Test circuit for gate charge behavior" )
-
-
-
STFI10LN80K5
Min. Typ. Max. Unit
800 V
1 µA
50 µA
±10 µA
4 5 V
0.55 0.63
Ω
3
Min. Typ. Max. Unit
-
-
-
427
43
0.25
-
-
- pF pF pF
-
-
72
27
7
15
4.2
9
-
-
-
-
-
- pF
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS pF
Ω nC nC nC
4/13 DocID028981 Rev 1
STFI10LN80K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 400 V, I
D
= 4 A, R
G
= 4.7 Ω
V
GS
= 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform" )
Symbol
I
RRM
Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
Table 8: Source-drain diode
Test conditions
Reverse recovery current
I
SD
= 8 A, V
GS
= 0 V
I
SD
= 8 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 17: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
Min. Typ. Max. Unit
- 8 A
- 32 A
-
-
-
350
3.9
1.5 V ns
µC
-
11.8
10
28
13
22.5
-
-
-
- ns ns ns ns
A t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 8 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see Figure 17: "Test circuit for inductive load switching and diode recovery times" )
-
-
-
505
5
20 ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min Typ. Max Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1 mA, I
D
= 0 A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
DocID028981 Rev 1 5/13
Electrical characteristics
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
STFI10LN80K5
K
Figure 3: Thermal impedance
GC20940_ZTH
δ=0.5
δ=0.2
0.1
0.05
10
-1 0.02
0.01
Single pulse
10
-2
Figure 4: Output characteristics
10
-3
10
-4
10
-3
10
-2
10
-1
10
0 t p
(s)
Figure 5: Transfer characteristics
6/13
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
DocID028981 Rev 1
STFI10LN80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics
DocID028981 Rev 1 7/13
Electrical characteristics
Figure 14: Maximum avalanche energy vs starting T
J
STFI10LN80K5
8/13 DocID028981 Rev 1
STFI10LN80K5
3 Test circuits
Figure 15: Test circuit for resistive load switching times
Test circuits
Figure 16: Test circuit for gate charge behavior
Figure 17: Test circuit for inductive load switching and diode recovery times
Figure 18: Unclamped inductive load test circuit
Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform
DocID028981 Rev 1 9/13
Package information
4
4.1
Package information
STFI10LN80K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
I
2
PAKFP (TO-281) package information
Figure 21: I²PAKFP (TO-281) package outline
10/13 DocID028981 Rev 1
8291506 Re v. C
STFI10LN80K5
Dim.
H
L1
L2
L3
L4
L5
L6
E
F
F1
G
A
B
D
D1
Table 10: I²PAKFP (TO-281) mechanical data mm
Min. Typ.
4.40
2.50
2.50
0.65
0.45
0.75
4.95
10.00
21.00
13.20
10.55
2.70
0.85
7.50 7.60
Package information
Max.
10.40
23.00
14.10
10.85
3.20
1.25
7.70
4.60
2.70
2.75
0.85
0.70
1.00
1.20
5.20
DocID028981 Rev 1 11/13
Revision history
5
STFI10LN80K5
Revision history
Date
10-Feb-2016
Table 11: Document revision history
Revision
1
Changes
First release.
12/13 DocID028981 Rev 1
STFI10LN80K5
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DocID028981 Rev 1 13/13
