STD12N65M2
Nchannel 650 V, 0.42 Ω typ., 8 A MDmesh M2
Power MOSFET in a DPAK package
Datasheet - production data
DPAK (TO-252)
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on) max. I
D
STD12N65M2 650 V 0.5 Ω 8 A
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
Table 1: Device summary
Order code Marking Package Packing
STD12N65M2 12N65M2 DPAK
Tape and reel
February 2015 DocID027317 Rev 2
This is information on a product in full production.
1/16 www.st.com
Contents
Contents
STD12N65M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
DPAK (TO-252) type A package information................................... 10
DPAK (TO-252) packing information ............................................... 13
5 Revision history ............................................................................ 15
2/16 DocID027317 Rev 2
STD12N65M2
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt
(2) dv/dt
(3)
T stg
T j
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature
Operating junction temperature
Value
± 25
8
5
32
85
15
50
- 55 to 150 °C
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 8 A, di/dt ≤ 400 A/µs; V
DS peak
< V
(BR)DSS
, V
DD
= 400 V.
(3)
V
DS
≤ 520 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-pcb
Thermal resistance junction-case max
Thermal resistance junction-pcb max
(1)
Notes:
(1)
When mounted on 1 inch² FR-4, 2 Oz copper board.
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetetive or not repetetive (pulse width limited by
T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
; V
DD
= 50 V)
Value
1.47
50
Unit
°C/W
°C/W
Value Unit
1.6 A
250 mJ
Unit
V
A
A
A
W
V/ns
V/ns
DocID027317 Rev 2 3/16
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
GSDS
= 650 V
T
C
= 125 °C
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
V
V
DS
DS
= 0 V, V
= V
GS
, I
D
GS
= ±25 V
= 250 µA
R
DS(on)
Static drain-source onresistance
V
GS
= 10 V, I
D
= 4 A
Symbol
Drain-source breakdown voltage
Parameter
Table 6: Dynamic
Test conditions
C
C oss
C
R iss rss
G
Q g
Q gs
Q gd
C
oss eq.
(1)
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
GS
= 0 V, V
DS
= 100 V, f = 1 MHz
V
GS
= 0 V, V
DS
= 0 to 520 V f = 1 MHz, open drain
V
DD
= 520 V, I
D
= 8 A,
V
GS
= 10 V (see Figure 15:
"Gate charge test circuit" )
-
-
-
-
-
STD12N65M2
Min. Typ. Max. Unit
650 V
1 µA
100 µA
3
0.42
±10 µA
4 V
0.5
Ω
2
Min. Typ. Max. Unit
-
-
535
25
-
- pF pF
- 1.1 - pF
144
7
16.5
2.6
8.5
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
-
-
-
-
- pF
Ω nC nC nC
4/16 DocID027317 Rev 2
STD12N65M2
Symbol Parameter t t d(on) t t r f d(off)
Turn-on delay time
Rise time
Turn-offdelay time
Fall time
Table 7: Switching times
Test conditions
V
DD
= 325 V, I
D
= 4 A, R
G
= 4.7
Ω, V
GS
= 10 V
(see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
9
7
34
13.5
-
-
-
- ns ns ns ns
Table 8: Source drain diode
Test conditions Min. Typ. Max. Unit Symbol Parameter
I
I
SD
SDM
V
I
I
SD
t
Q
RRM t
Q rr rr rr rr
RRM
(1)
(2)
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
V
GS
= 0 V, I
SD
= 8 A
I
SD
= 8 A, di/dt = 100 A/µs, V
DD
= 60 V
(see Figure 16: " Test circuit for inductive load switching and diode recovery times" )
I
SD
= 8 A, di/dt = 100 A/µs, V
DD
= 60 V,
T j
= 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times" )
-
-
-
-
-
-
-
-
-
313
2.7
17
462
4.1
17.5
8
32
1.6
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
5/16 DocID027317 Rev 2
Electrical characteristics
2.1
STD12N65M2
Electrical characteristics (curves)
Figure 2: Safe operating area
GIPD161220141753M T
I
D
(A)
Figure 3: Thermal impedance
10µs
10
1 ra tion
O pe
Li m ited in
th is m ax ar ea
R by is
D
S
(on
)
100µs
1ms
10ms
0.1
0.01
0.1
1 10
Tj=150°C
Tc=25°C
Single pulse
100 V
DS
(V)
I D
(A)
Figure 4: Output characteristics
GIPD161220141803MT
V GS = 7, 8, 9, 10 V
6V
16
5V
12
I D
(A)
Figure 5: Transfer characteristics
GIPD161220141809MT
16
V DS = 18 V
12
8
4
4V
0
0 5 10 15 20 25 V DS (V)
Figure 6: Normalized gate threshold voltage vs temperature
8
4
0
0 2 4 6 8 V
GS
(V)
Figure 7: Normalized V (BR)DSS vs. temperature
6/16 DocID027317 Rev 2
STD12N65M2
Figure 8: Static drain-source on-resistance
GIPD161220141813MT
R DS(on)
(Ω)
V
GS
= 10V
0.44
0.43
0.42
0.41
0.40
0 2 4 6 8 I D (A)
Figure 10: Gate charge vs. gate-source voltage
V GS
(V)
GIPD161220141820MT
V DS (V)
V
DS
V DD = 520 V
12
I D = 8 A 500
10
400
8
300
6
200
4
100
2
0
0 4 8 12 16
0
Q g (nC)
Figure 12: Turn-off switching loss vs drain current
GIPD171220141020MT
E
(µJ)
4
3
2
1
0
0 100 200 300 400 500 600 V DS (V)
Electrical characteristics
Figure 9: Normalized on-resistance vs temperature
C
(pF)
Figure 11: Capacitance variations
GIPD161220141823MT
Ciss
1000
100
Coss
10
1
0.1
0.1
1 10 100
Crss
V DS (V)
Figure 13: Source-drain diode forward characteristic
GIPD161220141847MT
V SD
(V)
1.1
T j = -50°C
1
0.9
T j = 25°C
0.8
0.7
0.6
0.5
0 2 4 6
T j = 150°C
8 I SD (A)
DocID027317 Rev 2 7/16
Test circuits
3
STD12N65M2
Test circuits
Figure 14: Switching times test circuit for resistive load
Figure 15: Gate charge test circuit
V
DD
12 V
47 k
Ω
100 nF
1 k Ω
V i
≤ V
GS
2200 μ F
I G = CONST
2.7 k Ω
47 k
Ω
1 k Ω
P W
100 Ω
D.U.T.
V G
AM01469v 1
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
25
Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
L=100 µH
G
D
D.U.T.
S
3.3
µF
1000
µF
V
DD
Figure 18: Unclamped inductive waveform
V
(BR)DSS
V
D
V
DD
I
D
I
DM
AM01470v1
V
DD
AM01472v 1
0
0
Figure 19: Switching time waveform t on t off t d(on) t r t d(off) t f
90% 90%
10%
10%
V
DS
V
GS
90%
10% AM01473v 1
8/16 DocID027317 Rev 2
STD12N65M2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
DocID027317 Rev 2 9/16
Package information
4.1 DPAK (TO-252) type A package information
Figure 20: DPAK (TO-252) type A package outline
STD12N65M2
10/16 DocID027317 Rev 2
0068772_R
STD12N65M2
Dim.
E1 e e1
H c2
D
D1
E
A
A1
A2 b b4 c
L
L1
L2
L4
R
V2
Table 9: DPAK (TO-252) type A mechanical data
Package information mm
Typ. Min.
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
5.10
Max.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
6.40 6.60
4.70
2.28
4.40
9.35
1.00
0.60
2.80
0.80
4.60
10.10
1.50
0.20
1.00
0° 8°
DocID027317 Rev 2 11/16
Package information
Figure 21: DPAK (TO-252) type A recommended footprint
STD12N65M2
All dimensions are in mm
FP0068772_R
12/16 DocID027317 Rev 2
STD12N65M2
4.2 DPAK (TO-252) packing information
Figure 22: Tape for DPAK (TO-252)
Package information
DocID027317 Rev 2 13/16
Package information
Figure 23: Reel for DPAK (TO-252)
STD12N65M2
14/16
Dim.
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
E
F
1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 10: DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID027317 Rev 2
STD12N65M2
5
Revision history
Revision history
Date Revision
Table 11: Document revision history
Changes
16-Dec-2014
12-Feb-2015
1
2
First release.
Updated features in cover page.
Updated Table 4: "Avalanche characteristics" ,
Table 7: "Switching times" ,
Figure 2: "Safe operating area"
and Section 5.1: "DPAK (TO-
252) type A package information" .
Minor text changes.
DocID027317 Rev 2 15/16
STD12N65M2
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16/16 DocID027317 Rev 2
