STD6N90K5
Nchannel 900 V, 0.91 Ω typ., 6 A MDmesh™ K5
Power MOSFET in a DPAK package
Datasheet - production data
Features
Order code V
DS
R
DS(on)
max.
STD6N90K5 900 V 1.10 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
6 A
Figure 1: Internal schematic diagram
Order code
STD6N90K5
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Table 1: Device summary
Marking Package Packing
6N90K5 DPAK Tape and reel
October 2017 DocID029947 Rev 2
This is information on a product in full production.
1/18 www.st.com
Contents
Contents
STD6N90K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
4.3
DPAK (TO-252) type A2 package information................................. 10
DPAK (TO-252) type C2 package information ................................ 12
DPAK (TO-252) tape and reel mechanical data .............................. 15
5 Revision history ............................................................................ 17
2/18 DocID029947 Rev 2
STD6N90K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
D
(1)
P
TOT
dv/dt (2) dv/dt (3)
T j
T stg
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
Value
± 30
6
4
24
110
4.5
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
°C
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
SD
≤ 6 A, di/dt ≤ 100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 450 V.
(3)
V
DS
≤ 720 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Value
1.14
50
Unit
°C/W
°C/W
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2 oz Cu
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value Unit
2 A
210 mJ
DocID029947 Rev 2 3/18
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 900 V
I
DSS
Zero gate voltage drain current V
GS
= 0 V, V
DS
T
C
= 125 °C (1)
= 900 V
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
V
DS
DD
= 0 V, V
= V
GS
, I
GS
D
= ±20 V
= 100 µA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 3 A
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 720 V,
V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 720 V, I
D
= 6 A
V
GS
= 10 V
(see Figure 15: "Test circuit for gate charge behavior" )
STD6N90K5
Min. Typ. Max. Unit
900 V
1 µA
50 µA
±10 µA
4 5 V
0.91 1.10
Ω
3
Min. Typ. Max. Unit
-
-
-
342
31
1.2
-
-
- pF pF pF
-
-
-
-
-
-
55
20
6.4
11
2.5
7
-
-
-
-
-
- pF pF
Notes:
(1)
C o(tr)
is a constant capacitance value that gives the same charging time as C oss
while V
DS
is rising from 0 to
80% V
DSS
.
(2)
C o(er)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to
80% V
DSS
.
Ω nC nC nC
4/18 DocID029947 Rev 2
STD6N90K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 450 V, I
D
= 3 A, R
G
= 4.7 Ω
V
GS
= 10 V
(see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
12.4
12.2
30.4
15.5
-
-
-
- ns ns ns ns
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage
Reverse recovery time t rr
Q rr
Reverrse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 8: Source-drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
I
SD
= 6 A, V
GS
= 0 V
I
SD
= 6 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 6 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
6
24
342
3.13
18.3
536
4.42
1.5
16.5
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1 mA,I
D
= 0 A
Min. Typ. Max. Unit
30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
5/18 DocID029947 Rev 2
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STD6N90K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/18 DocID029947 Rev 2
STD6N90K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Maximum avalanche energy vs starting
TJ
Figure 13: Source-drain diode forward characteristics
DocID029947 Rev 2 7/18
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STD6N90K5
Figure 15: Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
8/18 DocID029947 Rev 2
STD6N90K5
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID029947 Rev 2 9/18
Package information
4.1 DPAK (TO-252) type A2 package information
Figure 20: DPAK (TO-252) type A2 package outline
STD6N90K5
10/18 DocID029947 Rev 2
STD6N90K5
Dim.
D1
E
E1 e e1
H
L
L1
L2
L4
R
V2 b4 c c2
D
A
A1
A2 b
Package information
Table 10: DPAK (TO-252) type A2 mechanical data mm
Min. Typ. Max.
4.95
6.40
5.10
2.16
4.40
9.35
1.00
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
2.60
0.65
0.60
0°
5.10
5.20
2.28
2.80
0.80
0.20
5.25
6.60
5.30
2.40
4.60
10.10
1.50
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
3.00
0.95
1.00
8°
DocID029947 Rev 2 11/18
Package information
4.2 DPAK (TO-252) type C2 package information
Figure 21: DPAK (TO-252) type C2 package outline
STD6N90K5
12/18 DocID029947 Rev 2
STD6N90K5
Dim.
D1
E
E1 e
H
L
L1
L2
L3
L4
L6
θ1
θ2
V2 b4 c c2
D
A
A1
A2 b
Package information
Table 11: DPAK (TO-252) type C2 mechanical data mm
Min. Typ. Max.
5.10
6.50
5.20
2.186
9.80
1.40
2.20
0.90
0.00
0.72
5.13
0.47
0.47
6.00
2.30
1.01
5.33
6.10
6.60
2.286
10.10
1.50
2.90 REF
5.60
6.70
5.50
2.386
10.40
1.70
2.38
1.10
0.10
0.85
5.46
0.60
0.60
6.20
0.90 1.25
0.60
5°
5°
0°
0.51 BSC
0.80
1.80 BSC
7°
7°
1.00
9°
9°
8°
DocID029947 Rev 2 13/18
Package information STD6N90K5
Figure 22: DPAK (TO-252) recommended footprint (dimensions are in mm)
14/18 DocID029947 Rev 2
STD6N90K5
4.3 DPAK (TO-252) tape and reel mechanical data
Package information
Figure 23: DPAK (TO-252) tape outline
DocID029947 Rev 2 15/18
Package information
Figure 24: DPAK (TO-252) reel outline
STD6N90K5
16/18
Dim.
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
E
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
2.55
3.9
Table 12: DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID029947 Rev 2
STD6N90K5
5 Revision history
Date
Table 13: Document revision history
Revision Changes
02-Nov-2016
18-Oct-2017
1
2
First release.
Updated Section 5: "Package information" .
Revision history
DocID029947 Rev 2 17/18
STD6N90K5
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18/18 DocID029947 Rev 2
