STMicroelectronics STU7N65M2 Datasheet
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STP7N65M2, STU7N65M2
Nchannel 650 V, 0.98 Ω typ., 5 A MDmesh™ M2
Power MOSFETs in TO-220 and IPAK packages
Datasheet - production data
TAB
IPAK
G(1)
1
2
3
TAB
TO-220 1
2
3
Figure 1: Internal schematic diagram
D(2, TAB)
Features
Order code
STP7N65M2
STU7N65M2
V
DS
R
DS(on) max
650 V
1.15 Ω
650 V
1.15 Ω
I
D
5 A
5 A
Extremely low gate charge
Excellent output capacitance (C oss
) profile
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
These devices are N-channel Power MOSFETs developed using the MDmesh™ M2 technology.
Thanks to the strip layout associated with an improved vertical structure, the device exhibits both low on-resistance and optimized switching characteristics. It is therefore suitable for the most demanding high efficiency converters.
S(3)
Order code
STP7N65M2
STU7N65M2
AM01476v1_tab
Table 1: Device summary
Marking Package
7N65M2
7N65M2
TO-220
IPAK
Packaging
Tube
Tube
May 2015 DocID026788 Rev 3
This is information on a product in full production.
1/18 www.st.com
Contents
Contents
STP7N65M2, STU7N65M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
4 Package information ..................................................................... 10
TO-220 type A package information ................................................ 11
IPAK(TO-251) type A package information ..................................... 13
IPAK (TO-251) type C package information .................................... 15
5 Revision history ............................................................................ 17
2/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
1 Electrical ratings
Symbol
V
GS
I
D
I
D
I
P
TOT
T stg
T j
Table 2: Absolute maximum ratings
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature
Operating junction temperature
Electrical ratings
Value
± 25
5
3.2
20
60
15
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
°C
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
SD
≤ 5 A, di/dt ≤ 400 A/µs; V
DSpeak
< V
(BR)DSS
, V
DD
=400 V
(3)
V
DS
≤ 520 V
Table 3: Thermal data
Value Unit
Symbol Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-ambient max
TO-220 IPAK
62.5
2.08
100
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
=25°C, I
D
= I
AR
; V
DD
=50 V)
°C/W
°C/W
Value Unit
1 A
103 mJ
DocID026788 Rev 3 3/18
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On /off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0, V
DS
= 650 V
V
GS
= 0, V
DS
= 650 V,
T
C
=125 °C
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
DS
= 0, V
GS
= ± 25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 2.5 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C
C
C oss rss
Q iss
C
R
G
Q g
Q gs gd
Input capacitance
Output capacitance V
DS
= 100 V, f = 1 MHz,
V
GS
= 0
Reverse transfer capacitance
Equivalent output capacitance
V
DS
= 0 to 520 V, V
GS
= 0
Intrinsic gate resistance f = 1 MHz open drain
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 520 V, I
D
= 5 A,
V
GS
= 10 V
(see Figure 17: "Gate charge test circuit" )
STP7N65M2, STU7N65M2
-
-
-
-
-
Min. Typ. Max. Unit
650
1
V
µA
100 µA
±10 µA
3 4 V
0.98 1.15 Ω
2
Min. Typ. Max. Unit
270 -
- 14.5 - pF
- 0.8 -
108
7
9
2.3
4.3
-
-
-
-
-
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
= 325 V, I
D
= 2.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
-
-
-
-
8
20
30
20
-
-
-
- ns ns ns ns pF
Ω nC nC nC
4/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
Symbol Parameter
I
SD
Source-drain current
I
Source-drain current
(pulsed)
V
Forward on voltage t
Q rr rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8: Source drain diode
Test conditions
I
SD
= 5 A, V
GS
= 0
I
SD
= 5 A, di/dt = 100 A/µs
V
DD
I
SD
= 5 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 21: "Switching time waveform" )
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Electrical characteristics
Min. Typ. Max. Unit
- 5 A
- 20 A
- 1.6 V
- 275 ns
- 1.62 µC
- 11.8 A
- 430 ns
- 2.54 µC
- 11.9 A
DocID026788 Rev 3 5/18
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area for TO-220
STP7N65M2, STU7N65M2
Figure 3: Thermal impedance for TO-220
6/18
Figure 4: Safe operating area for IPAK
K
Figure 5: Thermal impedance for IPAK
CG34360
Figure 6: Output characteristics
10
0 c
10
-1
-2
10
10
-5
10
-4
10
-3
10
-2
10
-1 t p
(s)
Figure 7: Transfer characteristics
DocID026788 Rev 3
STP7N65M2, STU7N65M2
Figure 8: Gate charge vs gate-source voltage
Electrical characteristics
Figure 9: Static drain-source on-resistance
Figure 10: Capacitance variations Figure 11: Output capacitance stored energy
Figure 12: Normalized gate threshold voltage vs temperature
Figure 13: Normalized on-resistance vs temperature
DocID026788 Rev 3 7/18
Electrical characteristics
Figure 14: Source-drain diode forward characteristics
STP7N65M2, STU7N65M2
Figure 15: Normalized V(BR)DSS vs temperature
8/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
3 Test circuits
Figure 16: Switching times test circuit for resistive load
Test circuits
Figure 17: Gate charge test circuit
Figure 18: Test circuit for inductive load switching and diode recovery times
Figure 19: Unclamped inductive load test circuit
Figure 20: Unclamped inductive waveform
Figure 21: Switching time waveform
DocID026788 Rev 3 9/18
Package information
4 Package information
STP7N65M2, STU7N65M2
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
10/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
4.1 TO-220 type A package information
Figure 22: TO-220 type A package outline
Package information
DocID026788 Rev 3 11/18
Package information
Dim. e1
F
H1
J1
L
L1
L20
D
D1
E e
A b b1 c
L30
øP
Q
STP7N65M2, STU7N65M2
Table 9: TO-220 type A mechanical data mm
Min. Typ. Max.
4.40
0.61
1.14
0.48
15.25
1.27
4.60
0.88
1.70
0.70
15.75
10
2.40
4.95
1.23
6.20
2.40
13
3.50
3.75
2.65
16.40
28.90
10.40
2.70
5.15
1.32
6.60
2.72
14
3.93
3.85
2.95
12/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
4.2 IPAK(TO-251) type A package information
Figure 23: IPAK (TO-251) type A package outline
Package information
DocID026788 Rev 3 13/18
e1
H
L c2
D
E e
A
A1 b b2 b4
B5 c
L1
L2
V1
Package information
Dim.
STP7N65M2, STU7N65M2
Table 10: IPAK (TO-251) type A package mechanical data mm
Min. Typ. Max.
2.20
0.90
0.64
5.20
2.40
1.10
0.90
0.95
5.40
0.30
0.45
0.48
6.00
6.40
0.60
0.60
6.20
6.60
2.28
4.40
4.60
16.10
9.00
0.80
0.80
10°
9.40
1.20
1.00
14/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
4.3 IPAK (TO-251) type C package information
Figure 24: IPAK (TO-251) type C package outline
Package information
0068771_IK_typeC_rev13
DocID026788 Rev 3 15/18
Package information
Dim. b4 c c2
A
A1 b b2
D
D1
E
E1 e e1
H
L
L1
L2
ϑ1
ϑ2
STP7N65M2, STU7N65M2
Table 11: IPAK (TO-251) type C package mechanical data mm
Min. Typ. Max.
2.20
0.90
0.66
5.23
0.46
0.46
6.00
2.30
1.00
5.33
6.10
2.35
1.10
0.79
0.90
5.43
0.59
0.59
6.20
5.20
6.50
4.60
2.20
5.37
6.60
4.78
2.25
5.55
6.70
4.95
2.30
4.40
16.18
9.00
0.90
0.90
3°
1°
4.50
16.48
9.30
1.00
1.08
5°
3°
4.60
16.78
9.60
1.20
1.25
7°
5°
16/18 DocID026788 Rev 3
STP7N65M2, STU7N65M2
5
Revision history
Revision history
Date Revision
Table 12: Document revision history
Changes
07-Aug-2014
09-Oct-2014
28-May-2015
1
2
3
First release.
Added and .
Updated not found.
Minor text changes.
Document status promoted form preliminary to production data.
Updated package information.
DocID026788 Rev 3 17/18
STP7N65M2, STU7N65M2
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© 2015 STMicroelectronics
– All rights reserved
18/18 DocID026788 Rev 3
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