STU6N90K5
Nchannel 900 V, 0.91 Ω typ., 6 A MDmesh™ K5
Power MOSFET in an IPAK package
Datasheet - production data
TAB
IPAK
1
2
3
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max.
STU6N90K5 900 V 1.10 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
6 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STU6N90K5
Table 1: Device summary
Marking Package
6N90K5 IPAK
Packing
Tube
November 2016 DocID029950 Rev 1
This is information on a product in full production.
1/12 www.st.com
Contents
Contents
STU6N90K5
1 Electrical ratings ............................................................................... 3
2 Electrical characteristics ................................................................. 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ...................................................................................... 8
4 Package information ........................................................................ 9
4.1
IPAK (TO-251) type C package information ...................................... 9
5 Revision history .............................................................................. 11
2/12 DocID029950 Rev 1
STU6N90K5
1
Electrical ratings
Symbol
V
GS
I
D
I
D
I
D
(1)
P
TOT
dv/dt (2) dv/dt (3)
T j
T stg
Electrical ratings
Table 2: Absolute maximum ratings
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
SD
≤ 6 A, di/dt ≤ 100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 450 V.
(3)
V
DS
≤ 720 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
Value
± 30
6
4
24
110
4.5
50
- 55 to 150
Value
1.14
100
Value
2
210
°C
Unit
°C/W
°C/W
Unit
V
A
A
A
W
V/ns
Unit
A mJ
DocID029950 Rev 1 3/12
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
GS
= 0 V, V
DS
= 900 V
V
GS
= 0 V, V
DS
= 900 V
T
C
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±20 V
V
DD
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 3 A
STU6N90K5
Min. Typ. Max. Unit
900 V
1 µA
50 µA
4
±10 µA
5 V
0.91 1.10 Ω
3
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 720 V,
V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 720 V, I
D
= 6 A
V
GS
= 10 V
(see Figure 15: "Test circuit for gate charge behavior" )
-
-
-
-
Min. Typ. Max. Unit
-
-
-
342
31
1.2
-
-
- pF pF pF
-
-
55
20
6.4
11
2.5
7
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
C o(tr)
is a constant capacitance value that gives the same charging time as C oss
while V
DS
is rising from 0 to
80% V
DSS
.
(2)
C o(er)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to
80% V
DSS
.
4/12 DocID029950 Rev 1
STU6N90K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 450 V, I
D
= 3 A,
R
G
= 4.7 Ω
V
GS
= 10 V
(see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
- 12.4
- 12.2
- 30.4
- 15.5
-
-
-
- ns ns ns ns
Symbol
I
SD
Parameter
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverrse recovery charge
I
RRM
Table 8: Source-drain diode
Test conditions
Reverse recovery current
I
I
SD
= 6 A, V
GS
= 0 V
SD
V
= 6 A, di/dt = 100 A/µs,
DD
= 60 V
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Min. Typ. Max. Unit
-
-
-
- 342
- 3.13
- 18.3
6
24
1.5
A
A
V ns
µC
A t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 6 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
- 536
- 4.42
- 16.5 ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min. Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1 mA,I
D
= 0 A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
DocID029950 Rev 1 5/12
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STU6N90K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/12 DocID029950 Rev 1
STU6N90K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Maximum avalanche energy vs starting T
J
Figure 13: Source-drain diode forward characteristics
DocID029950 Rev 1 7/12
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STU6N90K5
Figure 15: Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
Figure 16: Test circuit for inductive load switching and diode recovery times
AM01469v10
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
8/12 DocID029950 Rev 1
STU6N90K5
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
IPAK (TO-251) type C package information
Figure 20: IPAK (TO-251) type C package outline
0068771_IK_typeC_rev14
DocID029950 Rev 1 9/12
Package information
Dim.
D
D1
E
E1 e e1
H
L
L1
L2
θ1
θ2
A
A1 b b2 b4 c c2
STU6N90K5
Table 10: IPAK (TO-251) type C package mechanical data mm
Min.
2.20
0.90
0.66
Typ.
2.30
1.00
5.33
2.20
4.40
16.18
9.00
0.90
0.90
3°
1°
5.23
0.46
0.46
6.00
5.20
6.50
4.60
6.10
5.37
6.60
4.78
2.25
4.50
1.08
5°
3°
16.48
9.30
1.00
5.43
0.59
0.59
6.20
5.55
6.70
4.95
Max.
2.35
1.10
0.79
0.90
2.30
4.60
16.78
9.60
1.20
1.25
7°
5°
10/12 DocID029950 Rev 1
STU6N90K5
5
Revision history
Revision history
Date
02-Nov-2016
Table 11: Document revision history
Revision
1
Changes
First release.
DocID029950 Rev 1 11/12
STU6N90K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics
– All rights reserved
12/12 DocID029950 Rev 1
