STMicroelectronics STWA40N95K5 Datasheet
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STWA40N95K5
Nchannel 950 V, 0.110 Ω typ., 38 A MDmesh™ K5
Power MOSFET in a TO-247 long leads package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2, TAB)
G(1)
Features
Order code V
DS
R
DS(on)
max I
D
P
TOT
STWA40N95K5 950 V
0.130 Ω
38 A 450 W
Industry’s lowest R
DS(on)
x area
Industry’s best figure of merit (FoM)
Ultra low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STWA40N95K5
S(3)
AM01476v1
Table 1: Device summary
Marking Package
40N95K5 TO-247
Packaging
Tube
August 2015 DocID028207 Rev 1
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STWA40N95K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
Electrical characteristics (curves) ...................................................... 6
4 Package mechanical data ............................................................. 10
TO-247 long leads package information ......................................... 10
5 Revision history ............................................................................ 12
2/13 DocID028207 Rev 1
STWA40N95K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
P
TOT
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
I
AR
Max current during repetitive or single pulse avalanche
E
AS
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
= 13 A, V
DD
= 50 V)
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
T j
T stg
Operating junction temperature
Storage temperature
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 19 A, di/dt ≤ 100 A/µs, V
DS(peak)
≤ V
(BR)DSS.
(3)
V
DS
≤ 760 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-amb max
Electrical ratings
Value
± 30
38
24
152
450
13
700
4.5
50
-55 to 150 mJ
V/ns
V/ns
°C
Unit
V
A
A
A
W
A
Value
0.28
50
Unit
°C/W
°C/W
DocID028207 Rev 1 3/13
Electrical characteristics
2 Electrical characteristics
(T case
=25 °C unless otherwise specified)
Symbol Parameter
Table 4: On /off states
Test conditions
V
(BR)DSS
I
DSS
I
GSS
Drain-source breakdown voltage
V
GS
= 0, I
D
= 1 mA
V
GS
= 0, V
DS
= 950 V
Zero gate voltage drain current
V
GS
= 0, V
DS
= 950 V,
T
C
=125 °C
Gate-body leakage current V
DS
=0, V
GS
= ± 20 V
V
DS
= V
GS
, I
D
= 100 µA V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on- resistance
V
GS
= 10 V, I
D
= 19 A
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
C
C
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
GS
=0, V
DS
=100 V, f=1 MHz
V
GS
= 0, V
DS
= 0 to 760 V f = 1 MHz, I
D
=0
V
DD
= 760 V, I
D
= 38 A
V
GS
=10 V
(see Figure 16: "Gate charge test circuit" )
STWA40N95K5
Min. Typ. Max. Unit
950
3 4
2
398
142
5
93
18.7
63.4
1
50
V
µA
µA
±10 µA
5 V
0.110 0.130 Ω
Min. Typ. Max. Unit
-
-
3300
250
-
- pF pF
-
-
-
-
-
-
-
-
-
-
-
-
-
- pF pF pF
Ω nC nC nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
(2) energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 6: Switching times
Test conditions Min. Typ. Max Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off-delay time t f
Fall time
V
DD
= 475 V, I
D
= 19 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 15: "Switching times test circuit for resistive load" )
- 33.5 -
- 51 -
- 91.5 -
- 10 - ns ns ns ns
4/13 DocID028207 Rev 1
STWA40N95K5
Symbol
I
SD
Source-drain current
I
Source-drain current
(pulsed)
V
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 7: Source drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
I
SD
= 38 A, V
V
DD
= 60 V
GS
= 0
I
SD
= 38 A, di/dt = 100 A/µs
(see Figure 18: "Unclamped inductive load test circuit" )
I
SD
= 38 A, di/dt = 100 A/µs
V
DD
= 60 V T
J
= 150 °C
(see Figure 18: "Unclamped inductive load test circuit" )
Electrical characteristics
Min. Typ. Max Unit
- 38 A
- 152 A
-
-
-
706
22
1.5 V ns
µC
- 62
- 886
- 28.2
- 64
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 8: Gate-source Zener diode
Parameter Test conditions Min Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1mA, I
D
=0 30 - -
The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated
Zener diodes thus avoid the usage of external components.
V
DocID028207 Rev 1 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STWA40N95K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/13 DocID028207 Rev 1
STWA40N95K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance
GIPD121120141039FSR
R DS(on)
(norm)
2.6
V
GS
= 10V
2.2
1.8
1.4
1
Figure 11: Normalized V(BR)DSS vs temperature
GIPD121120141041FSR
V (BR)DSS
(norm)
1.12
I
D
= 1m A
1.08
1.04
1.00
0.96
0.6
0.2
-50 0 50 100 T j
(°C)
Figure 12: Output capacitance stored energy
0.92
0.88
-50 0 50 100 T j
(°C)
Figure 13: Source-drain diode forward characteristics
DocID028207 Rev 1 7/13
Electrical characteristics
Figure 14: Maximum avalanche energy vs T J
GIPD141120141040FSR
E AS
(mJ)
600
STWA40N95K5
400
200
Single pulse
I
D
= 13 A
V DD = 50V
0
-50 0 50 100 T j (°C)
8/13 DocID028207 Rev 1
STWA40N95K5
3 Test circuits
Figure 15: Switching times test circuit for resistive load
Test circuits
Figure 16: Gate charge test circuit
Figure 17: Test circuit for inductive load switching and diode recovery times
Figure 18: Unclamped inductive load test circuit
Figure 19: Unclamped inductive waveform
Figure 20: Switching time waveform
DocID028207 Rev 1 9/13
Package mechanical data
4
4.1
Package mechanical data
STWA40N95K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
TO-247 long leads package information
Figure 21: TO-247 long leads package outline
10/13 DocID028207 Rev 1
STWA40N95K5
Dim.
E
E2
E3 e
L
L1
P
Q
S b2 b3 c
D
A
A1
A2 b
Package mechanical data
Table 9: TO-247 long leads package mechanical data mm.
Min. Typ. Max.
4.90
2.31
1.90
1.16
0.59
20.90
15.70
4.90
2.40
5.34
19.80
3.50
5.60
6.05
5.00
2.41
2.00
21.00
15.80
5.00
2.50
5.44
19.92
3.60
6.15
15.90
5.10
2.60
5.54
20.10
4.30
3.70
6.00
6.25
5.10
2.51
2.10
1.26
3.25
2.25
0.66
21.10
DocID028207 Rev 1 11/13
Revision history
5
STWA40N95K5
Revision history
Date
05-Aug-2015
Table 10: Document revision history
Revision
1
Changes
First release.
12/13 DocID028207 Rev 1
STWA40N95K5
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