STL8N6LF3
Automotive-grade Nchannel 60 V, 22.5 mΩ typ., 7.8 A
STripFET™ F3 Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max. I
D
STL8N6LF3 60 V 30 mΩ
AEC-Q101 qualified
Logic level V
GS(th)
175 °C maximum junction temperature
100% avalanche rated
Wettable flank package
7.8 A
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance.
Order code
STL8N6LF3
Marking
8N6LF3
Table 1: Device summary
Package
PowerFLAT™ 5x6
Packing
Tape and reel
May 2017 DocID027037 Rev 3
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STL8N6LF3
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT 5x6 WF type R package information ............................. 9
Packing information ......................................................................... 12
5 Revision history ............................................................................ 14
2/15 DocID027037 Rev 3
STL8N6LF3
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
(1)
I
D
I
D
(3)
I
D
(3)
I
DM
(2)(3)
P
TOT
P
TOT
(3)
I
AS
E
AS
(4)
T j
T stg
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Total dissipation at T pcb
= 25°C
Not-repetitive avalanche current
Single pulse avalanche energy
Operating junction temperature range
Storage temperature range
-55 to 175
Notes:
(1)
Current is limited by bonding, with an R thJC
= 2.3 °C/W the chip is able to carry 30 A at 25 °C.
(2)
Pulse width limited by safe operating area.
(3)
When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 s.
(4)
Starting T
J
= 25 °C, I
D
=I
AS
, V
DD
= 25 V.
Symbol
Table 3: Thermal resitance
Parameter Value
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
2.3
35
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.
Value
5.5
31.2
65
4.3
7.8
190
60
±20
20
20
7.8
Unit
°C/W
°C/W
Unit
A
A
W
W
A mJ
V
V
A
A
A
°C
DocID027037 Rev 3 3/15
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4: On/Off states
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
Zero gate voltage drain current
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
GS
= 0 V, I
D
= 250 μA
V
GS
= 0 V, V
DS
= 60 V
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= 10 V, I
D
= 4 A
V
GS
= 5 V, I
D
= 4 A
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
R
G t f
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Intrinsic gate resistance
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time
Fall time
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 30 V, I
D
= 7.8 A,
V
GS
= 0 to 10 V
(see Figure 14: "Test circuit for gate charge behavior" )
f =1 MHz, I
D
=0 A
Table 6: Switching times
Test conditions
V
DD
= 30 V, I
D
= 4 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
STL8N6LF3
Min. Typ. Max. Unit
60
1
Min. Typ. Max. Unit
-
-
668
144
-
- pF
- 14 -
-
-
-
-
13
2.4
3
-
-
-
Min. Typ. Max. Unit
- 9 -
-
-
7.7
32.5
-
- ns
-
±100 nA
2.5 V
22.5 30 mΩ
30 44 mΩ
4
5
1
-
-
V
µA nC
Ω
4/15 DocID027037 Rev 3
STL8N6LF3
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Reverse recovery time
Q rr
Reverse recovery charge
I
RRM
Parameter
Table 7: Source-drain diode
Test conditions
Reverse recovery current
I
I
DS
SD
= 7.8 A, V
GS
= 0 V
= 7.8 A, di/dt = 100 A/µs
V
DD
= 48 V, T j
= 150 °C (see
Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 7.8 A
- 31.2 A
-
-
-
30
35
1.3 V ns nC
- 2.35 A
Notes:
(1)
Pulse width limited by safe operating area.
(2) Pulsed: pulse duration = 300 μs, duty cycle 1.5 %.
DocID027037 Rev 3 5/15
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL8N6LF3
Figure 3: Thermal impedance d
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Normalized V
(BR)DSS
vs temperature
Figure 7: Static drain-source on-resistance
6/15 DocID027037 Rev 3
STL8N6LF3
Figure 8: Gate charge vs gate-source voltage
Electrical characteristics
Figure 9: Capacitance variation
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Source-drain diode forward characteristics
DocID027037 Rev 3 7/15
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STL8N6LF3
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
8/15 DocID027037 Rev 3
STL8N6LF3
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerFLAT 5x6 WF type R package information
Figure 19
: PowerFLAT™ 5x6 WF type R package outline
DocID027037 Rev 3
8231817_R_WF_Rev_15
9/15
Package information
Dim.
D4
D5
D6 e
E
E2
E3
C
D
D2
D3
A
A1
A2 b
E4
E5
E6
E7
E9
E10
K
L
L1
ϴ
STL8N6LF3
Table 8:
PowerFLAT™ 5x6 WF type R mechanical data mm
Min. Typ.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.4
0.3
1.27
6.40 6.20
3.50
2.35
0.40
0.08
0.20
0.85
4.00
3.55
1.275
0.725
0.175
0°
0.325
1.00
4.20
3.70
0.825
0.275
Max.
1.00
0.05
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
6.60
3.70
2.55
0.60
0.28
0.45
1.15
4.40
3.85
1.575
0.925
0.375
12°
10/15 DocID027037 Rev 3
STL8N6LF3 Package information
Figure 20
: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_rev15
DocID027037 Rev 3 11/15
Package information
4.2 Packing information
Figure 21
: PowerFLAT™ 5x6 WF tape (dimensions are in mm)
STL8N6LF3
Figure 22
: PowerFLAT™ 5x6 package orientation in carrier tape
12/15 DocID027037 Rev 3
STL8N6LF3 Package information
Figure 23
: PowerFLAT™ 5x6 reel (dimensions are in mm)
DocID027037 Rev 3 13/15
Revision history
5
STL8N6LF3
Revision history
Date Revision
Table 9: Document revision history
Changes
13-Oct-2014
23-Nov-2015
11-May-2017
1
2
3
First release.
Updated title.
Datasheet promoted from preliminary data to production data.
Updated Section 4: Package information.
Minor text changes.
Modified Figure 6: "Normalized V(BR)DSS vs temperature"
and Figure
11: "Normalized on-resistance vs temperature" .
Updated Section 4: "Package information"
Minor text changes.
14/15 DocID027037 Rev 3
STL8N6LF3
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DocID027037 Rev 3 15/15
