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ISD91200 Series Technical Reference Manual
5.6.4 I2C Protocol Registers
The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL
(control register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address registers, n=0~3), I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register) and I2C_TOCTL (Time-out counter register). Bits 31~ bit 8 of these I2C special function registers are reserved. These bits do not have any functions and are all zero if read back.
When I2C port is enabled by setting I2CEN (I2C_CTL[6]) to high, the internal states will be controlled by
I2C_CTL and I2C logic hardware. Once a new status code is generated and stored in I2C_STATUS, the I2C Interrupt Flag bit SI (I2C_CTL[3]) will be set automatically. If the Enable Interrupt bit INTEN
(I2C_CTL[7]) is set high at this time, the I2C interrupt will be generated. The bit field I2C_STATUS[7:3] stores the internal state code, the lowest 3 bits of I2C_STATUS are always zero and the contents are stable until SI is cleared by software. The base address of the I2C peripheral on theISD91200 is
0x4002_0000.
5.6.4.1 Address Registers (I2C_ADDR)
I2C port is equipped with four slave address registers I2C_ADDRn (n=0~3). The contents of the register are irrelevant when I2C is in master mode. In the slave mode, the bit field I2C_ADDRn[7:1] must be loaded with the MCU’s own slave address. The I2C hardware will react if the contents of I2C_ADDR are matched with the received slave address.
The I2C ports support the “General Call” function. If the GC bit (I2C_ADDRn[0]) is set the I2C port hardware will respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the I2C is in Slave mode, it can be received the general call address by 00H after
Master send general call address to I2C bus, then it will follow status of GC mode. If it is in master mode, the AA bit (I2C_CTL[2], Assert Acknowledge control bit) must be cleared when it will send general call address of 00H to I2C bus.
I2C-bus controllers support multiple address recognition with four address mask registers I2ADRMn
(n=0~3). When the bit in the address mask register is set to one, it means the received corresponding address bit is don’t-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
5.6.4.2 Data Register (I2C_DAT)
This register contains a byte of serial data to be transmitted or a byte which has just been received. The
CPU can read from or write to this 8-bit (I2C_DAT[7:0]) directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag (SI) is set. Data in I2C_DAT[7:0] remains stable as long as SI bit is set. While data is being shifted out, data on the bus is simultaneously being shifted in; I2C_DAT[7:0] always contains the last data byte present on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in I2C_DAT[7:0].
I2C_DAT[7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the SIO hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge bit into I2C_DAT[7:0] on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into I2C_DAT[7:0], the serial data is available in I2C_DAT[7:0], and the acknowledge bit (ACK or
NACK) is returned by the control logic during the ninth clock pulse. Serial data is shifted out from
I2C_DAT[7:0] on the falling edges of SCL clock pulses, and is shifted into I2C_DAT[7:0] on the rising edges of SCL clock pulses.
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Release Date: Sep 16, 2019
Revision 2.4
ISD91200 Series Technical Reference Manual
I2C Data Register:
DATA.7 DATA.6 DATA.5 DATA.4 DATA.3 DATA.2 DATA.1 DATA.0
shifting direction
Figure 5-22 I2C Data Shift Direction
5.6.4.3 Control Register (I2C_CTL)
The CPU can read from and write to this 8-bit field of I2C_CTL[7:0]. Two bits are affected by hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is cleared when a
STOP condition is present on the bus. The STO bit is also cleared when I2CEN = "0".
INTEN Enable Interrupt.
I2CEN
STA
STO
Set to enable I2C serial function block. When I2CEN=1 the I2C serial function is enabled.
I2C START Control Bit. Setting STA to logic 1 enters master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
I2C STOP Control Bit. In master mode, setting STO transmits a STOP condition to the bus.
The I2C hardware will check the bus condition and if a STOP condition is detected this flag will be cleared by hardware. In a slave mode, setting STO resets I2C hardware to the defined “not addressed” slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
SI
AA
I2C Interrupt Flag. When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested.
SI must be cleared by software. Clear SI is by writing one to this bit.
Assert Acknowledge Control Bit. When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:
1.) A slave is acknowledging the address sent from master,
2.) A receiver device is acknowledging the data sent by a transmitter.
When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
5.6.4.4 Status Register (I2C_STATUS)
I2C_STATUS[7:0] is an 8-bit read-only register. The three least significant bits are always 0. The bit field I2C_STATUS[7:3] contains the status code. There are 26 possible status codes. When
I2C_STATUS[7:0] contains F8H, no serial interrupt is requested. All other I2C_STATUS[7:3] values correspond to defined SIO states. When each of these states is entered, a status interrupt is requested
(SI = 1). A valid status code is present in I2C_STATUS[7:3] one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software.
In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. To recover I2C from bus error, STO should be set and SI should be clear to enter not addressed slave mode. Then clear STO to release bus and to wait new communication. I2C bus cannot recognize stop condition during this action when bus error occurs.
5.6.4.5 I2C Clock Baud Rate Bits (I2C_CLKDIV)
The data baud rate of I2C is determined by I2C_CLKDIV[7:0] register when SIO is in a master mode. It is not important when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize
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Release Date: Sep 16, 2019
Revision 2.4
ISD91200 Series Technical Reference Manual with any clock frequency up to 1M Hz from master I2C device.
Data Baud Rate of I2C = PCLK /(4x(I2C_CLKDIV[7:0]+1)). If PCLK=16MHz, the I2C_CLKDIV[7:0] = 40
(28H), data baud rate of I2C = 16MHz/(4x(40 +1)) = 97.5Kbits/sec.
5.6.4.6 The I2C Time-out Counter Register (I2C_TOCTL)
There is a 14-bit time-out counter which can be configured to deal with an I2C bus hang-up. If the timeout counter is enabled, the counter starts up-counting until it overflows (TOIF=1) and generates I2C interrupt to CPU or stops counting by clearing TOCEN to 0. When time-out counter is enabled, setting flag SI to high will reset counter. Counter will re-start after SI is cleared. If the I2C bus hangs up,
counter will overflow and generate a CPU interrupt. Refer to Figure 5-23 I2C Time-out Count Block
Diagram for the 14-bit time-out counter. User can clear TOIF by writing one to this bit.
Pclk
1/4
DIV4
0
1
Enabl e
I2CEN
TOCEN
14-bit Counter
Clear Counter
TOIF
SI
SI
Figure 5-23 I2C Time-out Count Block Diagram
To I2C Interrupt
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Release Date: Sep 16, 2019
Revision 2.4
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