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ISD91200 Series Technical Reference Manual
Detection Time Multiplex Register (BOD_BODDTMR)
The BOD detector can be set up to take periodic samples of the supply voltage to minimize power consumption. The circuit can be configured and used in Standby Power Down (SPD) mode and can wake up the device if a BOD is event detected. The detection timer uses the OSC10k oscillator as time base so this oscillator must be active for timer operation. When active the BOD circuit requires ~165uA.
With default timer settings, average current reduces to 500nA
165uA*DURTON/(DURTON+DURTOFF).
Register
BOD_BODDTMR
Offset
BOD_BA+0x10
R/W Description
R/W Brown Out Detector Timer Register
Reset Value
0x0003_03E3
Table 5-61 Detection Time Multiplex Register (BOD_BODDTMR, address 0x4008_4010)
31 30 29 28 27 26 25
Reserved
23
15
22
14
Reserved
21
13
20 19 18 17
DURTON[3:0]
10 9
7 6 5
12 11
DURTOFF[15:8]
4 3
DURTOFF[7:0]
2 1
Bits
[31:20]
Description
Reserved
[19:16]
[15:0]
DURTON
DURTOFF
Reserved.
Time BOD Detector Is Active
(DURTON+1) * 100us. Minimum value is 1. (default is 400us)
Time BOD Detector Is Off
(DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)
24
16
8
0
5.6 I2C Serial Interface Controller (Master/Slave)
5.6.1 Introduction
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented, bi-directional data transfers can be made up 1.0 Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-bybyte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).
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Release Date: Sep 16, 2019
Revision 2.4
ISD91200 Series Technical Reference Manual
STOP START
Repeated
START STOP
SDA t
BUF t
LOW t r t f
SCL t
HD;STA t
HIGH t
HD;DAT t
SU;DAT t
SU;STA t
SU;STO
Figure 5-9 I2C Bus Timing
The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. To enable this port, the bit I2CEN in
I2C_CTL should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: I2C_SDA and
I2C operation as these are open drain pins.
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are:
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and timerout counter overflows.
External pull-up are needed for high output
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
I2C-bus controllers support multiple address recognition ( Four slave address with mask option)
5.6.1.1 I
2
C Protocol
Normally, a standard communication consists of four parts:
1) START or Repeated START signal generation
2) Slave address transfer
3) Data transfer
4) STOP signal generation
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Release Date: Sep 16, 2019
Revision 2.4
ISD91200 Series Technical Reference Manual
SCL
1 2 7 8 9 1 2 3 - 7 8 9
P
SDA
S or
Sr
A6
MSB
A5 A4 - A1 A0 R/W
LSB
ACK D7
MSB
D6 D5 - D1 D0
LSB
NACK
ACK
Figure 5-10 I2C Protocol
5.6.1.2 Data transfer on the I2C-bus
A master-transmitter always begins by addressing a slave receiver with a 7-bit address. For a transaction where the master-transmitter is sending data to the slave, the transfer direction is not changed, master is always transmitting and slave acknowledges the data.
P or
Sr
Sr
S SLAVE ADDRESS R/W A DATA A DATA A/A P data transfer
(n bytes + acknowledge)
'0'(write) from master to slave from slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = START condition
P = STOP condition
Figure 5-11 Master Transmits Data to Slave
For a master to read data from a slave, master addresses slave with the R/W bit set to ‘1’, immediately after the first byte (address) is acknowledged by the slave the transfer direction is changed and slave sends data to the master and master acknowledges the data transfer.
S SLAVE ADDRESS R/W A DATA A DATA A P data transfer
(n bytes + acknowledge)
'1'(read)
Figure 5-12 Master Reads Data from Slave
5.6.1.3 START or Repeated START signal
When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer.
A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus.
STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.
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Release Date: Sep 16, 2019
Revision 2.4
ISD91200 Series Technical Reference Manual
SCL
SDA
START condition STOP condition
Figure 5-13 START and STOP condition
5.6.1.4 Slave Address Transfer
The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle.
5.6.1.5 Data Transfer
Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle.
If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases the
SDA line for the master to generate a STOP or Repeated START signal.
SCL
SDA data line stable; data valid change of data allowed
Figure 5-14 Bit Transfer on the I2C bus
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Release Date: Sep 16, 2019
Revision 2.4
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