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ISD91200 Series Technical Reference Manual
6.9 Register Map
R : read only, W : write only, R/W : both read and write
R/W Description Register Offset
FMC Base Address:
FMC_BA=0x5000_C000
FMC_ISPCTL FMC_BA+0x00
FMC_ISPADDR FMC_BA+0x04
R/W ISP Control Register
R/W ISP Address Register
FMC_ISPDAT
FMC_ISPCMD
FMC_ISPTRG
FMC_DFBA
FMC_BA+0x08
FMC_BA+0x0C
FMC_BA+0x10
FMC_BA+0x14
R/W ISP Data Register
R/W ISP Command Register
R/W ISP Trigger Control Register
R Data Flash Base Address
Reset Value
0x0002_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_XXXX
- 363 -
Release Date: Sep 16, 2019
Revision 2.4
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Table of contents
- 2 TABLE OF CONTENTS
- 9 GENERAL DESCRIPTION
- 10 FEATURES
- 14 PART INFORMATION AND PIN CONFIGURATION
- 14 Pin Configuration
- 15 Pin Description
- 20 BLOCK DIAGRAM
- 21 FUNCTIONAL DESCRIPTION
- 21 Cortex™-M0 core
- 23 System Manager
- 23 Overview
- 23 System Reset
- 24 System Power Distribution
- 25 System Memory Map
- 27 System Manager Control Registers
- 51 System Timer (SysTick)
- 55 Nested Vectored Interrupt Controller (NVIC)
- 101 System Control Registers
- 109 Clock Controller and Power Management Unit (PMU)
- 109 Clock Generator
- 110 System Clock & SysTick Clock
- 111 Peripheral Clocks
- 111 Power Management
- 113 Register Map
- 114 Register Description
- 131 General Purpose I/O
- 131 Overview and Features
- 131 GPIO I/O Modes
- 133 GPIO Control Register Map
- 134 Register Description
- 144 Brownout Detection and Temperature Alarm
- 144 Brownout Register Map
- 145 Brownout Register Description
- 148 I2C Serial Interface Controller (Master/Slave)
- 148 Introduction
- 152 Modes of Operation
- 153 Data Transfer Flow in Five Operating Modes
- 159 I2C Protocol Registers
- 162 Register Mapping
- 163 Register Description
- 170 PWM Generator and Capture Timer
- 170 Introduction
- 170 Features
- 172 PWM Generator Architecture
- 172 PWM-Timer Operation
- 174 PWM Double Buffering, Auto-reload and One-shot Operation
- 174 Modulate Duty Cycle
- 175 Dead-Zone Generator
- 176 Capture Timer Operation
- 177 PWM-Timer Interrupt Architecture
- 177 PWM-Timer Initialization Procedure
- 177 PWM-Timer Stop Procedure
- 178 Capture Start Procedure
- 179 Register Map
- 181 Register Description
- 198 Real Time Clock (RTC) Overview
- 198 RTC Features
- 199 RTC Block Diagram
- 199 RTC Function Description
- 202 Register Map
- 203 Register Description
- 216 Serial 0 Peripheral Interface (SPI0) Controller
- 216 Overview
- 216 Features
- 216 SPI0 Block Diagram
- 217 SPI0 Function Descriptions
- 227 SPI Timing Diagram
- 230 SPI Configuration Examples
- 232 Register Map
- 233 Register Description
- 248 Serial 1 Peripheral Interface (SPI1) Controller
- 248 Overview
- 248 Features
- 248 SPI1 Block Diagram
- 249 SPI1 Function Descriptions
- 255 SPI Timing Diagram
- 258 SPI Configuration Examples
- 260 Register Map
- 261 Register Description
- 272 Timer Controller
- 272 General Timer Controller
- 272 Features
- 272 Timer Controller Block Diagram
- 273 Register Map
- 274 Register Description
- 279 Watchdog Timer
- 281 Register Map
- 282 Register Description
- 284 UART Interface Controller
- 284 Overview
- 286 Features of UART controller
- 287 Block Diagram
- 289 IrDA Mode
- 291 LIN (Local Interconnection Network) mode
- 292 Register Map
- 293 Register Description
- 312 I2S Audio PCM Controller
- 312 Overview
- 312 Features
- 313 I2S Block Diagram
- 314 I2S Operation
- 315 FIFO operation
- 316 Register Map
- 317 Register Description
- 328 PDMA Controller
- 328 Overview
- 328 Features
- 328 Block Diagram
- 329 Function Description
- 330 Register Map
- 331 Register Description
- 350 Volume Control
- 350 Overview and feature
- 350 Volume Control Register Map
- 351 Volume Control register Description
- 354 FLASH MEMORY CONTROLLER (FMC)
- 354 Overview
- 354 Features
- 355 Flash Memory Controller Block Diagram
- 356 Flash Memory Organization
- 356 Boot Selection
- 357 Data Flash (DATAF)
- 358 User Configuration (CONFIG)
- 360 In-System Programming (ISP)
- 360 ISP Procedure
- 363 Register Map
- 364 Register Description
- 371 ANALOG SIGNAL PATH BLOCKS
- 371 Sigma- Delta Analog-to-Digital Converter (SDADC)
- 371 Functional Description
- 371 Features
- 371 Block Diagram
- 372 Operation
- 377 ADC Register Map
- 378 ADC Register Description
- 387 Audio Class D Speaker Driver (DPWM)
- 388 Functional Description
- 388 Features
- 388 Block Diagram
- 388 Operation
- 391 DPWM Register Map
- 392 DPWM Register Description
- 398 Analog Functional Blocks
- 398 Overview
- 398 Features
- 398 Register Map
- 399 VMID Reference Voltage Generation
- 400 LDO Power Domain Control
- 402 Microphone Bias
- 403 Oscillator Frequency Measurement and Control
- 409 Automatic Level Control (ALC)
- 409 Overview and Features
- 413 Register Map
- 414 Register Description
- 420 Capacitive Sensing Scan (CSCAN) and Operational Amplifiers
- 420 Overview and Features
- 420 Features
- 420 Operation
- 420 Operational Amplifier
- 423 Comparator
- 423 Register Map
- 424 Register Description
- 432 Biquad Filter (BIQ)
- 432 Overview and Features
- 433 Register Map
- 435 Register Description
- 440 Analog-to-Digital Convertor (SARADC)
- 440 Overview and Features
- 441 Block Diagram
- 441 Function description
- 447 Register Map
- 448 Register description
- 458 APPLICATION DIAGRAM
- 459 PACKAGE DIMENSIONS
- 459 64L LQFP (7x7x1.4mm footprint 2.0mm)
- 460 QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm
- 461 ORDERING INFORMATION
- 462 REVISION HISTORY