ST M8 SWIM communication protocol, M8 DM debug module User manual

Below you will find brief information for STM8 SWIM, STM8 DM. This manual describes the debug architecture of the STM8 core, which is made up of two modules: the Debug module and the Single Wire Interface Module. The STM8 Debug system provides non-intrusive read/write access to RAM and peripherals during program execution.

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UM0470
4.4
Debug module (DM)
Breakpoint decoding table
Table 4.
Decoding table for breakpoint interrupt generation
DM_CR1
DM_CSR1
BREAK CONDITIONS
BC2
BC1
BC0
BIR
BIW
BK1F
BK2F
BRW
0
0
0
0
0
0
0
x
0
0
0
0
1
Data Write on @=BK1 and Data=BK2L
1
0
0
0
0
0
1
0
Data Read on @=BK1 and Data=BK2L
1
0
1
0
0
0
0
0
1
1
1
Data R/W on @=BK1 and Data=BK2L
1
0
0/1
0
0
Instruction fetch BK1&lt;=@&lt;=BK2
1
0
x
0
0
1
0
1
Data Write on BK1&lt;=@&lt;=BK2
1
0
0
0
0
1
1
0
Data Read on BK1&lt;=@&lt;=BK2
1
0
1
0
0
1
1
1
Data R/W on BK1&lt;=@&lt;=BK2
1
0
0/1
0
1
0
0
0
Instruction fetch on @&lt;= BK1 or BK2&lt;=@
1
0
x
0
1
0
0
1
Data Write on @&lt;= BK1 or BK2&lt;=@
1
0
0
0
1
0
1
0
Data Read on @&lt;= BK1 or BK2&lt;=@
1
0
1
0
1
0
1
1
Data R/W on @&lt;= BK1 or BK2&lt;=@
0
1
1
X
X
1
0
0
0
0
Instruction fetch on @=BK1 then on @=BK2
1
0
0
0
1
Data Write on @=BK1 or @=BK2
1
0
0
1
0
Data Read on @=BK1 or @=BK2
10 or 01 or 11
1
1
0
0
1
1
Data R/W on @=BK1 or @=BK2
10 or 01 or 11
0/1
1
0
1
0
0
Instruction fetch on @=BK1 or @=BK2
10 or 01 or 11
x
1
0
1
0
1
Instruction fetch on @=BK1 / Data Write on @=BK2
10 or 01
x-0
1
0
1
1
0
Instruction fetch on @=BK1 / Data Read on @=BK2
10 or 01
x-1
1
0
1
1
1
Instruction fetch on @=BK1 / Data R/W on @=BK2
10 or 01
x-0/1
1
1
0
X
X
1
1
1
0
0
Data Write in Stack on @&lt;=BK1 / Instruction fetch on @=BK2
1
1
1
0
1
Data Write in Stack on @&lt;=BK1 / Data Write on @=BK2
10 or 01 or 11
0
1
1
1
1
0
Data Write in Stack on @&lt;=BK1 / Data Read on @=BK2
10 or 01
0-1
1
1
1
1
1
Data Write in Stack on @&lt;=BK1 / Data R/W on @=BK2
10 or 01 or 11
0-0/1
Disabled (RESET state)
Disabled
Disabled
Doc ID 14024 Rev 3
1
0
0/1
0
0
x
0
1
x
10 or 01 or 11
0
0
10 or 01
0
x
0-x
23/37
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Key features

Non-intrusive access
Read/write access to peripherals
Halt and step mode
Breakpoint capabilities
Watchdog control

Frequently asked questions

The STM8 Debug system is a single-wire interface based on asynchronous, high-sink open-drain, bidirectional communication that allows a debugging or programming tool to be connected to the MCU. It allows non-intrusive read/write access to RAM and peripherals during program execution.

The SWIM has three modes: OFF, I/O, and ACTIVE. The OFF mode is the default mode after power-on reset where the SWIM pin is not used as an I/O. The I/O mode is entered by setting the SWIM disable bit in the core configuration register, allowing the SWIM pin to be used as a standard I/O pin. The ACTIVE mode is entered by detecting a specific sequence on the SWIM pin while in OFF mode, enabling the SWIM pin to be used for communication with a debug tool.

The Debug Module (DM) allows the developer to perform certain debugging tasks without using an emulator. The DM can interrupt the MCU to break infinite loops or output the core context at a given point. It also supports two conditional breakpoints, software breakpoint control, step mode, external stall capability on WOTF command, watchdog and peripherals control, DM version identification capability, and interrupt vector table selection.