STMicroelectronics VNQ9080AJ Datasheet

VNQ9080AJ

Datasheet

Quad channel high-side driver with Current Sense analog feedback for automotive applications

PowerSSO-16

Product status link

VNQ9080AJ

Product summary

Order code VNQ9080AJTR

Package

Packing

PowerSSO-16

Tape and reel

Features

Description

Max transient supply voltage

Operating voltage range

Typ. on-state resistance (per Ch)

Current limitation (typ)

Standby current (max)

Parameter

V

CC

V

CC

R

ON

I

LIMH

I

STBY

Value

36 V

4 to 28 V

86 mΩ

13.6 A

0.5 µA

• AEC-Q100 qualified

• Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013)

• General

– Quad channel smart high-side driver with current sense analog feedback

– Very low standby current

– Compatible with 3 V and 5 V CMOS outputs

• CurrentSense diagnostic functions

– Multiplexed analog feedback of: load current with high precision proportional current mirror

– Overload and short to ground (power limitation) indication

– Thermal shutdown indication

– OFF-state open-load detection (with external pull-up)

– Output short to V

CC

detection

– Sense enable/disable

• Protections

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin

– Loss of ground and loss of V

CC

– Reverse battery with external components

– Electrostatic discharge protection

Applications

• Automotive resistive, inductive and capacitive loads

• Protected supply for ADAS systems: radars and sensors

• Automotive signal lamp: R10W and LEDs

DS12654 - Rev 5 - June 2022

For further information contact your local STMicroelectronics sales office.

www.st.com

VNQ9080AJ

Description

The device is a quad channel high-side driver manufactured using ST proprietary VIPower M0-9 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics.

The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off.

A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality.

A dedicated multifunction multiplexed analog output pin delivers diagnostic functions including high precision proportional load current sense, in addition to the detection of overload and short circuit to ground, short to V

CC and OFF-state open-load.

A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices.

DS12654 - Rev 5 page 2/44

1

VNQ9080AJ

Block diagram and pin description

Block diagram and pin description

Figure 1. Block diagram

VCC

IN0

IN1

IN2

IN3

SEn

SEL0

SEL1

FaultRST

V C C – G clamp

N D

Internal supply

Undervoltage shut- down

Channel 3

Channel 2

Channel 1

Channel 0 control & diagnostic

Gate driver

VCC– OUT

Clamp

Logic

Power limitation

Overtemperature

Open- Load in OFF

Current limitation

CH 0

CH 3

CH 2

CH 1

OUT3

OUT2

OUT1

CS

GND

Current

Sense

OUT0

Name

V

CC

OUTPUT

0,1,2,3

GND

INPUT

0,1,2,3

CS

SEn

SEL

0,1

FaultRST

Table 1. Pin functions

Function

Battery connection.

Power output

Ground connection; must be reverse battery protected by an external diode / resistor network.

Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs; controls output switch state.

analog current sense output pin; it delivers a current proportional to the selected load current.

Active high compatible with 3 V and 5 V CMOS outputs pin; enables the CS diagnostic pin.

Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer.

Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault - if kept low, sets the output to auto-restart mode.

DS12654 - Rev 5 page 3/44

VNQ9080AJ

Block diagram and pin description

Figure 2. Configuration diagram (top view)

OUTPUT0

SEn

INPUT0

GND

FaultRST

INPUT1

N.C.

OUTPUT1

1

2

3

4

5

6

7

8

PowerSSO-16

16

15

14

13

12

11

10

9

OUTPUT3

SEL1

INPUT3

CS

SEL0

INPUT2

N.C.

OUTPUT2

TAB = V

CC

GADG010318144RI

Connection/pin

Floating

To ground

1. X: do not care.

Table 2. Suggested connections for unused and not connected pins

CS

Not allowed

Through 1 kΩ resistor

NC Output

X

X (1)

X Not allowed

Input

X

Through 15 kΩ resistor

SEn, SELx, FaultRST

X

Through 15 kΩ resistor

DS12654 - Rev 5 page 4/44

2

Note:

2.1

VNQ9080AJ

Electrical specification

Electrical specification

Figure 3. Current and voltage conventions

V

FR

V

SEn

V

SEL

V

IN

I

IN

I

FR

I

SEn

I

SEL

I

S

FaultRST

SE n

SEL 0,1

V

CC

OUTPUT

0,1,2,3

CS

I

OUT

I

SENSE

V

Fn

V

SENSE

V

OUT

V

CC

INPUT

0,1,2,3

I

GND

GADG2802181245RI

V

Fn

= V

OUTn

- V

CC

during reverse battery condition.

Absolute maximum ratings

Stressing the device above the rating listed in Table 3. Absolute maximum ratings

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table below for extended periods may affect the device reliability.

Symbol

V

CC

-V

CC

V

CCJS

-I

GND

I

OUT

-I

OUT

I

IN

I

SEn

I

SEL0,1

I

FR

I

SENSE

E

MAX

V

ESD

Table 3. Absolute maximum ratings

Parameter

DC supply voltage

Reverse DC supply voltage

Maximum jump start voltage for single pulse short circuit protection

DC reverse ground pin current

OUTPUT

0,1,2,3

DC output current

Reverse DC output current

INPUT

0,1,2,3

DC input current

SEn DC input current

SEL

0,1

DC input current

FaultRST DC input current

CS pin DC output current (V

GND

= V

CC

and V

SENSE

< 0 V)

CS pin DC output current in reverse (V

CC

< 0 V)

Maximum switching energy (single pulse); T jstart

= 150 °C)

Electrostatic discharge (JEDEC 22A-114F)

INPUT

0,1,2,3

CS

SEn, SEL

0,1

, FaultRST

OUTPUT

0,1,2,3

V

CC

Value

36

0.3

28

200

Internally limited

2.2

-1 to 10

-1 to 3

-1 to 10

Unit mA

V

V mA

A

10

-20

4 mA mJ

2000

2000

2000

4000

4000

V

DS12654 - Rev 5 page 5/44

2.2

Symbol

V

ESD

T j

T stg

Parameter

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

Thermal data

Table 4. Thermal data

Symbol

R thj-board

R thj-amb

R thj-amb

Parameter

Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)

Thermal resistance junction-ambient (JEDEC JESD 51-5)

Thermal resistance junction-ambient (JEDEC JESD 51-7)

(1)(3)

(1)(2)

(1)(2)

1. One channel ON.

2. Device mounted on four-layer 2s2p PCB.

3. Device mounted on two-layer 2s0p PCB with 2 cm 2 heatsink copper trace.

VNQ9080AJ

Thermal data

Value

750

-40 to 150

-55 to 150

Unit

V

°C

Typ. value

9.5

54.5

22.5

Unit

°C/W

DS12654 - Rev 5 page 6/44

2.3

VNQ9080AJ

Main electrical characteristics

Main electrical characteristics

7 V < V

CC

< 28 V; -40 °C < T j

< 150 °C, unless otherwise specified.

All typical values refer to V

CC

= 13 V; T j

= 25 °C, unless otherwise specified.

Table 5. Power section

Symbol Parameter

V

CC

V

USD

Operating supply voltage

Undervoltage shutdown

V

USDReset

Undervoltage shutdown reset

V

USDhyst

Undervoltage shutdown hysteresis

Test conditions t

V

I

R

ON clamp

STBY

D_STBY

I

S(ON)

On-state resistance

Clamp voltage

Supply current in standby at

V

CC

= 13 V

(2)

(1)

Standby mode blanking time

Supply current

I

OUT

= 0.7 A; T j

= 25 °C

I

OUT

= 0.7 A; T j

= 150 °C

I

OUT

= 0.7 A; V

CC

= 4 V; T j

= 25 °C

I

OUT

= 0.07 A; V

CC

= 2.7 V; V

CC

decreasing

I

S

= 20 mA; 25 °C < T j

< 150 °C

I

S

= 20 mA; T j

= -40 °C

V

CC

= 13 V;

V

IN0,1,2,3

V

SEL0,1

= V

OUT0,1,2,3

= 0 V; T j

= V

= 25 °C

FR

= V

SEn

= 0 V;

V

CC

= 13 V;

V

IN0,1,2,3

= V

OUT0,1,2,3

= V

FR

= V

SEn

= 0 V;

V

SEL0,1

= 0; T j

= 85 °C (3)

V

CC

= 13 V;

V

IN0,1,2,3

= V

OUT0,1,2,3

= V

FR

= V

SEn

= 0 V;

V

SEL0,1

= 0 V; T j

= 125 °C

V

CC

= 13 V; V

IN

= V

OUT

= V

FR

= V

SEL0,1

= 0 V;

V

SEn

= 5 V to 0 V

V

CC

= 13 V; V

SEn

= V

FR

= V

SEL0,1

= 0 V;

V

IN0,1,2,3

= 5 V; I

OUT0,1,2,3

= 0 A

I

GND(ON)

Control stage current consumption in ON state. All channels active.

V

CC

V

= 13 V; V

SEn

IN0,1,2,3

= 5 V; I

= 5 V; V

FR

= V

SEL0,1

OUT0,1,2,3

= 0.7 A;

= 0 V;

I

L(off)

Off-state output current at

V

CC

= 13 V

(2)

V

IN0,1,2,3

= V

OUT0,1,2,3

= 0 V; V

CC

= 13 V;

T j

= 25 °C

V

IN0,1,2,3

= V

OUT0,1,2,3

= 0 V; V

CC

= 13 V;

T j

= 125 °C

V

F

Output - V

CC

diode voltage at

T j

= 150 °C

I

OUT

= -0.7 A; T j

= 150 °C

1. For each channel.

2. Power MOSFET leakage included.

3. Parameter specified by design; not subject to production test.

Min.

Typ.

Max.

Unit

4 13 28 V

2.1

2.7

4.5

V

V

V 0.15

86

36

36

38

190

149

516

45 mΩ

V

V

0.5

0.5

µA

3

60 260 550 µs

5.5

7.5

mA

9 mA

0 0.01

0.5

0 3

0.7

µA

V

DS12654 - Rev 5 page 7/44

VNQ9080AJ

Main electrical characteristics

Table 6. Switching

Symbol t t t d(on)

(1)

d(off)

(1)

(dV

OUT

/dt) on

(1)

(dV

OUT

/dt) off

(1)

W

ON

W

OFF

SKEW

V

CC

= 13 V; -40 °C < T j

< 150 °C, unless otherwise specified

Parameter Test conditions Min.

Typ.

Turn-on delay time at T j

= 25 °C

Turn-off delay time at T j

= 25 °C

Turn-on voltage slope at T j

= 25 °C

Turn-off voltage slope at T j

= 25 °C

Switching energy losses at turn-on (t won

)

Switching energy losses at turn-off (t woff

)

Differential pulse skew (t

PHL

- t

PLH

)

R

L

= 18.6 Ω

1. See

Figure 4. Switching time and pulse skew .

2. Specified by design and evaluated by characterization, not tested in production.

10

10

0.2

0.2

-45

26

30

0.42

0.45

0.06

0.06

5

Max.

120

100

0.7

0.7

0.095

(2)

0.095

(2)

55

Unit

µs

V/µs mJ mJ

µs

DS12654 - Rev 5 page 8/44

DS12654 - Rev 5

VNQ9080AJ

Main electrical characteristics

Symbol

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

V

ICL

V

SELL

I

SELL

V

SELH

I

SELH

V

SEL(hyst)

V

SELCL

V

SEnL

I

SEnL

V

SEnH

I

SEnH

V

SEn(hyst)

V

SEnCL

V

FRL

I

FRL

V

FRH

I

FRH

V

FR(hyst)

V

FRCL

Parameter

Table 7. Logic inputs

7 V < V

CC

< 28 V; -40 °C < T j

< 150 °C

Test conditions

INPUT

0,1,2,3

characteristics

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

V

IN

IN

= 0.9 V

= 2.1 V

Input clamp voltage

Input clamp voltage

I

IN

= 1 mA

I

IN

= -1 mA

FaultRST characteristics

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

V

IN

IN

= 0.9 V

= 2.1 V

Input clamp voltage

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

I

IN

= 1 mA

I

IN

= -1 mA

SEL

0,1

characteristics (7 V < V

CC

< 18 V)

V

V

IN

IN

= 0.9 V

= 2.1 V

Input clamp voltage

I

IN

= 1 mA

I

IN

= -1 mA

SEn characteristics (7 V < V

CC

< 18 V)

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

V

IN

IN

= 0.9 V

= 2.1 V

I

SEN

= 1 mA

I

SEN

= -1 mA

Min.

Typ.

Max.

Unit

1

2.1

0.2

6

0.9

10

8.5

-0.7

1

2.1

0.2

6

-0.7

0.9

10

8.5

V

µA

V

µA

V

V

V

µA

V

µA

V

V

1

2.1

0.2

6

-0.7

0.9

10

8.5

V

µA

V

µA

V

V

1

2.1

0.2

9

-0.7

0.9

10

12

V

µA

V

µA

V

V page 9/44

DS12654 - Rev 5

VNQ9080AJ

Main electrical characteristics

Table 8. Protections

Symbol Parameter

7 V < V

CC

< 18 V; -40 °C < T j

< 150 °C

Test conditions

I

I

LIMH

LIMH2

(1)

(2)

DC short- circuit current

V

CC

= 16 V; T j

= -40 °C

V

CC

= 16 V; T j

= 150 °C

V

CC

= 19 V; T j

= -40 °C

V

CC

= 19 V; T j

= 150 °C

V

CC

= 22 V; T j

= 25 °C I

LIMH at 22 V

T

TSD

Shutdown temperature

T

T

RS

HYST

Thermal reset of fault diagnostic indication

Thermal hysteresis

(T

TSD

- T

RS

) (3)

V

FR

= 0 V; V

SEn

= 5 V t

ΔT

J_SD

LATCH_RST

Dynamic temperature

Fault reset time for output

unlatch (3)

V

CC

= 19 V

V

CC

= 16 V

V

FR

= 5 V to 0 V; V

SEn

= 5 V;

For example Ch

0

:

V

IN0

= 5 V; V

SEL0,1

= 0 V t

D_Restart

Latch-OFF delay time before automatic restart

T j

> 125 °C

V

DEMAG

Turn-off output voltage clamp

I

OUT

= 0.7 A; L = 6 mH; T j

= -40 °C

I

T

OUT

= 0.7 A; L = 6 mH; j

= 25 °C to 150 °C

1. I

LIMH

guaranteed between 7 V and 16 V, -40 °C < T j

< 150 °C.

2. I

LIMH2

guaranteed between 16 V and 19 V, -40 °C < T j

< 150 °C.

3. Specified by design and evaluated by characterization, not tested in production.

Min.

-15%

-15%

-15%

-15%

150

135

3

7

55

80

Typ.

14

10

11.2

8.9

4.2

175

10

Max.

15%

15%

15%

15%

Unit

A

210

20

°C

K

µs

50 75

V

CC

- 36

V

CC

- 36 V

CC

- 38 V

CC

- 45 V ms

V page 10/44

DS12654 - Rev 5

VNQ9080AJ

Main electrical characteristics

Table 9. Current Sense

I

V

Symbol

SENSE_CL dK

OL

V

K

/K

OL

OL

(1)(2)

K

0 dK

0

/K

0

(1) (2)

K

1 dK

1

/K

1

(1)(2)

K

2 dK

2

/K

2

(1)(2)

K

850 dK

850

/K

850

(1)(2)

K

3 dK

3

/K

3

(1) (2)

V

I

SENSE0

OUT_MSD

SENSE_SAT

SENSE_SAT

(1)

(1)

Parameter

7 V < V

CC

< 18 V; -40 °C < T j

< 150 °C

Test conditions

CurrentSense clamp voltage

V

SEn

= 0 V; I

SENSE

= 1 mA

V

SEn

= 0 V; I

SENSE

= -1 mA

CurrentSense characteristics

I

OUT

/I

SENSE

Current sense ratio drift at calibration point

I

OUT

/I

SENSE

I

OUT

= 0.01 A; V

SENSE

= 0.5 V; V

SEn

= 5 V

I

OUT

= 0.025 A; V

SENSE

= 0.5 V; V

SEn

= 5 V

CurrentSense ratio drift

I

OUT

/I

SENSE

CurrentSense ratio drift

I

OUT

/I

SENSE

CurrentSense ratio drift

I

I

OUT

OUT

= 0.15 A; V

SENSE

= 0.7 A; V

SENSE

= 0.5 V; V

SEn

= 3.5 V; V

SEn

= 5 V

= 5 V

I

OUT

/I

SENSE

CurrentSense ratio drift

I

OUT

/I

SENSE

CurrentSense ratio drift

I

I

OUT

OUT

= 0.85 A; V

SENSE

= 2.1 A; V

SENSE

= 3.5 V; V

SEn

= 3.5 V; V

SEn

= 5 V

= 5 V

CS disabled: V

SEn

= 0 V

CurrentSense leakage current

CS disabled: -1 V < V

SENSE

< 5 V (1)

CS enabled: V

SEn

= 5 V; all channel ON;

I

OUTX

= 0 A; Ch

X

diagnostic selected;

For example Ch

0

:

V

IN0

= 5 V; V

IN1,2,3

= 5 V;

V

SEL0,1

= 0 V; I

OUT0

= 0 A;

I

OUT1,2,3

= 0.7 A

Output voltage for

CurrentSense shutdown

CurrentSense saturation voltage

CS saturation current

CS enabled: V

SEn

= 5 V; Ch

X

OFF;

I

OUTX

= 0 A; Ch

X

diagnostic selected;

For example Ch

0

:

V

IN0

= 0 V; V

IN1,2,3

= 5 V;

V

SEL0,1

= 0 V; I

OUT0

= 0 A; I

OUT1,2,3

= 0.7 A

V

SEn

= 5 V; R

SENSE

= 2.7 kΩ;

For example Ch

0

:

V

IN0

= 5 V; V

SEL0,1

= 0 V; I

OUT0

= 0.7 A

V

CC

= 7 V; R

SENSE

= 10 kΩ;

V

SEn

= 5 V; V

IN0

= 5 V;

V

SEL0,1

= 0 V; I

OUT0

= 6 A; T j

= -40 °C

V

CC

= 7 V; V

SENSE

= 3.5 V;

V

IN0

= 5 V; V

SEn

= 5 V;

V

SEL0,1

= 0 V; T j

= 150 °C

Min.

Typ.

Max.

Unit

-9 -8

7

-7

V

810

-25 25 %

-35% 1500 +35%

-25 25

-15% 1500 15%

-15 15

-7% 1500 7%

-7 7

-7% 1500 7%

-7 7

-5% 1500 5%

-5 5

0

-0.5

0.5

0.5

%

%

%

%

%

0

0

4.8

2

5

10

1

µA

V

V mA page 11/44

DS12654 - Rev 5

VNQ9080AJ

Main electrical characteristics

Symbol

I

OUT_SAT

(1)

t

V

I t t

I

V

OL

L(off2)

DSTKON

D_OL_V

D_VOL

SENSEH

SENSEH

Parameter

7 V < V

CC

< 18 V; -40 °C < T j

< 150 °C

Test conditions

Output saturation current

V

CC

= 7 V; V

SENSE

= 3.5 V;

V

IN0

= 5 V; V

SEn

= 5 V;

V

SEL0,1

= 0 V; T j

= 150 °C

OFF-state diagnostic

OFF-state open-load voltage detection threshold

V

SEn

= 5 V; C hX

OFF;

Ch

X

diagnostic selected;

For example Ch

0

:

V

IN0

= 0 V; V

SEL0,1

= 0 V;

OFF-state output sink current V

IN

= 0 V; V

OUT

= V

OL

; T j

= -40 °C to 125 °C

OFF-state diagnostic delay time from falling edge of

INPUT

(see

Figure 6. t

DSTKON

)

V

SEn

= 5 V; Ch

X

ON to OFF transition;

Ch

X

diagnostic selected;

For example Ch

0

:

V

IN0

= 5 V to 0 V; V

SEL0,1

= 0 V;

I

OUT0

= 0 A; V

OUT

= 4 V

Settling time for valid OFFstate open load diagnostic indication from rising edge of

SEn

V

V

IN0,1,2,3

SEn

= 0 V; V

= 0 V to 5 V

FR

= 0 V; V

OUT0

= 4 V;

OFF-state diagnostic delay time from rising edge of V

OUT

V

SEn

= 5 V; Ch

X

OFF;

Ch

X

diagnostic selected;

For example Ch

0

:

V

IN0

= 0 V; V

SEL0,1

= 0 V;

V

OUT0

= 0 V to 4 V

CurrentSense output voltage in fault condition

Fault diagnostic feedback (see

Table 10. Truth table )

•

13 V < V

CC

< 18 V;

For example:

Ch

0

in open load; R

SENSE

= 0.7 kΩ;

V

IN0

= 0 V;

V

SEn

= 5 V; V

SEL0,1

= 0 V;

I

OUT0

= 0 A; V

OUT0

= 4 V

•

V

CC

= 7 V;

For example:

Ch

0

in open load; R

SENSE

= 0.7 kΩ;

V

IN0

= 0 V;

V

SEn

= 5 V; V

SEL0,1

= 0 V;

I

OUT0

= 0 A; V

OUT0

= 4 V

CurrentSense output current in fault condition

•

13 V < V

CC

< 18 V; V

SENSE

= 5 V

For example:

Ch

0

in open load; V

IN0

= 0 V;

V

SEn

= 5 V; V

SEL0,1

= 0 V;

I

OUT0

= 0 A; V

OUT0

= 4 V

Min.

Typ.

Max.

Unit

4

2

100

5

4.3

7

3

-150 -40

170

5

8.6

4

-5

250

60

30

7.5

12

A

V

µA

µs

µs

µs

V mA page 12/44

DS12654 - Rev 5

VNQ9080AJ

Main electrical characteristics t t t

Symbol

DSENSE1H

DSENSE1L

Parameter

7 V < V

CC

< 18 V; -40 °C < T j

< 150 °C

Test conditions

V

R

IN

L

= 5 V; V

= 18.6 Ω

SEn

= 0 V to 5 V; R

SENSE

= 1 kΩ;

Min.

Typ.

Max.

Unit

I

SENSEH

CurrentSense output current in fault condition

•

V

CC

= 7 V; V

SENSE

= 5 V;

For example:

Ch

0

in open load; V

IN0

= 0 V;

V

SEn

= 5 V; V

SEL0,1

= 0 V;

I

OUT0

= 0 A; V

OUT0

= 4 V

4.4

CurrentSense timings (current sense mode - see

Figure 5. Current Sense timings (current sense mode)

) (3)

Current sense settling time from rising edge of SEn

Current sense disable delay time from falling edge of SEn

5

60

20 mA

µs

µs

DSENSE2H

Current sense settling time from rising edge of INPUT

V

IN

= 0 V to 5 V; V

SEn

= 5 V; R

SENSE

= 1 kΩ;

R

L

= 18.6 Ω

100 200 µs

Δt t t

DSENSE2H

DSENSE2L

DSENSE3H

Current sense settling time from rising edge of I

OUT

(dynamic response to a step change of I

OUT

)

Current sense turn-off delay time from falling edge of

INPUT

Current sense latch-OFF filtering time

V

IN

= 90 % of I

SENSEMAX

; R

L

V

R

IN

L

= 5 V; V

SEn

= 5 V; R

= 5 V to 0 V; V

= 18.6 Ω

SEn

SENSE

= 18.6 Ω

= 5 V; R

= 1 kΩ; I

SENSE

SENSE

= 1 kΩ;

1.4

70

2

100

250

2.6

µs

µs ms t t

D_XtoY

D_CStoVSENSEH

CurrentSense transition delay from Ch

X

to Ch

Y

CurrentSense transition delay from stable current sense on

Ch

X

to V

SENSEH on Ch

Y

CurrentSense timings (Multiplexer transition times) (3)

V

IN0

= 5 V; V

IN1

= 5 V; V

SEn

V to 5 V;

= 5 V; V

SEL0

= 0

I

OUT0

= 0 A; I

OUT1

= 0.7 A;

R

SENSE

= 1 kΩ

V

IN0

= 5 V; V

IN1

= 0 V; V

SEn

= 5 V; V

SEL0

= 0

V to 5 V;

I

OUT0

= 0.7 A; V

OUT1

= 4 V;

R

SENSE

= 1 kΩ

1. Parameter specified by design; not subject to production test.

2. All values refer to V

CC

= 13 V; T j

= 25 °C, unless otherwise specified.

3. Transition delay is measured up to ±10% of final conditions.

30

20

µs page 13/44

DS12654 - Rev 5

VNQ9080AJ

Main electrical characteristics

VOUT

Vcc

Figure 4. Switching time and pulse skew twon twoff dV

OUT

/dt

ON

80% Vcc

OFF dV

OUT

/dt

20% Vcc t

INPUT td(on) tpLH td(off) tpHL t

IN

SEn

High

Low

I

OUT

CURRENT SENSE

Figure 5. Current Sense timings (current sense mode) t

DSENSE2H t

DSENSE1L t

DSENSE1H t

DSENSE2L

GAPG1003141014CFT page 14/44

DS12654 - Rev 5

Figure 6. t

DSTKON

V

OUT

> V

OL

VNQ9080AJ

Main electrical characteristics

V

INPUT

V

OUT

MultiSense t

DSTKON

GAPG2609141140CFT

Table 10. Truth table

Mode

Standby

Normal

Overload

Undervoltage

All logic inputs low

Nominal load connected;

T j

Overload or short to GND causing:

T j

> T

TSD

or ΔT j

V

< 150 °C

CC

< V

USD

Conditions

> ΔT j _SD

(falling)

IN

X

L

FR SEn SEL

L L L

X

OUT

L

X

CS

Hi-Z

Comments

Low quiescent current consumption

L X L

H

H

L

H

See (1)

H

H

See (1)

Outputs configured for auto-restart

Outputs configured for

Latch-off

L X L

H

H

X

L

H

X X

See

(1)

X

H

L

L

L

See (1)

Output cycles with temperature hysteresis

Hi-Z

Hi-Z

Output latches-off

Re-start when

V

CC

> V

USD

+

V

USDhyst

(rising)

OFF-state diagnostics

Short to V

CC

Open-load

L X

L X

Negative output voltage

Inductive loads turn-off

1. Refer to Table 11. Current sense multiplexer addressing

.

L X

See

See

(1)

(1)

H

H

See

< 0 V See

(1)

(1)

External pull-up page 15/44

VNQ9080AJ

Main electrical characteristics

L X X

Table 11. Current sense multiplexer addressing

SEn SEL

1

SEL

0

MUX channel

Normal mode

CS output

Overload OFF-state diag.

Hi-Z

H

H

H

H

L

L

H

H

L

H

L

H

Channel 0 diagnostic

Channel 1 diagnostic

Channel 2 diagnostic

Channel 3 diagnostic

I

SENSE

= 1/K * I

OUT0

I

SENSE

= 1/K * I

OUT1

I

SENSE

= 1/K * I

OUT2

I

SENSE

= 1/K * I

OUT3

V

SENSE

= V

SENSEH

V

SENSE

= V

SENSEH

Negative output

Hi-Z

DS12654 - Rev 5 page 16/44

2.4

Waveforms

Figure 7. Latch-off mode - Intermittent short circuit

Normal condition

INPUT

Short circuit condition

Unlatch command is stored, but no restart until t

D_Restart is elapsed.

FaultRST

I

LIMH

I

OUT

I

NOM

CS

OTDIFF

(Internal signal)

OT

(Internal signal)

OT_Fault

(Internal signal)

OT_Fault_Diag

(Internal signal)

(*) Not in scale t

D_Restart t > t

DSENSE3H

I

OUT

CS

OTDIFF

(Internal signal)

OT

(Internal signal)

OT_Fault

(Internal signal)

OT_Fault_Diag

(Internal signal)

(*) Not in scale

Figure 8. Auto-restart mode - Intermittent short circuit

Short circuit condition Normal condition

INPUT

FaultRST

I

LIMH

Power Limitation

I

NOM t

D_Restart t > t

DSENSE3H

VNQ9080AJ

Waveforms

DS12654 - Rev 5 page 17/44

Figure 9. Auto-restart mode - Permanent short circuit

INPUT

FaultRST

I

OUT

CS

OTDIFF

(Internal signal)

OT

(Internal signal)

OT_Fault

(Internal signal)

OT_Fault_Diag

(Internal signal)

(*) Not in scale

I

LIMH

Power Limitation t

D_Restart

I

LIMH

Power Limitation t < t

DSENSE3H

Figure 10. Standby mode activation

VNQ9080AJ

Waveforms

DS12654 - Rev 5

Figure 11. Standby state diagram

Normal Operation t > t

D_STBY

INx = Low

AND

FaultRST = Low

AND

SEn = Low

AND

SELx = Low

Stand-by Mode

INx = High

OR

FaultRST = High

OR

SEn = High

OR

SELx = High

GADG2702181047RI page 18/44

VNQ9080AJ

Electrical characteristics (curves)

2.5

Electrical characteristics (curves)

I

Loff

(nA)

Figure 12. OFF-state output current

GADG300520221511OFFSI

120

Off state

V

CC

= 13 V

V

IN

= V

OUT

= 0 V

80

40

0

-50 0 50 100 150 T (°C)

I

GND(ON)

(mA)

6.5

Figure 14. I

GND(ON)

vs I out

GADG300520221516GNDon

V

CC

= 13 V

I

OUT

= 0.7 A

6.0

5.5

5.0

-50 0 50 100 150 T (°C)

Figure 16. Logic input low level voltage

V

IL

, V

(V)

FRL

, V

SELL

, V

SEnL GADG300520221521VIL

1.35

1.30

1.25

1.20

-50 0 50 100 150 T (°C)

I

STBY

(µA)

Figure 13. Standby current

GADG300520221512ISTBY

3

V

CC

= 13 V

2

1

0

-50 0 50 100 150 T (°C)

Figure 15. Logic input high level voltage

V

IH

, V

FRH

, V

SELH

, V

SEnH

(V)

GADG300520221518VIH

1.68

1.66

1.64

1.62

1.60

-50 0 50 100 150 T (°C)

Figure 17. High level logic input current

I

IH

, I

FRH

, I

SELH

, I

(µA)

SEnH GADG300520221522IIH

3.75

3.50

3.25

3.00

-50 0 50 100 150 T (°C)

DS12654 - Rev 5 page 19/44

Figure 18. Low level logic input current

I

IL

, I

FRL

, I

SELL

, I

SEnL

(µA)

GADG300520221523IIL

2.75

2.50

2.25

2.00

-50 0 50 100 150 T (°C)

Figure 20. FaultRST input clamp voltage

V

FRCL

(V)

GADG300520221526VFRCL

I

IN

= 1 mA

6

4

2

0

-2

-50 0

I

IN

= -1 mA

50 100 150 T (°C)

R

ON

(mΩ)

Figure 22. On-state resistance vs T

C

GADG300520221530RonT

140

V

CC

= 4 V

I

OUT

= 0.7 A

110

80

50

-50 0 50 100 150 T (°C)

VNQ9080AJ

Electrical characteristics (curves)

Figure 19. Logic input hysteresis voltage

V i(hyst)

, V

FR(hyst)

(V)

, V

SEL(hyst)

, V

SEn(hyst)

GADG300520221525VI

0.35

0.30

0.25

0.20

-50 0 50 100 150 T (°C)

V

USD

(V)

Figure 21. Undervoltage shutdown

GADG300520221527USD

2.5

110

80

50

0

2.0

1.5

1.0

-50 0 50 100 150 T (°C)

R

ON

(mΩ)

Figure 23. On-state resistance vs V

CC

GADG300520221531RonVcc

T = 150 °C

T = 125 °C

140

10

T = 25 °C

T = -40 °C

20 30 T (°C)

DS12654 - Rev 5 page 20/44

Figure 24. Turn-on voltage slope

(dVout/dt)

(V/µs)

On GADG300520221534dVdton

0.475

0.450

V

CC

= 13 V

R

L

= 18.6 Ω

0.425

0.400

-50 0 50 100 150 T (°C)

Figure 26. W

ON

vs T

C

GADG300520221537Won W

ON

(μJ)

0.6

0.4

0.2

0.0

-50 0 50 100 150 T (°C)

I

LIMH

(A)

14

13

12

11

10

-50

Figure 28. I

LIMH

vs T

C

GADG300520221541IlimH

0

V

CC

= 16 V

50 100 150 T (°C)

VNQ9080AJ

Electrical characteristics (curves)

Figure 25. Turn-off voltage slope

(dVout/dt)

Off

(V/µs)

GADG300520221535dVdtoff

0.45

V

CC

= 13 V

R

L

= 18.6 Ω

0.40

0.35

0.30

-50 0 50 100 150 T (°C)

Figure 27. W

OFF

vs T

C

GADG300520221539Woff W

OFF

(µJ)

0.6

0.4

0.2

0.0

-50 0 50 100 150 T (°C)

Figure 29. OFF-state open-load voltage detection threshold

V

OL

(V)

GADG300520221544VOL

2.75

2.50

2.25

2.00

-50 0 50 100 150 T (°C)

DS12654 - Rev 5 page 21/44

V

SENSE_CL

(V)

Figure 30. V

SENSE

clamp vs T

C

GADG300520221546SenCL

I

IN

= 1 mA

6

4

2

0

-2

-50 0

I

IN

= -1 mA

50 100 150 T (°C)

VNQ9080AJ

Electrical characteristics (curves)

V

SENSEH

(V)

5.75

Figure 31. V

SENSEH

vs T

C

GADG300520221548SenH

5.50

5.25

5.00

-50 0 50 100 150 T (°C)

DS12654 - Rev 5 page 22/44

3

3.1

3.2

3.3

3.4

VNQ9080AJ

Protections

Protections

Power limitation

The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔT

J

through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔT

J

exceeds the safety level of ΔT

J_SD

. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off

(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue.

Thermal shutdown

In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the

FaultRST pin, the device switches on again as soon as its junction temperature drops to T

R

(FaultRST = Low) or remains off (FaultRST = High).

Current limitation

The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, I

LIMH

, by operating the output power MOSFET in the active region.

Negative voltage clamp

In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, V

DEMAG

, allowing the inductor energy to be dissipated without damaging the device.

DS12654 - Rev 5 page 23/44

4

4.1

VNQ9080AJ

Application information

Application information

Figure 32. Application diagram

+5V

V

DD

OUT

OUT

OUT

OUT

ADC in

OUT

Rprot_SEn

SEn

INPUT

Rprot

Rprot

Rprot

FaultRST

SEL

Rprot

CS

Cext

Rsense

GND GND

Current mirror

Logic

R

GND

GND

GND

GND

GND protection network against reverse battery

Figure 33. Simplified internal structure

5V

Vcc

Rprot

INPUT

V

CC

D

GND

OUTPUT

GND GND

Dld

MCU

Rprot_SEn

SEn

Rprot

Rprot

FaultRST

CS

OUTPUT

Dld

Rsense

R

GND

GND

D

GND

GND

GAPGCFT00830

DS12654 - Rev 5 page 24/44

4.1.1

4.2

VNQ9080AJ

Immunity against transient electrical disturbances

Diode (DGND) in the ground line

A resistor (typ. R

GND

= 4.7 kΩ) should be inserted in parallel to D

GND

if the device drives an inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.

Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the V

CC

pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.

The related function performance status classification is shown in

Table 12. ISO 7637-2 - electrical transient conduction along supply line

.

Test pulses are applied directly to DUT (device under test) both in ON and OFF-state and in accordance to ISO

7637-2:2011(E), chapter 4.

The DUT is intended as the current device only, with external components as shown in

Figure 34. M0-9 application schematic .

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”.

Table 12. ISO 7637-2 - electrical transient conduction along supply line

Test Pulse

2011(E)

Test pulse severity level with Status II functional performance status

1

2a

3a

3b

4 (2)

Level

III

III

IV

IV

IV

U

S

(1)

-112 V

+55 V

-220 V

+150 V

-7 V

Load dump according to ISO 16750-2:2010

Test B

(3)

35 V

Minimum number of pulses or test time

500 pulses

500 pulses

1h

1h

1 pulse

5 pulse

Burst cycle / pulse repetition time min

0.5 s

0.2 s

90 ms

90 ms

1 min max

5 s

100 ms

100 ms

1. U

S

is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

2. Test pulse from ISO 7637-2:2004(E).

3. With 35 V external suppressor referred to ground (-40°C < T j

< 150 °C).

Pulse duration and pulse generator internal impedance

2 ms, 10 Ω

50 µs, 2 Ω

0.1 µs, 50 Ω

0.1 µs, 50 Ω

100 ms, 0.01 Ω

400 ms, 2 Ω

DS12654 - Rev 5 page 25/44

Note:

VNQ9080AJ

Immunity against transient electrical disturbances

Figure 34. M0-9 application schematic

+5V

V

DD

OUT

V

CC

OUT

OUT

OUT

ADC in

OUT

Rprot_SEn

SEn

INPUT

Rprot

Rprot

Rprot

FaultRST

SEL

Rprot

CS

Cext

Rsense

GND GND

Current mirror

Logic

OUTPUT

R

GND

GND

D

GND

Rload_nom

GND GND

GND

GND

In case of multiple channels, each OUTPUT must be connected to the resistive nominal load.

1μF

DS12654 - Rev 5 page 26/44

4.3

4.4

VNQ9080AJ

MCU I/Os protection

MCU I/Os protection

If a ground protection network is used and negative transients are present on the V

CC be pulled negative. ST suggests to insert a resistor (R prot

line, the control pins will

) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.

Equation

V

CCpeak

/I latchup

≤ R prot

≤ (V

OHµC

- V

IH

- V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= -150 V; I latchup

≥ 20 mA; V

OHµC

≥ 4.5 V

7.5 kΩ ≤ R prot

≤ 140 kΩ.

Recommended values: R prot

= 15 kΩ

A different value of the resistor has to be used for SEn pin, Rprot_SEn, as reported in

Figure 32. Application diagram .

CS - analog current sense

Diagnostic information on device and load status is provided by an analog output pin (CS) delivering the following signal:

• Current monitor: current mirror of channel output current

This signal is routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in

Table 11. Current sense multiplexer addressing

.

Figure 35. Current Sense and diagnostic – block diagram

VCC

VCC – GND

Clamp

Internal Supply

Undervoltage shut-down

FaultRST

R

PROT

To µC ADC

INPUT

SEL

1

SEL

0

SE n

I

SENSE

CS

R

SENSE

GND

MUX

Fault

Diagnostic

CURRENT

MONITOR

Fault

V

SENSEH

Control & Diagnostic

Gate Driver

VCC – OUT

Clamp

Current

Limitation

Power Limitation

Overtemperature

Short to VCC

Open-Load in OFF K factor

Current

Sense

T

I

OUT

OUT

DS12654 - Rev 5 page 27/44

VNQ9080AJ

CS - analog current sense

4.4.1

Principle of Current Sense signal generation

Figure 36. Current Sense block diagram

Vcc

Sense MOS

INPUT

Main MOS

OUT

Current sense

Current sense Switch Block

Fault

To uC ADC

CS

R

PROT

R

SENSE

GAPG2307131200CFT

Current sense

The output is capable of providing:

• Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to a known ratio named K

• Diagnostics flag in fault conditions delivering fixed voltage V

SENSEH

The current delivered by the current sense circuit, I

SENSE

, can be easily converted into a voltage V

SENSE

by using an external sense resistor, R

SENSE

, allowing continuous load monitoring and abnormal condition detection.

Normal operation (channel ON, no fault, SEn active)

While the device is operating in normal conditions (no fault intervention), V

SENSE

calculation can be done using simple equations

Current provided by CS output: I

SENSE

= I

OUT

/K

Voltage on R

SENSE

: V

SENSE

= R

SENSE

· I

SENSE

= R

SENSE

· I

OUT

/K

Where:

•

•

•

•

V

SENSE

is the voltage measurable on R

SENSE

resistor

I

SENSE

is the current provided from CS pin in current output mode

I

OUT

is the current flowing through output

K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of the overall circuitry, specifying the ratio between I

OUT

and I

SENSE

.

Failure flag indication

In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a “current limited” voltage source, V

SENSEH

.

In any case, the current sourced by the CS in this condition is limited to I

SENSEH

.

DS12654 - Rev 5 page 28/44

VNQ9080AJ

CS - analog current sense

+5V

Microcontroller V

DD

GND

100nF

OUT

GND

GND

2.2 k

OUT

15k

OUT

15k

OUT

15k

ADC in

15k

OUT

GND

15k

CEXT

Figure 37. Analog HSD – open-load detection in off-state

Vbat

100nF/50V

GND

V

CC

SEn

INPUT

FaultRST

SEL

CS

GND

Rsense

Cu rrent mirror

Logic

R

GND

4.7k

GND

D

GND

GND

OUTPUT

Vbat

Rpull-up

External

Pull -Up switch

OUTPUT

10nF /100V

GND

GAPG1201151432CFT

Figure 38. Open-load / short to V

CC

condition

V

IN

V

SENSE

Open-load

V

SENSE

Short to V

CC t

DSTKON

V

SENSEH

V

SENSE

= 0

Pull-up connected

Pull-up disconnected

V

SENSEH

DS12654 - Rev 5 page 29/44

4.4.2

VNQ9080AJ

CS - analog current sense

Open-load

Short to V

CC

Nominal

Condition

Table 13. Current Sense pin levels in off-state

Output

V

OUT

> V

OL

V

OUT

< V

OL

V

OUT

> V

OL

V

OUT

< V

OL

Hi-Z

V

SENSEH

Hi-Z

0

Hi-Z

V

SENSEH

Hi-Z

0

CS

L

H

L

L

H

H

L

H

SEn

Short to V

CC

and OFF-state open-load detection

Short to V

CC

A short circuit between V

CC and output is indicated by the relevant current sense pin set to V

SENSEH

during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short-circuit.

OFF-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor R

PU

connecting the output to a positive supply voltage V

PU

.

It is preferable that V

PU

is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, that is when load is connected.

R

PU must be selected in order to ensure V

OUT

> V

OLmax in accordance with the following equation:

R

PU

<

V

PU

- 4

I

L(off2)min @ 4V

DS12654 - Rev 5 page 30/44

5

VNQ9080AJ

Maximum demagnetization energy (Vcc = 16 V)

Maximum demagnetization energy (Vcc = 16 V)

Figure 39. Maximum turn off current versus inductance

10.00

VNQ9080AJ - Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

1.00

0.10

0.1

L (mH) 1 10 100

Figure 40. Maximum turn off energy versus inductance

100.00

VNQ9080AJ - Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

10.00

1000

Note:

1.00

0.1

L (mH)

1 10 100 1000

Values are generated with R

L

= 0 Ω.

In case of repetitive pulses, T jstart

(at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

DS12654 - Rev 5 page 31/44

6

6.1

VNQ9080AJ

Package and PCB thermal data

Package and PCB thermal data

PowerSSO-16 thermal data

Figure 41. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5)

Figure 42. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7)

DS12654 - Rev 5

Dimension

Board finish thickness

Board dimension

Board Material

Copper thickness (top and bottom layers)

Copper thickness (inner layers)

Thermal vias separation

Thermal via diameter

Copper thickness on vias

Footprint dimension (top layer)

Heatsink copper area dimension (bottom layer)

Table 14. PCB properties

Value

1.6 mm ±10%

77 mm x 86 mm

FR4

0.070 mm

0.035 mm

1.2 mm

0.3 mm ±0.08 mm

0.025 mm

2.2 mm x 3.9 mm

Footprint, 2 cm 2 or 8 cm 2 page 32/44

DS12654 - Rev 5

VNQ9080AJ

PowerSSO-16 thermal data

70

60

50

Figure 43. R thj-amb

vs PCB copper area in open box free air condition (one channel on)

R thj-amb

90

R thj-amb

80

R

TH_J PCB

= 9.5° C/W

40

30

0 2 4 6

PCB Cu heatsink area (cm2 )

8 10

Figure 44. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)

100

Z

TH_JA

(°C/W)

10

1

0.0001

0.001

0.01

0.1

Time (s)

1

Equation: pulse calculation formula

Z

THδ

= R

TH

· δ + Z

THtp

(1 - δ) where δ = t

P

/T

10

Cu=foot print

Cu=2 cm2

Cu=8 cm2

4 Layer

100 1000 page 33/44

VNQ9080AJ

PowerSSO-16 thermal data

Figure 45. Thermal fitting model of a double-channel HSD in PowerSSO-16

Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections

(power limitation or thermal cycling during thermal shutdown) are not triggered.

Table 15. Thermal parameters

Area/island (cm 2 )

R1 = R7 = R9 = R11 (°C/W)

R2 = R8 = R10 = R12 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 = C7 = C9 = C11 (W·s/°C)

C2 = C8 = C10 =C12 (W·s/°C)

C3 (W·s/°C)

C4 (W·s/°C)

C5 (W·s/°C)

C6 (W·s/°C)

FP

2

2.5

6

8.5

33

29

0.00008

0.0008

0.08

0.004

0.4

3

2

19

18

-

-

-

-

-

5.5

7.5

0.004

0.5

5

8

9

18

-

-

-

5.5

7.5

-

-

0.004

0.7

7

4L

0.004

3.5

18

3

6

-

-

-

5

6

-

-

DS12654 - Rev 5 page 34/44

7

7.1

VNQ9080AJ

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

PowerSSO-16 package information

Bottom view

Figure 46. PowerSSO-16 package dimensions ggg C A-B D D2

D3 ggg C A-B D minimum solderable area

E3 E2

Section A-A

θ 2 h

A A2

A1 e for dual gauge only eee C b ddd C D

N

A

D

A ccc C

SEATING PLANE

C

2x f f f C A-B

D

θ 3

Section B-B

b

H

S h

B

θ 1

R1

R

GAUGE PLANE

θ

L1

B

L

WITH PLATING

1.2

for dual gauge only c c1

E1 E index area

(0.25D x 0.75E1)

2x aaa C D

Top view

1 2 3

B

8017965_Rev_9

A N/2

2x N/2 TIPS bbb C b1

BASE METAL

GAPG1605141159CFT

DS12654 - Rev 5 page 35/44

DS12654 - Rev 5

Symbol

E2

E3 h

L

L1

N

R

R1

S c1

D

D2

D3 e

E

E1

A

A1

A2 b b1 c

Θ

Θ1

Θ2

Θ3 aaa bbb ccc ddd eee fff ggg

Table 16. PowerSSO-16 mechanical data

Millimeters

Typ.

Min.

0°

0°

5°

5°

0.00

1.10

0.20

0.20

0.19

0.19

0.25

0.20

4.90 BSC

3.31

2.61

0.50 BSC

6.00 BSC

3.90 BSC

2.20

1.49

0.25

0.40

0.60

1.00 REF

16

0.07

0.07

0.20

Tolerance of form and position

0.10

0.10

0.08

0.08

0.10

0.10

0.15

VNQ9080AJ

PowerSSO-16 package information

2.80

0.50

0.85

Max.

8°

1.60

0.30

0.28

0.25

0.23

15°

15°

1.70

0.10

3.91

page 36/44

7.2

VNQ9080AJ

PowerSSO-16 packing information

PowerSSO-16 packing information

Figure 47. PowerSSO-16 reel 13"

Access Hole at

Slot Location

( 40 mm min.)

A D

Description

Base quantity

Bulk quantity

A (max)

B (min)

C (+0.5, -0.2)

D (min)

N

W1 (+2 /-0)

W2 (max)

1. All dimensions are in mm.

C

If present, tape slot in core for tape start:

2.5 mm min. width x

10.0 mm min. depth

B

Table 17. Reel dimensions

Value

(1)

2500

2500

330

1.5

13

20.2

100

12.4

18.4

W2

W1

N

TAPG2004151655CFT

DS12654 - Rev 5 page 37/44

DS12654 - Rev 5

VNQ9080AJ

PowerSSO-16 packing information

0.30 ±0.05

Figure 48. PowerSSO-16 carrier tape

P

2

2.0 ±0.1

P

0

4.0 ±0.1

1.55 ±0.05

X

1.75 ±0.1

1.6 ±0.1

F

W

B

0

K

1

K

0

SECTION X - X

R 0.5

Typical

Y

X

Y

P

1

REF 4.18

REF 0.6

SECTION Y - Y

REF 0.5

A

0

GAPG2204151242CFT

Table 18. PowerSSO-16 carrier tape dimensions

Description

A

0

B

0

K

0

K

1

F

P

1

W

1. All dimensions are in mm.

Value

(1)

6.50 ± 0.1

5.25 ± 0.1

2.10 ± 0.1

1.80 ± 0.1

5.50 ± 0.1

8.00 ± 0.1

12.00 ± 0.3

Figure 49. PowerSSO-16 schematic drawing of leader and trailer tape

Embossed carrier

Punched carrier

8 mm & 12 mm only

END

Carrier tape

Round sprocket holes

START

Top cover tape

Elongated sprocket holes

(32 mm tape and wider)

Trailer

160 mm minimum

Top cover tape

Components

User direction feed

100 mm min.

Leader

400 mm minimum

GAPG2004151511CFT page 38/44

7.3

PowerSSO-16 marking information

Figure 50. PowerSSO-16 marking information

VNQ9080AJ

PowerSSO-16 marking information

Special function digit

&: Engineering sample

<blank>: Commercial sample

PowerSSO-16 TOP VIEW

(not to scale)

GADG0310161234SMD

Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS12654 - Rev 5 page 39/44

VNQ9080AJ

Revision history

Date

11-Sep-2018

24-Sep-2020

17-Sep-2021

26-Jan-2022

16-Jun-2022

Revision

1

2

3

4

5

Table 19. Document revision history

Changes

Initial release.

Updated cover page, Figure 1. Block diagram , Table 3. Absolute maximum ratings.

Updated Main electrical characteristics, Section 2.4 Waveforms and Section 3 Protections .

Added Application information .

•

•

Added:

Section 5 Maximum demagnetization energy (Vcc = 16 V) ;

Section 6 Package and PCB thermal data .

•

•

•

•

•

•

Updated:

Figure 12. Application diagram;

Figure 16. Analog HSD – open-load detection in off-state;

Table 4. Thermal data;

Table 6. Switching;

Table 9. Current Sense;

Section 7.1 PowerSSO-16 package information.

•

•

Minor text changes in:

Table 3. Absolute maximum ratings;

Table 5. Power section.

Updated features list in cover page.

Updated Table 8. Protections and Table 9. Current Sense .

Updated Figure 12. Application diagram , Figure 13. Simplified internal structure , Section 4.2

Immunity against transient electrical disturbances and Section 4.3 MCU I/Os protection .

Added

Section 2.5 Electrical characteristics (curves) .

Minor text changes.

DS12654 - Rev 5 page 40/44

VNQ9080AJ

Contents

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1

Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3

Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5

Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.1

Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2

Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3

Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4

Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.1

GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.1

Diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2

Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4

CS - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4.1

4.4.2

Principle of Current Sense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Short to V

CC

and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Maximum demagnetization energy (Vcc = 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.1

PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1

PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2

PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.3

PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

DS12654 - Rev 5 page 41/44

VNQ9080AJ

List of tables

List of tables

Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 11. Current sense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. Current Sense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 14. PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 17. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18. PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DS12654 - Rev 5 page 42/44

VNQ9080AJ

List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Switching time and pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Current Sense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. t

DSTKON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Latch-off mode - Intermittent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. Auto-restart mode - Intermittent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Auto-restart mode - Permanent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14. I

GND(ON)

vs I out

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15. Logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. Logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17. High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18. Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19. Logic input hysteresis voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20. FaultRST input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 21. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22. On-state resistance vs T

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 23. On-state resistance vs V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 25. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 26. W

ON

vs T

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. W

OFF

vs T

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 28. I

LIMH

vs T

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 29. OFF-state open-load voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 30. V

SENSE

clamp vs T

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 31. V

SENSEH

vs T

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 32. Application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 33. Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 34. M0-9 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 35. Current Sense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 36. Current Sense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 37. Analog HSD – open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 38. Open-load / short to V

CC

condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 39. Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 40. Maximum turn off energy versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 41. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 42. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 43. R thj-amb

vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 44. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . . . . . . . . . . . . . . . . 33

Figure 45. Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 46. PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 47. PowerSSO-16 reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 48. PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 49. PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 50. PowerSSO-16 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DS12654 - Rev 5 page 43/44

VNQ9080AJ

IMPORTANT NOTICE – READ CAREFULLY

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DS12654 - Rev 5 page 44/44