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Chip-Level Editor
2.3.3
1. Click each drop-arrow (in parameter value fields) and make your selections.
Some parameters are integer values. Set these values by clicking the up/down arrows, or doubleclick the value and type in the value. If you type a value that is out of range, an error message appears in the lower-left corner.
2. Repeat this process for all placed user modules.
Global Resources
Global Resources are hardware settings that determine the underlying operation of the part (for the entire application). For example, the CPU clock designates the clock speed of the M8C.
Note that Global Resource options differ slightly for each device family.
To update and save Global Resources:
1. Click each drop-arrow (in parameter value fields) and make your selections.
Some parameters in Global Resources are specified as integer values (such as 24V1 and 24V2).
Set these values by clicking the up/down arrows or double-clicking the value and typing over them. If you enter an out of range value, you see a dialog box specifying the acceptable range.
Click OK to close the dialog box.
2. The current settings for the Global Resources can be saved as default settings. Right-click on any Global Resource name and select Update Default Values. This action saves all Global
Resource settings to the \Preferences directory under the PSoC Designer installation path.
Use these settings for any other project by right-clicking any Global Resource name and selecting Restore Default Values. If no custom default values are saved, then the menu item and the right-click to Restore Default Settings restore the factory default Global Resource Settings.
The Global Resources available in PSoC Designer are shown and described briefly. Different PSoC
Devices have different global resources. The figure shown is typical.
Figure 2-5. Global Resources Example.
8 Bit Capture or FreeRun Prescaler
Selects which 8 bits of the 16-bit Free Running Timer are captured when in bit mode.
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32K_Select
The 32K_Select parameter allows selection of the internal 32 kHz oscillator or an external crystal oscillator. A complete discussion of the implications of this selection is found in the PSoC Technical
Reference Manual.
A_Buf_Power
A_Buf_Power allows the user to select the power level for the analog output buffers of the PSoC.
These buffers are used to supply internal analog signals to external pins on the PSoC. Power levels may affect the frequency response and current drive capability of the output buffers. Complete tables for the AC Analog Output Buffer Specifications and DC Analog Output Buffer Specifications are contained in the applicable device data sheet.
AGNDBypass
A provision is made in some versions of the PSoC device to provide an external AGND bypass capacitor to reduce the small amounts of switching noise present on the internal AGND. This feature is switched on and off using the AGNDBypass global parameter. Typical values for the external bypass capacitor are 0.01
μF and should not generally exceed 10 μF. The recommended value is 1
μF.
Analog Power
This parameter controls the power to the analog section of the PSoC. Power is controlled in three stages:
1. All Analog Blocks Off
2. Continuous Time Blocks ON/Switched Capacitor Blocks OFF
3. Continuous Time Blocks ON/Switched Capacitor Blocks ON
For each of the two 'ON' cases, select reference drive levels of high, medium, and low to choose the current drive capability for the internal reference buffers. All selections of this parameter, whether used as a User Module Parameter or this Global Resource, need to agree. This selection affects the total power consumption of the PSoC. Each user module using the reference and the opamp block associated with it adds slightly to the power consumed by the device. Since the internal reference is used as an integral part of most switched capacitor circuits, the current drive capability has an impact on the speed at which the switched capacitor block operates. In general, higher settings for this parameter allow switched capacitor circuits to operate at higher clock rates, at the expense of higher power consumption. To estimate the current (and power) consumption per opamp block, refer to the applicable table in the data sheet for the part: DC Operation Amplifier Specifications (ISOA).
Capture Clock
Selects the clock source for the Timer Capture Clock (TCAPCLK).
Capture Clock/N
Selects the Capture Clock divider value. The TCAPCLK will be Capture Clock source divided by N.
Capture Edge
Selects whether the capture timer data register has the First Hold data or the Most Recent edge data. This option applies to all four capture timers.
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CLKOUT Source
Selects one of the clocks, internal SysClk, external, low power 32 KHz, or CPUCLK to be output directly on port P0[1].
CPU_Clock
The CPU_Clock selection allows the selection of the M8C clock speed from 93.75 kHz to 24 MHz.
The CPU clock is derived directly from the SysClock. Use an external 32 kHz oscillator and the PLL
Ext_Lock to improve clock accuracy. A discussion of the main oscillator is contained in the PSoC
Technical Reference Manual.
Crystal OSC
Selects the external crystal oscillator when enabled. The external crystal oscillator shares pads
CLKIN and CLKOUT with two GPIOs; P0.0 and P0.1, respectively.
Crystal OSC Xgm
XGM is the amplifier transconductance setting and selects the calibration for the external crystal oscillator.
EFTB
The external crystal oscillator is passed through the EFTB filter when this option is enabled.
FreeRun Timer and Free Run Timer/N
Selects clock source for 16-bit free-running timer. The free-running timer generates an interrupt at a
1024-µs rate. It can also generate an interrupt when counter overflow occurs at every 16.384 ms.
The combination of the FreeRun Timer and the FreeRun Timer divider are used to obtain the
FreeRun Timer rate.
Low V Detect
Selects the level of the supply voltage at which the low voltage detect interrupt is generated.
LVD ThrottleBack
This parameter allows you to configure the PSoC to lower its own CPU clock speed under low voltage conditions. Use of this parameter and the bit it controls is discussed in the PSoC Technical Reference Manual. Not all PSoC devices incorporate this parameter and bit.
Opamp Bias
Performance of the internal opamps are tailored based upon the application under development by selecting high or low bias conditions for the analog section of the PSoC. Selecting high bias causes the opamp to consume more current but also increases its bandwidth and switching speed, lowering its output impedance. To estimate the current (and power) consumption per opamp block, including the effect from high or low selection of opamp Bias, refer to the applicable table in the data sheet for the part: DC Operation Amplifier Specifications (ISOA). To estimate the effect on AC opamp parameters, refer to the applicable AC Operational Amplifier Specifications in the device data sheet.
PLL_Mode
The PSoC Technical Reference Manual discusses use of the phase-locked loop mode.
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Power Setting [Vdd/SysClock Freq]
This parameter allows you to select the SysClock frequency and nominal operating voltage. Based upon the SysClock selected, the Internal Main Oscillator (IMO) is set with appropriate calibration settings. Since many internal clocks are derived from the SysClock, you see significant device powerconsumption savings by lowering the SysClock frequency, if the implemented design permits it.
Ref Mux
The Ref Mux source selection is used to control the range and (potential) accuracy of various analog resources. The reference chosen controls the maximum voltage that is input to a switched capacitor circuit and output from a switched capacitor circuit. Both the analog ground level and the peak-topeak voltage are selected using this parameter. Values specified with the Ref Mux parameter are in pairs and consist of [AGND level ± full scale]. Keep in mind that selecting Vdd (supply voltage) as a reference level couples Vdd changes into the AGND input of internal resources. This directly affects absolute accuracy of measurements. Using the internal bandgap reference results in better accuracy but may not offer an exact Vdd/2 input reference. Choices of ± full-scale values also offer a number of options. These full-scale values may be based on the PSoC internal references or on external input voltages. The ± full scale values present constraints similar to those for AGND in terms of Vdd variation and absolute range of input/output. Individual design criteria dictate the best selection for the AGND and ± full-scale values. Further discussion of the analog reference can be found in the
PSoC Technical Reference Manual.
Sleep_Timer
The Sleep_Timer parameter selects the timing of the sleep interrupt, if enabled. When the sleep interrupt is active, and the processor is in a sleep state, it is awakened at the rate specified with this parameter. The Watchdog Reset, if enabled, occurs after three rollover events in the sleep timer (if the Watchdog counter is not reset). A complete discussion of the relation of these two elements is found in the PSoC Technical Reference Manual.
Supply Voltage
Selects the nominal operating voltage to be either 3.3V or 5V.
SwitchModePump
An integrated switch mode pump circuit is available for operation of the device from very low voltage sources. The pump requires a few external components and can be configured to automatically turn on as supply voltage drops. Further discussion of the switch mode pump is found in the PSoC Tech-
nical Reference Manual.
SysClock_Source and SysClock*2 Disable
These parameters allow you to select the 24 MHz system SysClock from an internal or external source. The SysClock*2 Disable parameter allows the internal 48 MHz clock to be shut off. A complete discussion of system clocking is found in the PSoC Technical Reference Manual.
Timer Clock
Selects the clock source for the 12-bit down counting internal timer (TIMERCLK).
Timer Clock/N
Selects the Timer Clock divider value. The TIMERCLK will be Timer Clock source divided by N.
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Trip Voltage [LVD (SMP)]
A precision POR circuit is integrated into the PSoC. This parameter allows the user to select voltage levels that the PSoC uses to internally monitor its supply voltage. Two levels are specified in the parameter with the syntax <LVD (SMP)>. LVD is the value at which the internal low voltage comparator asserts its control signal. SMP is the level at which the integrated switch mode pump is enabled.
Although selection of SMP is implicit in the selection of LVD, if no switch mode pump circuitry is used, the part is reset if supply voltage falls too low. At the point when the supply voltage exceeds the threshold level, the part resumes operation as if the power was switched off and on (POR). Further discussion of the switch mode pump and low voltage detect is found in the PSoC Technical Ref-
erence Manual.
USB Clock
Selects the source for the USB SIE.
USB Clock/2
This option divides the USB clock source by 2 when the source is an external crystal oscillator.
When the USB clock is the internal 24 MHz Oscillator, then the divide by 2 is always enabled.
V Keep-alive
Allows voltage regulator to source upto 20 µA of current when the voltage regulator is disabled.
V Reg
A 3.3 V regulator output is placed on the pin P1[2] when Enabled, and when Vcc is above 4.35 V. A
1 µF min, 2 µF max capacitor is required on VREG output.
V Reset
Selects the Power on Reset (POR) voltage level.
VC1 and VC2
These resources are clocks that can be chained to provide various internal clock frequencies used for digital or analog blocks. A complete discussion of system clocking is found in the PSoC Technical
Reference Manual.
VC3_Source and VC3_Divider
VC3 is a system clock resource similar to the VC1 and VC2 resources. The main difference between it and VC1 and VC2 is that VC3 may be chained from one of several clock sources and may not be used as an input clock as flexibly as VC1 and VC2. You cannot use it as a direct input to the analog section of the PSoC. It can be used as an input to a digital PSoC block and then used to derive a clock that can be used in many more places. For this reason, it is important to evaluate clocking options as a PSoC design is being developed. Often, rearranging clock sources according to where they are most easily connected solves clocking problems. A complete discussion of system clocking is found in the PSoC Technical Reference Manual.
Watchdog Enable
This parameter activates the Watchdog Timer. The Watchdog Timer is based on a counter that counts three sleep timer events. To prevent system reset, you must clear this counter before three sleep timer state events occur, or the PSoC is internally reset. The duration of each sleep timer event is selected using the Sleep_Timer parameter in the Global Resources frame of PSoC
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