Functional overview STM32MP157C/F
3.27 Voltage reference buffer (VREFBUF)
The STM32MP157C/F devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin.
The internal voltage reference buffer supports four voltages:
• 1.5 V
• 1.8 V
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.
Figure 4. Voltage reference buffer
VREFBUF
Bandgap +
V
DDA
DAC, ADC
-
VREF+
Low frequency cut-off capacitor
100 nF
MSv40197V1
3.28 Digital filter for sigma delta modulators (DFSDM1)
The device embeds one DFSDM with support for 6 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs.
The DFSDM peripheral is dedicated to interface external Σ∆ modulators to
STM32MP157C/F and perform digital filtering of the received data streams. Σ∆ modulators are used to convert analog signals into digital serial streams that constitute the inputs of the
DFSDM. The DFSDM can also interface PDM (pulse density modulation) microphones and perform the PDM to PCM conversion and filtering (hardware accelerated). The DFSDM features optional parallel data stream inputs from internal ADC peripherals or
STM32MP157C/F memory (through DMA/CPU transfers into DFSDM).
The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user-defined filter parameters with up to 24-bit final ADC resolution.
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STM32MP157C/F Functional overview
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1-wire interface support
– PDM (pulse density modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0…20 MHz
• Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):
– internal sources: ADC data or memory data streams (DMA)
• 6 digital filter modules with adjustable digital signal processing:
– Sinc x filter: filter order/type (1…5), oversampling ratio (1…1024)
– integrator: oversampling ratio (1…256)
• Up to 24-bit output data resolution, signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM0)
• Analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sinc x digital filter (order = 1…3, oversampling ratio =
1…32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
• Short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1…256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
• Break signal generation on analog watchdog event or on short circuit detector event
• Extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
• DMA capability to read the final conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence
• “Regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
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