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Chapter
26
Dividing Frequencies
When would you need to divide the frequency of a TTL signal?
Sometimes you may need to use an internal signal at a certain frequency, but this frequency is not available on your data acquisition
(DAQ) device. In order to get the frequency you need, you can divide the available device frequencies. You can also divide the frequency of an external signal. Frequency division is outputting a pulse or pulse train from a counter every N cycles of an internal or external source.
Counters can only decrease (or divide-down) the frequency of the source signal. The resulting divided-down frequency is equal to the input frequency/N (timebase divisor). N ( timebase divisor) can only be an integer number, not a real number, and must also be greater than 1.
Performing frequency division on a internal signal is called a down counter ; whereas, frequency division on an external signal is called a signal divider . Figure 26-1 shows how to wire counters to perform frequency division.
Frequency Division for a Signal Divider
Frequency Division for a Down Counter
Figure 26-1. Wiring Your Counters for Frequency Division
In order to divide down frequencies, you must use Intermediate VIs instead of Easy VIs. For a LabVIEW example on frequency division, refer to How to Generate Pulses and Pulse Trains VI, (pulse generation method 5) in examples \ daq \ counter.llb
. The diagram in
National Instruments Corporation 26-1 LabVIEW Data Acquisition Basics Manual
Chapter 26 Dividing Frequencies
Figure 26-2 shows how you can program a signal divider using the
Down Counter or Divide Config, Counter Start, and Counter Stop VIs.
Figure 26-2. Programming a Single Divider for Frequency Division
The Down Counter or Divide Config VI configures the specified counter to divide the SOURCE signal by the timebase divisor value and output a signal when the counter reaches its terminal count (TC).
Using Down Counter or Divide Config VI, you can configure the type of output to be pulse or toggled. The diagram above outputs a high pulse lasting one cycle of the source signal once the counter reaches its
TC. For more information on the different types of signal outputs, refer to the Down Counter or Divide Config VI description in Chapter 18,
Intermediate Counter VIs , of the LabVIEW Data Acquisition VI Reference
Manual . The diagram above counts the rising edges of the SOURCE signal, the default value of the source edge input. In order to figure out where the inputs and outputs are located on this VI, remember to use the Help window. Open this window by choosing Help » Show Help .
The Counter Start VI tells the counter to start counting the SOURCE signal edges. The counter only stops the frequency division when the stop button is pressed. The Counter Stop VI stops the counter immediately and clears the count register. It is a good idea to always check your errors at the end of an operation to see if the operation was successful.
You can alter the Down Counter or Divide Config VI to create a down counter. To do this, change the timebase value from 0.0
(external
SOURCE) to a frequency available on your counter. With the Am9513 chip, you can choose timebases of 1 MHz, 100 kHz, 10 kHz, 1 kHz, and
100 Hz. With the DAQ-STC chip, you can choose timebases of
20 MHz and 100 kHz.
LabVIEW Data Acquisition Basics Manual 26-2 National Instruments Corporation
Chapter 26 Dividing Frequencies
Instead of triggering frequency division for signal dividers and down counters by software, as was previously discussed, you can trigger using the GATE signal. You can trigger while the GATE signal is high, low or on the rising or falling edge. For more information, look at the
Down Counter or Divide Config VI description in Chapter 18,
Intermediate Counter VIs , of the LabVIEW Data Acquisition VI Reference
Manual .
National Instruments Corporation 26-3 LabVIEW Data Acquisition Basics Manual
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