USER`S MANUAL

USER’S MANUAL

S3F80N8

8-Bit CMOS Microcontrollers

November, 2008

REV 1.10

Confidential Proprietary of Samsung Electronics Co., Ltd

Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

"Typical" parameters can and do vary in different applications. All operating parameters, including

"Typicals" must be validated for each customer application by the customer's technical experts.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the

Samsung product could create a situation where personal injury or death may occur.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold

Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that

Samsung was negligent regarding the design or manufacture of said product.

S3F80N8 8-Bit CMOS Microcontrollers

User's Manual, Revision 1.10

Publication Number: 21.10-S3-F80N8-112008

© 2008 Samsung Electronics

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and

objectives.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Ri, Giheung- Eup

Yongin-City, Gyeonggi-Do, Korea

C.P.O. Box #37, Suwon 449-900

TEL: (82)-(031)-209-5238

FAX: (82)-(031)-209-6494

Home-Page URL: Http://www.samsungsemi.com

Printed in the Republic of Korea

NOTIFICATION OF REVISIONS

ORIGINATOR:

Samsung Electronics, SSCR

PRODUCT NAME:

S3F80N8 8-bit CMOS Microcontroller

DOCUMENT NAME:

S3F80N8 User's Manual, Revision 1.10

DOCUMENT NUMBER:

21.10-S3-F80N8-112008

EFFECTIVE DATE:

November, 2008

DIRECTIONS:

Revision 1.10

REVISION HISTORY

Revision No

0.00

1.00

Description of Change

Preliminary Spec for internal release only

First revision

Author(s) Date

May, 2007

June, 2008

October,2008

S3F80N8 MICROCONTROLLER iii

REVISION DESCRIPTIONS FOR REVISION 1.0

Chapter

Chapter Name

01. Product Overview

02. Address Space

12. Embedded Flash

Memory Interface

13. Electrical Data

Page

1-3

2-3

12-2

13-2

Subjects (Major changes comparing with last version)

‘External clock Range’ is changed from ‘1MHz to 6MHz ’ to ‘1MHz to

10MHz’. ‘operating voltage’ is changed from ‘2.2V~5.5V’ to ‘2.0 V~

5.5V’.

Figure 2-2 Smart Option: LVR level 3.9V Selection Bits is changed from ’01’ to ‘11’.

TEST pin voltage when read/write FLASH ROM is changed from

12.5V to 11.0V.

The max value of Vol2 is changed from 1.0V to 1.5V.

The pull up resister of I/O ports is changed from ’30k

Ω 70kΩ 100kΩ’ to ’25k

Ω 50kΩ 100kΩ’.

13-9

Add ESD characteristic.

15-9

ICE & Writer updated.

15. Development tool

iv S3F80N8 MICROCONTROLLER

REVISION DESCRIPTIONS FOR REVISION 1.1

Chapter

Chapter Name

12. Electrical Data

14. S3F80N8 Flash MCU

Subjects (Major changes comparing with last version)

Page

12-3 Idd3 revision from 2.5~5uA @25

°C to 2.5~10uA @-40°C ~85°C

14-2

TEST pin voltage when write FLASH ROM is changed from 11.0V to

11.0V

± 0.25V.

S3F80N8 MICROCONTROLLER v

Preface

The S3F80N8 Microcontroller User's Manual is designed for application designers and programmers who are using the S3F80N8 microcontroller for application development. It is organized in two main parts:

Part I Programming Model Part II Hardware Descriptions

Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters:

Chapter 1

Chapter 2

Chapter 3

Product Overview

Address Spaces

Addressing Modes

Chapter 4

Chapter 5

Chapter 6

Control Registers

Interrupt Structure

Instruction Set

Chapter 1, "Product Overview," is a high-level introduction to S3F80N8 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the

S3F8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3F80N8 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3F8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in

Part II. If you are not yet familiar with the S3F8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the S3F80N8 microcontroller. Also included in Part II are electrical, mechanical data. It has 9chapters:

Chapter 7

Chapter 8

Clock Circuit

RESET and Power-Down

Chapter 9 I/O Ports

Chapter 10 Basic Timer & Timer0

Chapter 11 Low Voltage Reset

Chapter 12

Chapter 13

Chapter 14

Electrical Data

Mechanical Data

S3F80N8 Flash MCU

Chapter 15 Development Tools

Two order forms are included at the back of this manual to facilitate customer order for S3F80N8 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

vi S3F80N8 MICROCONTROLLER

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

S3F8-Series Microcontrollers........................................................................................................................1-1

S3F80N8 Microcontroller ..............................................................................................................................1-1

Features ........................................................................................................................................................1-2

Block Diagram ...............................................................................................................................................1-3

Pin Assignment .............................................................................................................................................1-4

Pin Descriptions ............................................................................................................................................1-5

Pin Circuits ....................................................................................................................................................1-6

Chapter 2 Address Spaces

Overview........................................................................................................................................................2-1

Program Memory (ROM)...............................................................................................................................2-1

Smart Option .................................................................................................................................................2-2

Register Architecture.....................................................................................................................................2-4

Working Registers.....................................................................................................................................2-5

Using The Register Points ........................................................................................................................2-6

Register Addressing ......................................................................................................................................2-8

Common Working Register Area (C0H–CFH)..........................................................................................2-10

4-bit Working Register Addressing ...........................................................................................................2-11

8-bit Working Register Addressing ...........................................................................................................2-13

System and User Stack.................................................................................................................................2-15

Chapter 3 Addressing Modes

Overview........................................................................................................................................................3-1

Register Addressing Mode (R)......................................................................................................................3-2

Indirect Register Addressing Mode (IR) ........................................................................................................3-3

Indexed Addressing Mode (X).......................................................................................................................3-7

Direct Address Mode (DA) ............................................................................................................................3-10

Indirect Address Mode (IA) ...........................................................................................................................3-12

Relative Address Mode (RA).........................................................................................................................3-13

Immediate Mode (IM) ....................................................................................................................................3-14

S3F80N8 MICROCONTROLLER vii


(Continued)

Chapter 4 Control Registers

Overview ....................................................................................................................................................... 4-1

Chapter 5 Interrupt Structure

Overview ....................................................................................................................................................... 5-1

Interrupt Types ......................................................................................................................................... 5-2

S3F80N8 Interrupt Structure .................................................................................................................... 5-3

System-Level Interrupt Control Registers ................................................................................................ 5-5

Interrupt Processing Control Points ......................................................................................................... 5-6

Peripheral Interrupt Control Registers...................................................................................................... 5-7

System Mode Register (SYM).................................................................................................................. 5-8

Interrupt Mask Register (IMR).................................................................................................................. 5-9

Interrupt Priority Register (IPR) ................................................................................................................ 5-10

Interrupt Request Register (IRQ) ............................................................................................................. 5-12

Interrupt Pending Function Types ............................................................................................................ 5-13

Interrupt Source Polling Sequence .......................................................................................................... 5-14

Interrupt Service Routines........................................................................................................................ 5-14

Generating interrupt Vector Addresses.................................................................................................... 5-15

Nesting of Vectored Interrupts ................................................................................................................. 5-15

Instruction Pointer (IP).............................................................................................................................. 5-15

Fast Interrupt Processing ......................................................................................................................... 5-15

Procedure for Initiating Fast Interrupts..................................................................................................... 5-16

Fast Interrupt Service Routine ................................................................................................................. 5-16

Relationship to Interrupt Pending Bit Types............................................................................................. 5-16

Programming Guidelines.......................................................................................................................... 5-16

Chapter 6 Instruction Set

Overview ....................................................................................................................................................... 6-1

Data Types ............................................................................................................................................... 6-1

Register Addressing ................................................................................................................................. 6-1

Addressing Modes.................................................................................................................................... 6-1

Flags Register (FLAGS) ........................................................................................................................... 6-6

Flag Descriptions...................................................................................................................................... 6-7

Instruction Set Notation ............................................................................................................................ 6-8

Condition Codes....................................................................................................................................... 6-12

Instruction Descriptions ............................................................................................................................ 6-13

viii S3F80N8 MICROCONTROLLER


(Continued)

Part II Hardware Descriptions

Chapter 7 Clock Circuit

Overview........................................................................................................................................................7-1

System Clock Circuit.................................................................................................................................7-1

Main Oscillator Circuits .............................................................................................................................7-2

Clock Status During Power-Down Modes ................................................................................................7-3

System Clock Control Register (CLKCON) ..............................................................................................7-4

Chapter 8

Reset and Power-Down

System Reset ................................................................................................................................................8-1

Overview ...................................................................................................................................................8-1

Normal Mode Reset Operation .................................................................................................................8-3

Hardware Reset Values ............................................................................................................................8-3

Power-Down Modes ......................................................................................................................................8-5

Stop Mode.................................................................................................................................................8-5

Idle Mode ..................................................................................................................................................8-6

Chapter 9 I/O Ports

Overview........................................................................................................................................................9-1

Port Data Registers...................................................................................................................................9-2

Port 0.........................................................................................................................................................9-3

Port 1.........................................................................................................................................................9-5

Port 2.........................................................................................................................................................9-9

Port3 (32-pin S3F80N8)............................................................................................................................9-11

Chapter 10 Basic Timer and Timer 0

Overview........................................................................................................................................................10-1

Basic Timer (BT) ...........................................................................................................................................10-1

Basic Timer Control Register (BTCON)....................................................................................................10-2

Basic Timer Function Description .............................................................................................................10-3

8-bit Timer/Counter 0 ....................................................................................................................................10-7

Timer/Counter 0 Control Register (T0CON) .............................................................................................10-7

Timer 0 Function Description ....................................................................................................................10-9

S3F80N8 MICROCONTROLLER ix


(Continued)

Chapter 11 Low Voltage Reset

Overview ....................................................................................................................................................... 11-1

Chapter 12 Electrical Data

Overview ....................................................................................................................................................... 12-1

Chapter 13 Mechanical Data

Overview ....................................................................................................................................................... 13-1

Chapter 14 S3F80N8 Flash MCU

Overview ....................................................................................................................................................... 14-1

On Board Writing .......................................................................................................................................... 14-3

Chapter 15 Development Tools

Overview ....................................................................................................................................................... 15-1

Target Boards ............................................................................................................................................ 15-1

Programming Socket Adapter.................................................................................................................... 15-1

TB80N8 Target Board................................................................................................................................ 15-3

OTP/MTP Programmer (Writer)................................................................................................................. 15-8

x S3F80N8 MICROCONTROLLER

List of Figures

Number Number

1-2

1-3

S3F80N8 Pin Assignments (32-pin SOP/SDIP) .........................................................1-4

S3F80N8 Pin Assignments (28-pin SOP) ..................................................................1-4

2-9

2-10

2-11

2-12

2-13

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

3-11

2-3 Register file.................................................................................................................2-4

2-4 8-Byte Working Register Areas (Slices) .....................................................................2-5

2-5

2-6

Contiguous 16-Byte Working Register Block .............................................................2-6

Non-Contiguous 16-Byte Working Register Block .....................................................2-7

Common Working Register Area................................................................................2-10

4-Bit Working Register Addressing ............................................................................2-12

4-Bit Working Register Addressing Example .............................................................2-12

8-Bit Working Register Addressing ............................................................................2-13

8-Bit Working Register Addressing Example .............................................................2-14

Indirect Register Addressing to Register File.............................................................3-3

Indirect Register Addressing to Program Memory .....................................................3-4

Indirect Working Register Addressing to Register File ..............................................3-5

Indirect Working Register Addressing to Program or Data Memory ..........................3-6

Indexed Addressing to Register File ..........................................................................3-7

Indexed Addressing to Program or Data Memory with Short Offset ..........................3-8

Indexed Addressing to Program or Data Memory......................................................3-9

Direct Addressing for Load Instructions .....................................................................3-10

Direct Addressing for Call and Jump Instructions ......................................................3-11

S3F80N8 MICROCONTROLLER xi

10-3

10-4

10-5

10-6

10-7

10-8

10-9

9-9

9-10

9-11

9-12

9-13

10-1

7-3

7-4

7-5

7-6

8-1

9-1

9-2

9-3

9-4

9-5

9-6

9-7

5-3

5-5

5-6

5-9

6-1

List of Figures

(Continued)

Number Number

ROM Vector Address Area ........................................................................................ 5-4

System Mode Register (SYM) ................................................................................... 5-8

Interrupt Mask Register (IMR) ................................................................................... 5-9

Interrupt Request Register (IRQ)............................................................................... 5-12

System Flags Register (FLAGS) ............................................................................... 6-6

RC Oscillator MODE 2(fosc)...................................................................................... 7-2

System Clock Circuit Diagram ................................................................................... 7-3

System Clock Control Register (CLKCON) ............................................................... 7-4

STOP Control Register (STPCON)............................................................................ 7-4

Low Voltage Reset Circuit ......................................................................................... 8-2

Port 0 High-Byte Control Register (P0CONH)........................................................... 9-3

Port 0 Low-Byte Control Register (P0CONL) ............................................................ 9-4

Port 0 Pull-up Control Register (P0PUR) .................................................................. 9-4




External Interrupt Enable Register (EXTINT) ............................................................ 9-7




Port 3 Control Register (P3CON) .............................................................................. 9-11


Basic Timer Control Register (BTCON)..................................................................... 10-2

Oscillation Stabilization Time on STOP Mode Release............................................. 10-5

Basic Timer Block Diagram ....................................................................................... 10-6

Timer 0 Control Register (T0CON) ............................................................................ 10-8

Simplified Timer 0 Function Diagram: Interval Timer Mode ...................................... 10-9

Simplified Timer 0 Function Diagram: PWM Mode.................................................... 10-10

Simplified Timer 0 Function Diagram: Capture Mode................................................ 10-11

Timer 0 Block Diagram .............................................................................................. 10-12

xii S3F80N8 MICROCONTROLLER

List of Figures

(Continued)

14-3

15-2

15-3

15-4

12-9

13-1

13-2

13-3

14-1

Number Number

11-1

12-1

12-2

Low Voltage Reset Circuit ..........................................................................................11-2

Stop Mode Release Timing When Initiated by External Interrupt ..............................12-4

Stop Mode Release Timing When Initiated by RESET ..............................................12-4

12-5

12-6

Clock Timing Measurement at XIN.............................................................................12-7

Input Timing for External Interrupts ............................................................................12-8

The Circuit Diagram to Improve EFT Characteristics.................................................12-9

28-SOP-375 Package Dimensions.............................................................................13-1

32-SOP-450A Package Dimensions ..........................................................................13-2

32-SDIP-400 Package Dimensions............................................................................13-3

S3F80N8 Pin Assignments (32-pin SOP/SDIP) .........................................................14-1

PCB Design Guide for on Board Programming..........................................................14-3

TB80N8 Target Board Configuration..........................................................................15-3

50-Pin Connector Pin Assignment for user System ...................................................15-6

TB80N8 Probe Adapter Cable....................................................................................15-6

S3F80N8 MICROCONTROLLER xiii

12-7

12-9

12-10

14-1

15-2

8-1

9-1

9-2

12-2

12-4

List of Tables

Number

1-1

Number

KS86C0004 Pin Descriptions .....................................................................................1-5

4-1 Registers.....................................................................................................................4-1

5-1

5-2

Interrupt Control Register Overview ...........................................................................5-5

Interrupt Source Control and Data Registers .............................................................5-7

S3F80N8 Register and Values after Reset ................................................................8-3

S3F80N8 Port Configuration Overview ......................................................................9-1

Port Data Register Summary......................................................................................9-2

DC Electrical Characteristics ......................................................................................12-2

Data Retention Supply Voltage in Stop Mode ............................................................12-4

RC Oscillation (Mode2) Characteristics .....................................................................12-7

Input Low Width Electrical Characteristics .................................................................12-8

LVR Circuit Characteristics ........................................................................................12-8

Descriptions of Pins Used to Read/Write the Flash ROM..........................................14-2

Setting of the Jumper in TB80N8 ...............................................................................15-5

S3F80N8 MICROCONTROLLER xv

List of Programming Tips

Description

Chapter 2: Address Spaces

Page

Number

Setting Register Pointers ........................................................................................................................ 2-6

Using RPs to Caculate the Sums of a series of Registers ..................................................................... 2-7

Addressing the Common Working Register Area .................................................................................. 2-11

Standard Stack Operations Using PUSH and POP ............................................................................... 2-16

S3F80N8 MICROCONTROLLER xvii

List of Register Descriptions

Register

Identifier

Full Register Name Page

Number

BTCON Basic Timer Control Register ..................................................................................... 4-4

CLKCON Clock Control Register ............................................................................................... 4-5

EXTINT External Interrupt Enable Register ............................................................................. 4-6

EXTPND External Interrupt Enable Register ............................................................................. 4-7

FLAGS System Flags Register ............................................................................................... 4-8

IMR

IPH

IPL

IPR

IRQ

P0CONH

P0CONL

Interrupt Mask Register .............................................................................................. 4-9

Instruction Pointer (High Byte) ................................................................................... 4-10

Instruction Pointer (Low Byte) .................................................................................... 4-10

Interrupt Priority Register ........................................................................................... 4-11

Interrupt Request Register ......................................................................................... 4-12

Port 0 Control Register (High Byte)............................................................................ 4-13

Port 0 Control Register (Low Byte) ............................................................................ 4-14

P0PUR

P1CONH

P1CONL

P1PUR

P2CONH

P2CONL

P2PUR

P3CON

P3PUR

PP

RP0

RP1

SPL

STOPCON

SYM

T0CON

Port 0 Pull-Up Register............................................................................................... 4-15

Port 1 Control Register............................................................................................... 4-16



Port 2 Control Register (High Byte)............................................................................ 4-19

Port 2 Control Register (Low Byte) ............................................................................ 4-20




Register Page Pointer ................................................................................................ 4-24

Register Pointer 0....................................................................................................... 4-25

Register Pointer 1....................................................................................................... 4-25

Stack Pointer .............................................................................................................. 4-26

STOP Mode Control Register .................................................................................... 4-27

System Mode Register ............................................................................................... 4-28

Timer 0/A Control Register......................................................................................... 4-29

S3F80N8 MICROCONTROLLER xix

List of Instruction Descriptions

Instruction

Mnemonic


Number

ADD

AND

BAND

BCP

BITC

BITS

BOR

BTJRF

BTJRT

BXOR

CALL

CCF

CLR

COM

CP

CPIJNE

DA

DEC

DECW

Add ............................................................................................................................. 6-15

Logical AND ............................................................................................................... 6-16

Bit AND....................................................................................................................... 6-17

Bit Compare ............................................................................................................... 6-18

Bit Complement.......................................................................................................... 6-19

Bit Set ......................................................................................................................... 6-21

Bit OR ......................................................................................................................... 6-22

Bit Test, Jump Relative on False ............................................................................... 6-23

Bit Test, Jump Relative on True................................................................................. 6-24

Bit XOR....................................................................................................................... 6-25

Call Procedure............................................................................................................ 6-26

Complement Carry Flag ............................................................................................. 6-27

Clear ........................................................................................................................... 6-28

Complement ............................................................................................................... 6-29

Compare..................................................................................................................... 6-30

Compare, Increment, and Jump on Non-Equal ......................................................... 6-32

Decimal Adjust ........................................................................................................... 6-33

Decrement .................................................................................................................. 6-35

Decrement Word ........................................................................................................ 6-36

DIV

DJNZ

EI

Divide (Unsigned)....................................................................................................... 6-38

Decrement and Jump if Non-Zero.............................................................................. 6-39

Enable Interrupts ........................................................................................................ 6-40

ENTER

EXIT

Enter ........................................................................................................................... 6-41

Exit.............................................................................................................................. 6-42

IDLE Idle Operation............................................................................................................. 6-43

INC Increment ................................................................................................................... 6-44

INCW Increment Word.......................................................................................................... 6-45

IRET Interrupt Return .......................................................................................................... 6-46

JP Jump........................................................................................................................... 6-47

JR

LD

LDB

Jump Relative............................................................................................................. 6-48

Load............................................................................................................................ 6-49

Load Bit ...................................................................................................................... 6-51

S3F80N8 MICROCONTROLLER xxi

List of Instruction Descriptions

(Continued)

Instruction

Mnemonic

LDC/LDE

LDCD/LDED

LDCPD/LDEPD

LDCPI/LDEPI

MULT

NEXT

NOP

OR

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

RCF

RET

RL

RLC

RR

RRC

SB0

SB1

SBC

SCF

SRP/SRP0/SRP1

STOP

SUB

SWAP

TCM

TM

WFI

XOR


Number

Load Memory..............................................................................................................6-52

Load Memory and Decrement ....................................................................................6-54

Load Memory with Pre-Decrement.............................................................................6-56

Load Memory with Pre-Increment ..............................................................................6-57

Multiply (Unsigned) .....................................................................................................6-59

Next.............................................................................................................................6-60

No Operation ..............................................................................................................6-61

Logical OR ..................................................................................................................6-62

Pop from Stack ...........................................................................................................6-63

Pop User Stack (Decrementing).................................................................................6-64

Pop User Stack (Incrementing) ..................................................................................6-65

Push to Stack..............................................................................................................6-66

Push User Stack (Decrementing) ...............................................................................6-67

Push User Stack (Incrementing) ................................................................................6-68

Reset Carry Flag.........................................................................................................6-69

Return .........................................................................................................................6-70

Rotate Left ..................................................................................................................6-71

Rotate Left through Carry ...........................................................................................6-72

Rotate Right................................................................................................................6-73

Rotate Right through Carry.........................................................................................6-74

Select Bank 0..............................................................................................................6-75

Select Bank 1..............................................................................................................6-76

Subtract with Carry .....................................................................................................6-77

Set Carry Flag.............................................................................................................6-78

Set Register Pointer....................................................................................................6-80

Stop Operation............................................................................................................6-81

Subtract ......................................................................................................................6-82

Swap Nibbles..............................................................................................................6-83

Test Complement under Mask ...................................................................................6-84

Test under Mask .........................................................................................................6-85

Wait for Interrupt .........................................................................................................6-86

Logical Exclusive OR..................................................................................................6-87

xxii S3F80N8 MICROCONTROLLER

PRODUCT OVERVIEW S3F80N8_UM_REV1.10

1

PRODUCT OVERVIEW

S3F8-SERIES MICROCONTROLLERS

Samsung's S3F8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode released by interrupt

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.

S3F80N8 MICROCONTROLLER

The S3F80N8 single-chip CMOS micro-controller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture. Its design is based on the powerful SAM8RC CPU core. Stop and idle (power-down) modes were implemented to reduce power consumption.

The S3F80N8 is a micro-controller with a 8K-byte multi-time-programmable Flash ROM embedded.

Using a proven modular design approach, Samsung engineers have developed the S3F80N8 by integrating the following peripheral modules with the powerful SAM8RC core:

— Three programmable I/O port, including two 8-bit ports, one 6-bit port, for a total of 22 pins. (28-pin)

— One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).

— One 8-bit timer/counter with selectable operating modes.

The S3F80N8 is a versatile general-purpose microcontroller, which is especially suitable for use as MWO controller. It is currently available in a 28-pin SOP, 32-pin SOP and 32-pin SDIP package.

1-1


FEATURES

CPU

•

SAM8RC CPU core

Memory

•

•

ROM: 8K-Bytes flash or mask ROM

RAM: 144-Bytes

Instruction Set

•

78 instructions

•

Idle and Stop instructions added for power-down modes

Instruction Execution Time

•

400ns at 10-MHz f

OSC

(minimum)

I/O Ports

•

Two 8-bit I/O ports (P0-P1), one 4-bit I/0 ports

(P3), P1 can be used for 8 external interrupt

One 6-bit I/O port (P2, Open drain output, each pin with big driving current [80mA] function),

•

[=>26 I/O, 32-pin]

Two 8-bit I/O ports (P0-P1), P1 can be used for 8 external interrupt

One 6-bit I/O port (P2, Open drain output, each pin with big driving current [80mA] function),

[=>22 I/O, 28-pin]

Interrupts

•

3 interrupt levels and 10 interrupt sources (8 external interrupt, by falling edge or both rising edge and falling edge, and 2 internal interrupt)

•

Fast interrupt processing feature

S3F80N8_UM_REV1.10

Timers

•

Basic timer: One programmable 8-bit basic timer

(BT) for oscillation stabilization control or watchdog timer function

•

Timer0: One 8-bit timer with three operating modes: Interval, capture and PWM mode

Two Power-Down Modes

•

Idle mode: only CPU clock stops

•

Stop mode: system clock and CPU clock stop

Oscillation Source

•

External Clock: 1.0 to 10MHz f

OSC

•

External RC oscillator (Mode 2): 1 to 10MHz

Built-in RESET Circuit (LVR)

• Low-Voltage check to make system reset

• V

LVR

= 2.2/ 3.9V (by smart option)

Operating Temperature Range

•

–40

°C to +85 °C

Operating Voltage Range

•

2.0V to 5.5V

Package Type

•

28-pin SOP, 32-pin SOP and 32-pin SDIP package

1-2

S3F80N8_UM_REV1.10

BLOCK DIAGRAM


X

IN

X

OUT

Main

OSC

P2.2/CLO

P2.3/T0CLK

P2.4/T0

8-Bit

Basic

Timer

P0.0-P0.7

Port 0

P1.0-P1.7/INT0-INT7

Port 1

Internal Bus

Port I/O and Interrupt

Control

Port 2

P2.0

P2.1

P2.2/CLO

P2.3/T0CLK

P2.4/T0

P2.5

SAM8RC CPU

Port 3

P3.0-P3.3

8-Bit

Timer/

Counter

8K-byte

ROM

144-byte

Register File

LVR

TEST nRESET V

DD

V

SS

Figure 1-1. Block Diagram

1-3


PIN ASSIGNMENT

S3F80N8_UM_REV1.10

V

SS

X

OUT

X

IN

(V

PP

) TEST

P0.0

P0.1

nRESET

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.5

P3.3

P3.2

7

8

5

6

3

4

1

2

9

10

11

12

13

14

15

16

S3F80N8

32-SOP/SDIP

20

19

18

17

24

23

22

21

28

27

26

25

32

31

30

29

V

DD

P1.0/INT0 (SCLK)

P1.1/INT1 (SDAT)

P1.2/INT2

P1.3/INT3

P1.4/INT4

P1.5/INT5

P1.6/INT6

P1.7/INT7

P2.0

P2.1

P2.2/CLO

P2.3/T0CLK

P2.4/T0

P3.0

P3.1

Figure 1-2. S3F80N8 Pin Assignments (32-pin SOP/SDIP)

V

SS

X

OUT

X

IN

(V

PP

) TEST

P0.0

P0.1

nRESET

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.5

9

10

11

12

13

14

5

6

7

8

3

4

1

2

S3F80N8

28-SOP

20

19

18

17

16

15

24

23

22

21

28

27

26

25

V

DD



P1.2/INT2

P1.3/INT3

P1.4/INT4

P1.5/INT5

P1.6/INT6

P1.7/INT7

P2.0

P2.1

P2.2/CLO

P2.3/T0CLK

P2.4/T0

Figure 1-3. S3F80N8 Pin Assignments (28-pin SOP)

1-4

S3F80N8_UM_REV1.10 PRODUCT OVERVIEW

PIN DESCRIPTIONS

CLO

T0CK

T0

INT0-INT7

X

IN

X

OUT

V

DD

V

SS

TEST nRESET

Table 1-1. S3F80N8 Pin Descriptions （32-pin）

Pin

Names

P0.0 - P0.7

P1.0

P1.1

P1.2 – P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P3.0–P3.3

Pin

Type

Pin Description

I/O I/O port with bit-programmable pins.

Configurable to input or open-drain / push-pull output mode. Pull-up resistors can be assigned by software.


Configurable to input or open-drain / push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as external interrupt pins.


Configurable to input or open-drain / push-pull output mode. Pull-up resistors can be assigned by software. Pins can also be assigned individually as alternative function pins.


Configurable to input or open-drain/ push-pull output mode. Pull-up resistors can be assigned by software.

O CPU clock output

I Timer 0 clock input

I/O Timer 0 PWM output and capture input

I External interrupt input pins

I

O

System clock input and output pins

I Test signal input pin (for factory use only; must be connected to V

SS

.)

I System reset pin

– Power supply input pin

Circuit

Type

A

B

A

A

C

A

C

A

A

C

A

C

B

_

_

_

_

_

Pin

Numbers

5, 6

8 - 13

20 – 27

14 – 19

15 – 18

17 P2.2

16 P2.3

15 P2.4

20 – 27

2

3

4 _

7

Shared pins

–

INT0/SCLK

INT1/SDAT

INT2–INT7

CLO

T0CK

T0

–

P1.0 – P1.7

_

–

32 –

1 –

1-5


PIN CIRCUITS

S3F80N8_UM_REV1.10

Data

Output Disable

Open-drain

Enable

V

DD

V

DD

P-CH

Pull-up Resistor

Pull-up Enable

I/O

N-CH

V

SS

Digital Input

Data

Output Disable

Open-drain

Enable

Figure 1-4. Pin Circuit Type A

V

DD

V

DD

P-CH

Pull-up Resistor

Pull-up Enable

I/O

N-CH

V

SS

Digital Input

Interrupt Input

Figure 1-5. Pin Circuit Type B

1-6

S3F80N8_UM_REV1.10 PRODUCT OVERVIEW

Open-drain

Enable

P2CONH.1-.0

P2CONL.5-.4

CLO

M

U

X

T0

Output Disable

Data

Digital Input

V

DD

V

DD

P-CH

Pull-up Resistor

Pull-up Enable

I/O

N-CH

V

SS

Figure 1-6. Pin Circuit Type C

1-7


NOTES

S3F80N8_UM_REV1.10

1-8

S3F80N8_UM_REV1.10 ADDRESS

2

ADDRESS SPACES

OVERVIEW

The S3F80N8 micro-controller has two types of address space:

— Internal program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.

The S3F80N8 has an internal 8-Kbyte flash-programmable ROM.

There are 192 mapped registers in the internal register file. Of these, 144 are for general-purpose. (This number includes a 16-byte working register common area used as a "scratch area" for data operations, 128-byte prime register areas). 48 registers are used for the CPU and the system control, and are also mapped for peripheral controls and data registers. In the 48 register locations, 12 are not mapped.

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program codes or table data. The S3F80N8 has 8K bytes internal program memory.

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which a program execution starts after a reset is 0100H.

2-1

ADDRESS SPACES S3F80N8_UM_REV1.10

(Decimal)

8191

(HEX)

1FFFH

8K-Byte

Internal

Program

Memory Area

255 FFH

Interrupt

Vector Area

0 0H

Figure 2-1. Program Memory Address Space

SMART OPTION

Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 3CH, 3DH, and 3EH to 3FH. The S3F80N8 only uses 3EH. The unused bits must be initialized to “1”. The default value of program memory is FFH.

2-2


MSB .7

.6

.5

ROM Address: 3CH

.4

.3

.2

.1

.0

LSB

Must be initialized to 0FFH

MSB .7

.6

.5

ROM Address: 3DH

.4

.3

.2

.1

.0

LSB


MSB .7

.6

.5

ROM Address: 3EH

.4

.3

.2

.1

.0

LSB

Not used

LVR level selection bit:

10:2.2V

11:3.9V

Oscillator selection bits:

000 = f

RC

/1 (RC oscillation mode2)

LVR control bit

00=LVR disable in run mode, disable in stop mode

001 = f

RC


010 = f

RC


01=LVR disable in run mode, enable in stop mode

10=LVR enable in run mode, disable in stop mode

011 = f

RC


111 = External crystal, ceramic

11=LVR enable in run mode, enable in stop mode

MSB .7

.6

.5

ROM Address: 3FH

.4

.3

.2

.1

.0

LSB


NOTE: The unused bits must be initialized to ”1”

Figure 2-2. Smart Options

2-3


REGISTER ARCHITECTURE

In case of S3F80N8 the total number of addressable 8-bit registers is 192. Of these 192 registers, 48 bytes are for CPU and system control registers or for peripheral control and data registers, 16 bytes are used as shared working registers, and 128 registers are for general-purpose use.

Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1.

Table 2-1. S3F80N8 Register Type Summary

Register Type

General-purpose registers (including the 16-byte common working register area)

CPU and system control registers, Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

Number of Bytes

144

48

192

Not used

FFH

FCH

E0H

D0H

C0H

7FH

Prime

Register

Area

00H

CPU and system control registers

General-purpose registers

Peripheral registers and I/O ports

Figure 2-3. Register file

2-4


WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 192-byte register file one that consists of 24 four 8-byte register groups or "slices." Each can be seen by the programmer slice comprises of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.

The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area (C0H–CFH).

1 1 1 1 1 X X X

RP1 (Registers R8-R15)

Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block.

0 0 0 0 0 X X X

RP0 (Registers R0-R7)

~

Slice 24

Slice 23

Slice 2

Slice 1

Figure 2-4. 8-Byte Working Register Areas (Slices)

FFH

F8H

F7H

F0H

CFH

C0H

~

10H

FH

8H

7H

0H

2-5


USING THE REGISTER POINTS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.

(see Figures 2-5 and 2-6).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice

(see Figure 2-5). In some cases, it may be necessary to define working register areas in different (noncontiguous) areas of the register file. In Figure 2-6, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements.

)

PROGRAMMING TIP — Setting the Register Pointers

RP0

← no change, RP1 ← 48H

RP0

← 00H, RP1 ← no change

← no change, RP1 ← 0F8H

Register File

Contains 24

8-Byte Slices

0 0 0 0 1 X X X

RP1

0 0 0 0 0 X X X

RP0

8-Byte Slice

8-Byte Slice

FH (R15)

8H

7H

0H (R0)

16-Byte

Contiguous

Working

Register block

Figure 2-5. Contiguous 16-Byte Working Register Block

2-6


8-Byte Slice

F7H (R15)

F0H (R8)

1 1 1 1 0 X X X

RP1

0 0 0 0 0 X X X

RP0

Register File

Contains 24

8-Byte Slices

8-Byte Slice

7H (R7)

0H (R0)

16-Byte non-

Contiguous

Working

Register block

Figure 2-6. Non-Contiguous 16-Byte Working Register Block

)

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

RP0

← R0 + R1

R0

← R0 + R3 + C

R0

← R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used:

80H

← (80H) + (82H) + C

80H

← (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-7


REGISTER ADDRESSING

The S3F8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific

8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

Rn+1 n = Even address

Figure 2-7. 16-Bit Register Pair

2-8


Special-Purpose Registers

FFH

Control

Registers

E0H

D0H

C0H

BFH

System

Registers

CFH

RP1

Register

Pointers

RP0

Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file. After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area).

NOTE:

In the S3F80N8 microcontroller, only Page 0 is implemented.

General-Purpose Register

Prime

Registers

C0H

80H

00H

Can be Pointed by Register Pointer

Figure 2-8. Register File Addressing

2-9


COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices, locations C0H–CFH, as the active 16-byte working register block:

This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.

FFH

FFH

Page 7

Page 6

FFH

FFH

Page 5

Page 4

FFH

FFH

FFH

FFH

Page 3

Page 2

Page 1

Page 0

FFH

FCH

E0H

D0H

C0H

Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH.

RP0 =

RP1 =

1 1 0 0 0 0 0 0

1 1 0 0 1 0 0 0

C0H

BFH

~

Page 0

Prime

Space

00H

NOTE:

In the S3F80N8 microcontrolle, only Page 0 is implemented.

Figure 2-9. Common Working Register Area

~

~

~

~

~

~

~

~

2-10


)

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.

Examples 1. LD 0C2H,40H ; Invalid addressing mode!

Use working register addressing instead:

R2,40H

2. ADD 0C3H,#45H ; Invalid addressing mode!

Use working register addressing instead:

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).

— The five high-order bits in the register pointer select an 8-byte slice of the register space.

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-10, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice.

Figure 2-11 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction

"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-11


Selects

RP0 or RP1

Address OPCODE

RP0

RP1

Register pointer provides five high-order bits

4-bit address provides three low-order bits

Together they create an

8-bit register address

Figure 2-10. 4-Bit Working Register Addressing

RP0

0 1 1 1 0 0 0 0

0 1 1 1 0 1 1 0

Register address

(76H)

Selects RP0

RP1

0 1 1 1 1 0 0 0

R6

0 1 1 0

OPCODE

1 1 1 0

Instruction

'INC R6'

Figure 2-11. 4-Bit Working Register Addressing Example

2-12


8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.

As shown in Figure 2-12, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction.

Figure 2-13 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low order bits of the register address (011) are provided by the three low order bits of 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH

(10101011B).

These address bits indicate 8-bit working register addressing

RP0

RP1

Selects

RP0 or RP1

1 1 0 0

Address

8-bit logical address

Three low-order bits Register pointer provides five high-order bits

8-bit physical address

Figure 2-12. 8-Bit Working Register Addressing

2-13


RP0

0 1 1 0 0 0 0 0

Selects RP1

R11

1 1 0 0 1 0 1 1

8-bit address form instruction

'LD R11, R2'

Specifies working register addressing

RP1

1 0 1 0 1 0 0 0

1 0 1 0 1 0 1 1

Register address

(0ABH)

Figure 2-13. 8-Bit Working Register Addressing Example

2-14


SYSTEM AND USER STACK

The S3F8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3F80N8 architecture supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-14.

High Address

Top of stack

PCL

PCH

PCL

PCH

Flags

Top of stack

Stack contents after a call instruction

Stack contents after an interrupt

Low Address

Figure 2-14. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3F80N8, the SP must be initialized to an 8-bit value in the range 00H–7FH.

2-15


)

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD ;

; (Normally, the SP is set to 07FH by the initialization

•

•

•

PUSH

PUSH

PUSH

PUSH

•

PP

RP0

RP1

R3

•

•

POP R3

; Stack address 0FEH

; Stack address 0FDH

; Stack address 0FCH

; Stack address 0FBH

← PP

← RP0

← RP1

← R3

POP PP

; R3

← Stack address 0FBH

;

RP0

; PP

← Stack address 0FEH

2-16

3

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.

The S3F-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are:

— Indirect Register (IR)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

3-1

ADDRESSING MODES S3F80N8_UM_REV1.10

REGISTER ADDRESSING MODE (R)

In Register addressing mode (R), the operand value is the content of a specified register or register pair

(see Figure 3-1).

Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Register File

Point to One

Register in Register

File

Value used in

Instruction Execution

OPERAND

Sample Instruction:

DEC CNTR ; Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File

MSB Point to

RP0 ot RP1

RP0 or RP1

Program Memory

4-bit

Working Register dst src

OPCODE

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD R1, R2

3 LSBs

Point to the

Working Register

(1 of 8)

OPERAND

; Where R1 and R2 are registers in the currently

selected working register area.

Selected

RP points to start of working register block

Figure 3-2. Working Register Addressing

3-2

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using the Indirect Register addressing mode.

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Point to One

Register in Register

File

Address of Operand used by Instruction

Register File

ADDRESS

OPERAND

Value used in

Instruction Execution

Sample Instruction:

RL @SHIFT ; Where SHIFT is the label of an 8-bit register address

Figure 3-3. Indirect Register Addressing to Register File

3-3


INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

S3F80N8_UM_REV1.10

Example

Instruction

References

Program

Memory

Program Memory dst

OPCODE

Points to

Register Pair

Sample Instructions:

CALL

JP

@RR2

@RR2

REGISTER

PAIR

Value used in

Instruction

Program Memory

OPERAND

16-Bit

Address

Points to

Program

Memory

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4-bit

Working

Register

Address

Program Memory dst src

OPCODE

~

3 LSBs

Point to the

Working Register

(1 of 8)

~

ADDRESS

~

~

Sample Instruction:

OR R3, @R6

Value used in

Instruction

OPERAND

Selected

RP points to start fo working register block

Figure 3-5. Indirect Working Register Addressing to Register File

3-5


INDIRECT REGISTER ADDRESSING MODE (Concluded)

S3F80N8_UM_REV1.10

MSB Points to

RP0 or RP1

Register File

RP0 or RP1

4-bit Working

Register Address

Example Instruction

References either

Program Memory or

Data Memory

Program Memory dst src

OPCODE

Next 2-bit Point

to Working

Register Pair

(1 of 4)

LSB Selects

Register

Pair

Program Memory or

Data Memory

Value used in

Instruction

OPERAND

Selected


16-Bit address points to program memory or data memory


LCD

LDE

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using Indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented.

Register File

RP0 or RP1

Two-Operand

Instruction

Example

Value used in

Instruction

~

OPERAND

~

Selected RP points to start of working register block

+

Program Memory

Base Address dst/src x

OPCODE

3 LSBs

Point to One of the

Woking Register

(1 of 8)

~

INDEX

~

Sample Instruction:

LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7


INDEXED ADDRESSING MODE (Continued)

S3F80N8_UM_REV1.10

4-bit Working

Register Address

Program Memory

OFFSET dst/src x

OPCODE

MSB Points to

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

(1 of 4)

LSB Selects

8-Bits

+

16-Bits

~

Register File

RP0 or RP1

~

Selected


Register

Pair

16-Bit address added to offset

Program Memory or

Data Memory

16-Bits

OPERAND

Value used in

Instruction


LDC R4, #04H[RR2]

LDE R4,#04H[RR2]

; The values in the program address (RR2 + 04H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

INDEXED ADDRESSING MODE (Concluded)

4-bit Working

Register Address

Program Memory

OFFSET

OFFSET dst/src src

OPCODE

Register File

MSB Points to

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

LSB Selects

8-Bits

+

16-Bits

~

RP0 or RP1

~

Selected


Register

Pair

Program Memory or

Data Memory

16-Bit address added to offset

16-Bits

OPERAND

Value used in

Instruction


LDC R4, #1000H[RR2]

LDE R4,#1000H[RR2]

; The values in the program address (RR2 + 1000H)




Figure 3-9. Indexed Addressing to Program or Data Memory

3-9


DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Program Memory

Memory

Address

Used

Upper Address Byte

Lower Address Byte dst/src "0" or "1"

OPCODE

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory


LDC R5,1234H

LDE R5,1234H

; The values in the program address (1234H)




Figure 3-10. Direct Addressing for Load Instructions

3-10

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory

Address

Used

Upper Address Byte

Lower Address Byte

OPCODE


JP C,JOB1

CALL DISPLAY

; Where JOB1 is a 16-bit immediate address

; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11


INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.

Program Memory

Current

Instruction dst

OPCODE

Next Instruction

LSB Must be Zero

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H ; The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current Instruction

Displacement

OPCODE

Current

PC Value

Signed

Displacement Value

+


JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13


IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

4

CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the S3F80N8 control registers are presented in an easy-to-read format.

You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual. Data and counter registers are not described in detail in this reference chapter. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual.

The locations and read/write characteristics of all mapped registers in the S3F80N8 register file are listed in Table

4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-Down."

Table 4-1. Registers

Register NAME

Timer 0 Counter Register

Timer 0 Data Register

Timer 0 Control Register

Basic Timer Control Register

Clock Control Register

Mnemonic R/W

T0CNT R

T0DATA R/W

T0CON R/W

BTCON R/W

CLKCON R/W

Address Reset Value(bit)

Decimal Hex 7 6 5 4 3 2 1 0

208 D0H 0 0 0 0 0 0 0 0

209

210

D1H

D2H

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

211

212

D3H 0 0 0 0 0 0 0 0

D4H 0 – – 0 0 – – –

System Flags Register

Register Pointer 0

Register Pointer 1

FLAGS R/W

RP0 R/W

213

214

D5H x x x x x x 0 0

D6H 1 1 0 0 0 – – –

RP1 R/W 215 D7H 1 1 0 0 1 – – –

Location D8H is not mapped.

Stack Pointer Register (Low Byte) SPL R/W

Instruction Pointer (High Byte) IPH R/W

Instruction Pointer (Low Byte) IPL R/W

217

218

219

D9H x

DAH

DBH x x x x x x x x x x x x x x x x x x x x x x x

Interrupt Request Register

Interrupt Mask Register

IRQ

IMR

R

R/W

220

221

DCH 0 0 0 0 0 0 0 0

DDH 0 0 0 0 0 0 0 0

NOTE: - : Not mapped or not used, x: Undefined

4-1

CONTROL REGISTERS S3F80N8_UM_REV1.10

Table 4-1. Registers (continued)

Register NAME

System Mode Register

Register Page Pointer

Port 0 data register




Mnemonic R/W

SYM

PP

R/W

R/W

P0

P1

P2

P3

R/W

R/W

R/W

R/W

Address Reset Value (bit)

Decimal Hex 7 6 5 4 3 2 1 0

222

223

DEH

DFH

0

0

–

0

–

0 x

0 x

0 x

0

0

0

0

0

224

225

226

227

E0H

E1H

E2H

E3H

0

0

–

–

0

0

–

–

0

0

–

0

0

–

0

0

0

0

0 0 0 0

0 0

0

0

0

0

0

0

0

0

Port 0 control register (High byte) P0CONH R/W

Port 0 control register (Low byte) P0CONL R/W

Port 0 pull-up resistor enable register

P0PUR R/W

228

229

E4H

E5H

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

230 E6H 0 0 0 0 0 0 0

Locations E7H is not mapped.

Port 1 control register (High byte) P1CONH R/W 232 E8H 0 0 0 0 0 0 0 0



P1PUR R/W

External interrupt enable register EXTINT R/W

233

234

235

E9H

EBH

0

EAH 0

0

0

0

0

0

0

0

0

0

0

0

0 0 0 0

0

0

0

0

0

0

0

External interrupt pending register EXTPND R/W 236 ECH 0 0 0 0 0 0 0 0

Location EDH is not mapped.




P2PUR R/W

238

239

240

EEH

EFH

F0H

–

0

–

0

–

–

0

–

0

1

0

0

0

0 0 0 0

0

0

0

0

0

0

Locations F1H is not mapped.

Port 3 control register


P3CON R/W

P3PUR R/W

242 F2H 0 0 0 0 0 0 0 0

243 F3H – – – 1 1 1 1

STOP control register

Basic timer counter register

Interrupt priority register

Locations F4H-FAH are not mapped.

STOPCON R/W 251 FBH 0 0 0 0 0 0 0 0

Location FCH is not mapped.

BTCNT R 253 FDH 0 0 0 0 0 0 0 0

Location FEH is not mapped.

IPR R/W 255 FFH x x x x x x x x

NOTES:

1. The reset value of P2.5 setting is open-drain output.

2. The reset value of P3PUR is 0FH, this value enables the pull up resistor.

4-2

Bit number(s) that is/are appended to the register name for bit addressing

Register ID Register name

Name of individual bit or related bits

Register address

(hexadecimal)

FLAGS - System Flags Register

Bit Identifier

RESET Value

Read/Write

Bit Addressing

Mode

.7

.6

.5

.7

.6

.5

.4

x

R/W x

R/W x

R/W

Register addressing mode only x

R/W

.3

x

R/W

.2

x

R/W

Carry Flag (C)

0 Operation does not generate a carry or borrow condition

1

Operation generates carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

D5H

.1

x

R/W

.0

0

R/W

R = Read-only

W = Write-only

R/W = Read/write

'-' = Not used

Type of addressing that must be used to address the bit

(1-bit, 4-bit, or 8-bit)

Description of the effect of specific bit settings

Figure 4-1. Register Description Format

Bit number:

MSB = Bit 7

LSB = Bit 0

RESET value notation:

'-' = Not used

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

4-3


BTCON

— Basic Timer Control Register D3H

.1

.0

Reset Value

Read/Write

Addressing Mode

.7–.4

.3–.2

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

Watchdog Timer Function Disable Code (for System Reset)

1 0 1

Others

0 Disable watchdog timer function

Enable watchdog timer function

Basic Timer Input Clock Selection Bits

f

OSC f f

OSC

OSC

/4096

/1024

/128

Basic Timer Counter Clear Bit

1

(1)

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for all Timers

(2)

1 Clear both clock frequency dividers

NOTES:

1. When BTCON.1 is set to “1” , the basic timer counter value is cleared to “00H”. Immediately following the write operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a “1” to BTCON.0, the corresponding frequency divider is cleared to “00H”. Immediately following the write operation, the BTCON.0 value is automatically cleared to “0”.

4-4

CLKCON

— System Clock Control Register D4H

Reset Value

Read/Write

Addressing Mode

.7–.5

.4–.3

.2–.0

.7 .6 .5 .4 .3 .2 .1 .0

– – – 0 0 – – –


Not used for the S3F80N8.

CPU Clock (System Clock) Selection Bits

0 0 f

0 1 f

1 0 f

1 1 f

OSC

OSC

OSC

OSC

/16

/8

/2

/1


(note)

NOTE: After a reset, the clock (not divided) is selected as the system clock. To select other clock speeds, load

4-5


.3

.2

.4

.6

.5

.1

.0

EXTINT

— External Interrupt Enable Register

Reset Value

Read/Write

Addressing Mode

.7

EBH

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



P1.7/INT7, External Interrupt Enable Bit

0 INT7 interrupt disable

1 INT7 interrupt enable






















4-6

EXTPND

— External Interrupt Pending Register

.4

.5

.6

Reset Value

Read/Write

Addressing Mode

.7

Port 1.7/INT7, External Interrupt Pending Bit

0 No interrupt pending (when read)

0 Pending bit clear (when write)

1 Interrupt is pending (when read)

1 No effect (when write)
















ECH

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-7


.1

.0

.3

.2

.4

.5

.7

.6

FLAGS

— System Flags Register D5H

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x 0 0

Reset Value

Read/Write

Addressing Mode


Carry Flag (C)

0 Operation does not generate a carry or borrow condition

1 Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

0 Operation result is a non-zero value

1 Operation result is zero

Sign Flag (S)

0 Operation generates a positive number (MSB = "0")

1 Operation generates a negative number (MSB = "1")

Overflow Flag (V)

0 Operation result is

≤ +127 or ≥ –128

1 Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0 Add operation completed

1 Subtraction operation completed

Half-Carry Flag (H)

0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)

1 Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0 Bank 0 is selected

1 Bank 1 is selected

4-8

IMR

— Interrupt Mask Register DDH

.5

.2

.4

.3

.7

.6

Reset Value

Read/Write

Addressing Mode

.1

.0

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Interrupt Level 7 (IRQ7)

0

Disable (mask)

1

Enable (unmask)


0 Disable (mask)

1 Enable (unmask)


0 Disable (mask)

1 Enable (unmask)


0 Disable (mask)

1 Enable (unmask)


0 Disable (mask)

1 Enable (unmask)


0 Disable (mask)

1 Enable (unmask)


0 Disable (mask)

1 Enable (unmask)


0 Disable (mask)

1 Enable (unmask)

NOTE: When an interrupt level is masked, the CPU does not recognize any interrupt requests that may be issued.

4-9


IPH

— Instruction Pointer (High Byte)

Reset Value

Read/Write

Addressing Mode

.7–.0

DAH

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).

IPL

— Instruction Pointer (Low Byte)

Reset Value

Read/Write

Addressing Mode

.7–.0

DBH

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH register (DAH).

4-10

IPR

— Interrupt Priority Register FFH

.2

.3

.6

.5

.0

Reset Value

Read/Write

Addressing Mode

.7, .4, and .1

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x x



Priority Control Bits for Interrupt Groups A, B, and C

0

0

0

0

0

1

0

1

0

NOTE: Interrupt Group A - IRQ0, IRQ1

Interrupt Group B - IRQ2, IRQ3, IRQ4

Interrupt Group C - IRQ5, IRQ6, IRQ7

Group priority undefined

B > C > A

A > B > C

0 1 1 B > A > C

1 0 0 C > A > B

1 0 1 C > B > A

1 1 0 A > C > B

1 1 1 Group priority undefined

Interrupt Subgroup C Priority Control Bit

0 IRQ6 > IRQ7

1 IRQ7 > IRQ6

Interrupt Group C Priority Control Bit

0 IRQ5 > (IRQ6, IRQ7)

1 (IRQ6, IRQ7) > IRQ5

Interrupt Subgroup B Priority Control Bit

0 IRQ3 > IRQ4

1 IRQ4 > IRQ3

Interrupt Group B Priority Control Bit

0 IRQ2 > (IRQ3, IRQ4)

1 (IRQ3, IRQ4) > IRQ2

Interrupt Group A Priority Control Bit

0 IRQ0 > IRQ1

1 IRQ1 > IRQ0

(note)

4-11


IRQ

— Interrupt Request Register

.2

.1

.0

.5

.6

.4

.3

Reset Value

Read/Write

Addressing Mode

.7

1 Pending

Level 6 (IRQ6) Request Pending Bit;

1 Pending


1 Pending


1 Pending


1 Pending


1 Pending


1 Pending


1 Pending

DCH

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0

R R R R R R R R



4-12

P0CONH

— Port 0 Control Register (High Byte)

.3–.2

.1–.0

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6

P0.7 Configuration Bits

0 0 Normal

0 1 Output mode, push-pull

1 0 Output mode, open-drain

1 1 Not


0 0 Normal



1 1 Not


0 0 Normal



1 1 Not


0 0 Normal



1 1 Not

E4H

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-13


P0CONL

— Port 0 Control Register (Low Byte)

.3–.2

.1–.0

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6













E5H

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-14

P0PUR

— Port 0 Pull-up Control Register

.0

.2

.1

.5

.6

.4

.3

Reset Value

Read/Write

Addressing Mode

.7

P0.6 Pull-up Resistor Enable Bit

0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable

E6H

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0




0 Pull-up disable

1 Pull-up enable

4-15


P1CONH

— Port 1 Control Register (High Byte)

.3–.2

.1–.0

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6


0 0 CMOS input;INT7 external falling edge interrupt input

0 1 CMOS input; INT7 external both falling edge and rising edge interrupt input




0 0 CMOS input; INT6 external falling edge interrupt input














E8H

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-16

P1CONL


.1–.0

.3–.2

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6



0 1 CMOS input;INT3 external both falling edge and rising edge interrupt input


















E9H

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-17


P1PUR


.0

.2

.1

.5

.6

.4

.3

Reset Value

Read/Write

Addressing Mode

.7








EAH

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0




4-18

P2CONH

— Port 2 Control Register (High Byte) EEH

.1–.0

Reset Value

Read/Write

Addressing Mode

.7–.6

.3–.2

.7 .6 .5 .4 .3 .2 .1 .0

– – – – 1 0 0 0




0 0 Normal



1 1 Not


0 0 Normal input (or T0 capture input)



1 1 Alternative function: T0 PWM output

NOTE: The reset setting of P2.5 is open drain output.

4-19


P2CONL


.3–.2

.1–.0

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6


0 0 Normal input (or T0 clock input)






1 1 Alternative function : CLO







EFH

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-20

P2PUR


.1

.0

.2

.4

Reset Value

Read/Write

Addressing Mode

.7–.6

.5

.3



0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable


0 Pull-up disable

1 Pull-up enable

F0H

.7 .6 .5 .4 .3 .2 .1 .0

– – 0 0 0 0 0 0

– – R/W R/W R/W R/W R/W R/W


4-21


P3CON

— Port 3 Control Register

.3–.2

.1–.0

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6













F2H

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



4-22

P3PUR

— Port 3 Pull-up Control Register F3H

.7 .6 .5 .4 .3 .2 .1 .0

Reset Value

Read/Write

Addressing Mode

.7–.4

– – – – 1 1 1 1



.3 P3.3 Pull-up Resistor Enable Bit

0

Pull-up disable

1

Pull-up enable


0

Pull-up disable

1

Pull-up enable


0

Pull-up disable

1

Pull-up enable


0

Pull-up disable

1

Pull-up enable

NOTE: The reset value of P3PUR is 0FH, this value enables the pull-up resistor.

4-23


PP

— Register Page Pointer DFH

Reset Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0




NOTE: In S3F80N8, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to ‘00H’ following a hardware reset. These values should not be changed during normal operation.

4-24

RP0

— Register Pointer 0

Reset Value

Read/Write

Addressing Mode

.7–.3

D6H

.7 .6 .5 .4 .3 .2 .1 .0

1 1 0 0 0 – – –

R/W R/W R/W R/W R/W – – –

Register addressing only

Register Pointer 0 Address Value

Register pointer 0 can independently point to one of the 144-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to address C0H, selecting the 8-byte working register slice C0H–C7H.

.2–.0

Not used for the S3F80N8

RP1

— Register Pointer 1

Reset Value

Read/Write

Addressing Mode

.7 – .3

D7H

.7 .6 .5 .4 .3 .2 .1 .0

1 1 0 0 1 – – –

R/W R/W R/W R/W R/W – – –

Register addressing only

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 144-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to address C8H, selecting the 8-byte working register slice C8H–CFH.

.2 – .0


4-25


SPL

— Stack Pointer (Low Byte)

Reset Value

Read/Write

Addressing Mode

.7–.0 Stack Pointer Address (Low Byte)

The SP value is undefined following a reset.

D9H

.7 .6 .5 .4 .3 .2 .1 .0

x x x x x x x X



4-26

STOPCON

— Stop Control Register FBH

Reset Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



STOP Control Bits

1 0 1 0 0 1 0 1

Other values

Enable stop instruction

Disable stop instruction

NOTES:

1. Before execute the STOP instruction, set this STPCON register as “10100101b”.

2. When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address.

4-27


SYM

— System Mode Register DEH

.0

Reset Value

Read/Write

Addressing Mode

.7

.6–.5

.4–.2

.1

0

1

.7 .6 .5 .4 .3 .2 .1 .0

0 – – x x x 0 0


Tri-state External Interface Control Bit

Fast Interrupt Enable Bit

0

1

(3)

Disable fast interrupt processing

Enable fast interrupt processing

(1)

Normal operation (disable tri-state operation)

Set external interface lines to high impedance (enable tri-state operation)


Fast Interrupt Level Selection Bits

Global Interrupt Enable Bit

(4 )

0

1

Disable all interrupt processing

Enable all interrupt processing

(2)

NOTES:

1. Because an external interface is not implemented, SYM.7 must always be ‘0’.

2. You can select only one interrupt level at a time for fast interrupt processing.

3. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2-SYM.4.

4. Following a reset, you must enable global interrupt processing by executing an EI instruction

(not by writing a "1" to SYM.0).

4-28

T0CON

— Timer 0 Control Register D2H

.0

.2

.1

.3

.5–.4

Reset Value

Read/Write

Addressing Mode

.7–.6

1

0

1

.7 .6 .5 .4 .3 .2 .1 .0

0 0 0 0 0 0 0 0



Timer 0 Input Clock Selection Bits

0 0 f

OSC

/4096

0 1 f

OSC

/256

1 0 f

OSC

1

/8

External clock (P2.3/T0CK)

Timer 0 Operating Mode Selection Bits

0 0 Interval

0 1 Capture mode (capture on rising edge, counter running, OVF can occur)

1 0 Capture mode (capture on falling edge, counter running, OVF can occur)

1 1 PWM mode (OVF interrupt can occur)

Timer 0 Counter Clear Bit

0

1

No effect

Timer 0 Match Interrupt Enable Bit

Disable Match interrupt

Enable Match interrupt

Timer 0 Match Interrupt Pending Bit

0

0

1

1

No interrupt pending (When read)

Clear pending bit (when write)

Interrupt is pending (When read)

No effect (When write)

(note)

Clear the timer 0 counter (when write)

Timer 0 Overflow Interrupt Enable bit

0

1

Disable Overflow interrupt

Enable Overflow interrupt

NOTE: When T0CON.3 is set to "1", the timer 0 counter value is cleared to "00H". Immediately following the write operation, the T0CON.3 value is automatically cleared to "0".

4-29

CONTROL REGISTERS

NOTES

S3F80N8_UM_REV1.10

4-30

5

INTERRUPT STRUCTURE

OVERVIEW

The S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3F80N8 interrupt structure recognizes three interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for

S3F8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3F80N8 uses 10 vectors.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.

Each vector can have several interrupt sources. In the S3F80N8 interrupt structure, there are ten possible interrupt sources.

When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE S3F80N8_UM_REV1.10

INTERRUPT TYPES

The three components of the S3F8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.

The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1: One level (IRQn) + one vector (V

1

) + one source (S

1

)

Type 2: One level (IRQn) + one vector (V

1

) + multiple sources (S

1

– S n

)

Type 3: One level (IRQn) + multiple vectors (V

1

– V n

) + multiple sources (S

1

– S n

, S n+1

– S n+m

)

In the S3F80N8 microcontroller, two interrupt types are implemented.

T y p e 1 :

T y p e 2 :

L e v e ls

IR Q n

IR Q n

V e c t o r s

V

1

V

1

T y p e 3 :

IR Q n

V

1

V

2

V

3

V n

N O T E S :

1 . T h e n u m b e r o f S n

a n d V n

v a lu e is e x p a n d a b le .

2 . In th e S F 8 0 N 8 im p le m e n ta tio n ,

in te r r u p t ty p e s 1 a n d 3 a r e u s e d .

Figure 5-1. S3F8-Series Interrupt Types

S o u r c e s

S

1

S

1

S

2

S

3

S n

S

1

S

2

S

3

S n

S n +

1

S n +

2

S n + m

5-2

S3F80N8 INTERRUPT STRUCTURE

The S3F80N8 microcontroller supports ten interrupt sources. Every interrupt source has a corresponding interrupt address. As shown in Figure 5-2, level of three interrupt are recognized by the CPU in this device-specific interrupt structure.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware).

When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.

Levels Vectors Sources Reset/Clear

RESET 100H Basic timer overflow H/W

IRQ0

IRQ1

IRQ2

F4H

F2H

F0H

EEH

ECH

EAH

FCH

FAH

F8H

F6H

External interrupt 7








Timer 0 match/capture interrupt

Timer 0 overflow interrupt

NOTE:

External interrupts are triggered by falling edge or both rising edge and falling edge.

S/W

S/W

S/W

S/W

S/W

H/W

S/W

S/W

S/W

S/W

Figure 5-2. S3F80N8 Interrupt Structure

5-3


Interrupt Vector Addresses

All interrupt vector addresses for the S3F80N8 interrupt structure is stored in the vector address area of the first

256 bytes of the program memory (ROM).

You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses.

The program reset address in the ROM is 0100H.

(D e c im a l)

8 1 9 1

(H E X )

1 F F F H

8 K -b y te

P r o g ra m M e m o ry

A re a

2 5 5

0

In te rru p t V e c to r

A d d re s s A re a

1 0 0 H

F F H

R e s e t

A d d re s s

0 0 H

Figure 5-3. ROM Vector Address Area

5-4

Enable/Disable Interrupt Instructions (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities.

NOTE

The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure.

During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented).

Control Register

Interrupt mask register


Interrupt request register

System mode register

Table 5-1. Interrupt Control Register Overview

ID

IMR

IPR

IRQ

SYM

R/W Function Description

R/W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0–IRQ7.

R/W Controls the relative processing priorities of the interrupt levels.

The eight levels of S3F80N8 are organized into three groups:

A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2,

IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

R This register contains a request pending bit for each interrupt level.

R/W This register enables/disables fast interrupt processing, and dynamic global interrupt processing.

NOTE: All interrupts must be disabled before IMR register is changed to any value. Using DI instruction is recommended.

5-5


INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are:

— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information.

EI nRESET

IRQ0-IRQ7,

Interrupts

S

R

Q

Interrupt Priority

Register


(Read-only)

Polling

Cycle

Interrupt Mask

Register

Global Interrupt Control

(EI, DI or SYM.0

manipulation)

Vector

Interrupt

Cycle

Figure 5-4. Interrupt Function Diagram

5-6

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-2).

Interrupt Source

P1.7 external interrupt








Timer 0 match/capture

Timer 0 overflow

Table 5-2. Interrupt Source Control and Data Registers

Interrupt Level Register(s) Location(s)

IRQ0 EXTINT EBH

EXTPND

P1CONH

ECH

E8H

IRQ1 EXTINT

EXTPND

P1CONL

IRQ2 T0CON

T0CNT

T0DATA

EBH

ECH

E9H

D2H

D0H

D1H

5-7


SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5).

A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose.

M S B .7

.6

S y s te m M o d e R e g is te r (S Y M )

D E H , R /W

.5

.4

.3

.2

.1

.0

L S B

A lw a y s lo g ic "0 ".

N o t u s e d fo r th e

S 3 F 8 0 N 8 .

F a s t in te rru p t le v e l s e le c tio n b its :

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

IR Q 0

IR Q 1

IR Q 2

IR Q 3

IR Q 4

IR Q 5

IR Q 6

IR Q 7

G lo b a l in te rru p t e n a b le b it:

0 = D is a b le a ll in te rru p ts p ro c e s s in g

1 = E n a b le a ll in te rru p ts p ro c e s s in g

F a s t in te rru p t e n a b le b it:

0 = D is a b le fa s t in te rru p ts p ro c e s s in g

1 = E n a b le fa s t in te rru p ts p ro c e s s in g

Figure 5-5. System Mode Register (SYM)

5-8

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's

IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH. Bit values can be read and written by instructions using the

Register addressing mode.

MSB .7

.6

Interrupt Mask Register (IMR)

DDH, R/W

.5

.4

.3

.2

.1

.0

LSB

IRQ7

IRQ0

IRQ3

IRQ2

IRQ1

IRQ6

IRQ5

IRQ4

Interrupt level enable bit:

0 = Disable (mask) interrupt level

1 = Enable (un-mask) interrupt level

NOTE:

Before IMR register is changed to any value, all interrupts must be disable.

Using DI instruction is recommended.

Figure 5-6. Interrupt Mask Register (IMR)

5-9


INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7):

Group A IRQ0, IRQ1

Group B IRQ2, IRQ3, IRQ4

Group C IRQ5, IRQ6, IRQ7

IPR

Group A

IPR

Group B

IPR

Group C

A1 A2 B1 B2 C1 C2

B21 B22 C21 C22

IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.

For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of group C interrupts.

— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,

6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-10

MSB .7

Group priority:

D7 D4 D1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

= Undefined

= B > C > A

= A > B > C

= B > A > C

= C > A > B

= C > B > A

= A > C > B

= Undefined

.6

Interrupt Priority Register (IPR)

FEH, R/W

.5

.4

.3

.2

.1

.0

LSB

Group A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

Group B

0 = IRQ2 > (IRQ3, IRQ4)

1 = (IRQ3, IRQ4) > IRQ2

Subgroup B

0 = IRQ3 > IRQ4

1 = IRQ4 > IRQ3

Group C

0 = IRQ5 > (IRQ6, IRQ7)

1 = (IRQ6, IRQ7) > IRQ5

Subgroup C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

Figure 5-8. Interrupt Priority Register (IPR)

5-11


INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to

IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A

"1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the

IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled.

MSB .7

.6

Interrupt Request Register (IRQ)

DCH, Read-only

.5

.4

.3

.2

.1

.0

LSB

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

Interrupt level request pending bits:

0 = Interrupt level is not pending

1 = Interrupt level is pending

Figure 5-9. Interrupt Request Register (IRQ)

5-12

INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software.

In the S3F80N8 interrupt structure, the timer 0 overflow interrupt (IRQ2) belongs to this category of interrupts in which pending condition is cleared automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source’s mode or control register.

5-13


INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the source's interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request is serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one level is currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.

The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.

5-14

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs).

4. When the lower-priority interrupt service routine ends, execute DI, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the procedure above to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is adopted by all the S3F8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt processing for the selected level, you set SYM.1 to “1”.

5-15


FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and

— When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated register called FLAGS' ("FLAGS prime").

NOTE

For the S3F80N8 microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing.

PROCEDURE FOR INITIATING FAST INTERRUPTS

To initiate fast interrupt processing, follow these steps:

1. Load the start address of the service routine into the instruction pointer (IP).

2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)

3. Write a "1" to the fast interrupt enable bit in the SYM register.

FAST INTERRUPT SERVICE ROUTINE

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

1. The contents of the instruction pointer and the PC are swapped.

2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.

3. The fast interrupt status bit in the FLAGS register is set.

4. The interrupt is serviced.

5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back.

6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.

7. The fast interrupt status bit in FLAGS is cleared automatically.

RELATIONSHIP TO INTERRUPT PENDING BIT TYPES

As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the application program's interrupt service routine. You can select fast interrupt processing for interrupts with either type of pending condition clear function — by hardware or by software.

PROGRAMMING GUIDELINES

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the

SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends.

5-16

S3F80N8_UM_REV1.10 INSTRUCTION

6

INSTRUCTION SET

OVERVIEW

The SAM8RC instruction set is specifically designed to support the large register files that are typical of most

SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include:

— A full complement of 8-bit arithmetic and logic operations, including multiply and divide

— No special I/O instructions (I/O control/data registers are mapped directly into the register file)

— Decimal adjustment included in binary-coded decimal (BCD) operations

— 16-bit (word) data can be incremented and decremented

— Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES

The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Chapter 2, "Address Spaces."


There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative

(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to

Chapter 3, "Addressing Modes."

6-1

INSTRUCTION SET S3F80N8_UM_REV1.10

Table 6-1. Instruction Group Summary

Mnemonic Operands Instruction

Load Instructions

CLR dst Clear

LDE

LDC

LDED

LDCD

LDEI

LDCI

LDEPD

LDCPD

LDEPI

LDCPI

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst dst,src dst,src src dst,src dst,src

Load external data memory

Load program memory

Load external data memory and decrement

Load program memory and decrement

Load external data memory and increment

Load program memory and increment

Load external data memory with pre-decrement

Load program memory with pre-decrement

Load external data memory with pre-increment

Load program memory with pre-increment

Pop from stack

Pop user stack (decrementing)

Pop user stack (incrementing)

Push to stack

Push user stack (decrementing)

Push user stack (incrementing)

6-2


Table 6-1. Instruction Group Summary (Continued)


Arithmetic Instructions

ADC dst,src Add with carry

DEC dst Decrement

DECW dst Decrement

INC dst Increment

INCW dst Increment

MULT dst,src Multiply

SBC dst,src Subtract with carry

Logic Instructions

COM dst Complement

XOR dst,src Logical exclusive OR

6-3


Table 6-1. Instruction Group Summary (Continued)


Program Control Instructions

BTJRF

BTJRT dst,src dst,src

Bit test and jump relative on false

Bit test and jump relative on true

CALL dst Call

CPIJE dst,src Compare, increment and jump on equal

CPIJNE

DJNZ dst,src r,dst

ENTER

EXIT

IRET

JP cc,dst

Compare, increment and jump on non-equal

Decrement register and jump on non-zero

Enter

Exit

Jump on condition code

JR cc,dst

NEXT

RET

WFI

Bit Manipulation Instructions

Jump relative on condition code

Next

Return

Wait for interrupt

BITC dst Bit

BITR dst Bit

TCM

TM dst,src dst,src

Test complement under mask

Test under mask

6-4


Table 6-1. Instruction Group Summary (Concluded)


Rotate and Shift Instructions

RLC dst Rotate left through carry

RRC

SRA dst dst

Rotate right through carry

Shift right arithmetic

SWAP dst Swap

CPU Control Instructions

CCF Complement carry flag

DI Disable

EI Enable

IDLE

NOP

Enter Idle mode

RCF

SB0

SB1

SCF

SRP

SRP0

SRP1

STOP src src src

Reset carry flag

Set bank 0

Set bank 1

Set carry flag

Set register pointers

Set register pointer 0

Set register pointer 1

Enter Stop mode

6-5


FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and

FLAGS.2 are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.

MSB

Carry flag (C)

.7

Zero flag (Z)

.6

System Flags Register (FLAGS)

D5H, R/W

.5

.4

.3

.2

.1

.0

LSB

Bank address status flag (BA)

Fast interrupt status flag (FIS)

Sign flag (S)

Half-carry flag (H)

Overflow flag (V)

Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

6-6


FLAG DESCRIPTIONS

C

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.

Z

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

S

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number.

V

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than

– 128. It is also cleared to "0" following logic operations.

D

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition.

H

Half-Carry Flag (FLAGS.2)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program.

FIS

Fast Interrupt Status Flag (FLAGS.1)

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.

When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed.

BA

Bank Address Flag (FLAGS.0)

The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.

6-7


INSTRUCTION SET NOTATION

Table 6-2. Flag Notation Conventions

Flag Description

0

1

*

– x

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

Table 6-3. Instruction Set Symbols

Symbol Description

@ Indirect register address prefix

FLAGS Flags register (D5H)

#

H

D

B

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix opc Opcode

6-8


Table 6-4. Instruction Notation Conventions

Notation

cc r rb r0 rr

R

Rb

RR

IA

Ir

IR

Irr

IRR

X

XS xl da ra im iml

Description Actual Operand Range

Condition code

Working register only

Bit (b) of working register

Bit 0 (LSB) of working register

Working register pair

Register or working register

Bit 'b' of register or working register

Register pair or working register pair

See list of condition codes in Table 6-6.

Rn (n = 0–15)

Rn.b (n = 0–15, b = 0–7)

Rn (n = 0–15)

RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0–255, n = 0–15) reg.b (reg = 0–255, b = 0–7) reg or RRp (reg = 0–254, even number only, where p = 0, 2, ..., 14)

Indirect addressing mode

Indirect working register only

Indexed addressing mode

Indexed (short offset) addressing mode addr (addr = 0–254, even number only)

@Rn (n = 0–15)

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Indirect working register pair only @RRp (p = 0, 2, ..., 14)

Indirect register pair or indirect working register pair

@RRp or @reg (reg = 0–254, even only, where p = 0, 2, ..., 14)

#reg [Rn] (reg = 0–255, n = 0–15)

Indexed (long offset) addressing mode

Direct addressing mode

Relative addressing mode

#addr [RRp] (addr = range –128 to +127, where p = 0, 2, ..., 14)

#addr [RRp] (addr = range 0–65535, where p = 0, 2, ..., 14) addr (addr = range 0–65535)

Immediate addressing mode

Immediate (long) addressing mode addr (addr = number in the range +127 to –128 that is an offset relative to the address of the next instruction)

#data (data = 0–255)

#data (data = range 0–65535)

6-9


H

E

X

L

E

B

B

N

E

R

I

U

P

P

Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

– 0 1 2 3 4 5 6 7

0

DEC

R1

DEC

IR1

ADD r1,r2

ADD r1,Ir2

ADD

R2,R1

ADD

IR2,R1

ADD

R1,IM

BOR r0–Rb

1

2

RLC

R1

INC

R1

RLC

IR1

INC

IR1

ADC r1,r2

SUB r1,r2

ADC r1,Ir2

SUB r1,Ir2

ADC

R2,R1

SUB

R2,R1

ADC

IR2,R1

SUB

IR2,R1

ADC

R1,IM

SUB

R1,IM

BCP r1.b, R2

BXOR r0–Rb

3

4

5

6

7

8

9

A

B

C

D

E

F

DECW

RR1

RL

R1

INCW

RR1

CLR

R1

RRC

R1

JP

IRR1

DA

R1

POP

R1

COM

R1

PUSH

R2

SRA

R1

RR

R1

SWAP

R1

SRP/0/1

IM

DA

IR1

POP

IR1

COM

IR1

PUSH

IR2

DECW

IR1

RL

IR1

INCW

IR1

CLR

IR1

RRC

IR1

SRA

IR1

RR

IR1

SWAP

IR1

SBC r1,r2

OR r1,r2

AND r1,r2

TCM r1,r2

TM r1,r2

PUSHUD

IR1,R2

POPUD

IR2,R1

CP r1,r2

XOR r1,r2

CPIJE

Ir,r2,RA

CPIJNE

Irr,r2,RA

LDCD r1,Irr2

LDCPD r2,Irr1

SBC r1,Ir2

OR r1,Ir2

AND r1,Ir2

TCM r1,Ir2

TM r1,Ir2

PUSHUI

IR1,R2

POPUI

IR2,R1

CP r1,Ir2

XOR r1,Ir2

LDC r1,Irr2

LDC r2,Irr1

LDCI r1,Irr2

LDCPI r2,Irr1

SBC

R2,R1

OR

R2,R1

AND

R2,R1

TCM

R2,R1

TM

R2,R1

MULT

R2,RR1

DIV

R2,RR1

CP

R2,R1

XOR

R2,R1

LDW

RR2,RR1

CALL

IA1

LD

R2,R1

CALL

IRR1

SBC

IR2,R1

OR

IR2,R1

AND

IR2,R1

TCM

IR2,R1

TM

IR2,R1

MULT

IR2,RR1

DIV

IR2,RR1

CP

IR2,R1

XOR

IR2,R1

LDW

IR2,RR1

LD

R2,IR1

LD

IR2,R1

SBC

R1,IM

OR

R1,IM

AND

R1,IM

TCM

R1,IM

TM

R1,IM

MULT

IM,RR1

DIV

IM,RR1

CP

R1,IM

XOR

R1,IM

LDW

RR1,IML

IR1,IM

LD

R1,IM

CALL

DA1

Ir1, r2

LDC r1, Irr2, xs

LDC r2, Irr1, xs

LD r1, x, r2

LD r2, x, r1

LDC r1, Irr2, xL

LDC r2, Irr2, xL

LD r1, Ir2

BTJR r2.b, RA

LDB r0–Rb

BITC r1.b

BAND r0–Rb

BIT r1.b

6-10


B

B

L

N

I

P

E

R

U

P

E

H

E

X

Table 6-5. Opcode Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

– 8 9 A B C D E F

NEXT 0 LD LD r1,R2 r2,R1

1

↓ ↓

DJNZ r1,RA

↓

JR cc,RA

↓

LD r1,IM

↓

JP cc,DA

↓

INC r1

↓

ENTER

2

3

4

5

6

7

8

9

A

B

C

D

E

↓

↓

↓

↓

F LD LD r1,R2 r2,R1

↓

↓

DJNZ r1,RA

↓

↓

JR cc,RA

↓

↓

LD r1,IM

↓

↓

JP cc,DA

↓

↓

INC r1

IRET

RCF

SCF

DI

EI

RET

CCF

NOP

EXIT

WFI

SB0

SB1

IDLE

STOP

6-11


CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions.

Table 6-6. Condition Codes

Binary Mnemonic Description

0000 F Always

1000 T Always

0111

(note)

C Carry

1111

(note)

NC No carry

0110

(note)

1110

(note)

Z

NZ

Zero

Not zero

1101

0101

0100

1100

0110

(note)

1110

(note)

PL

MI

OV

NOV

EQ

NE

Plus

Minus

Overflow

No overflow

Equal

Not equal

1001

0001

1010

0010

1111

(note)

0111

(note)

1011

0011

GE

LT

GT

LE

UGE

ULT

UGT

ULE

Greater than or equal

Less than

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

–

–

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

NOTES:

1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used.

2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-12


INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Specific flag settings affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

6-13


ADC

— Add with carry

ADC

dst,src

Operation:

dst

← dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.

Flags:

Format:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result

is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

Bytes Addr Mode

(Hex) dst src

opc dst | src 2 4 12 r r

6 13 lr

6 15 IR

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH:

ADC R1,R2

→

ADC R1,@R2

→

ADC 01H,02H

→

ADC 01H,@02H

→

ADC 01H,#11H

→

R1 = 14H, R2 = 03H

R1 = 1BH, R2 = 03H

Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H

Register 01H = 32H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1, R2" adds

03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

6-14


ADD

— Add

ADD

dst,src

Operation:

dst

← dst + src

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.



V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result

is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if a carry from the low-order nibble occurred.

Format:

Bytes Addr Mode

(Hex) dst src


6 03 lr

6 05 IR

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD R1,R2

→

ADD R1,@R2

→

ADD 01H,02H

→

ADD 01H,@02H

→

ADD 01H,#25H

→

R1 = 15H, R2 = 03H

R1 = 1CH, R2 = 03H


Register 01H = 2BH, register 02H = 03H

Register 01H = 46H

In the first example, destination working register R1 contains 12H and the source working register

R2 contains 03H. The statement "ADD R1, R2" adds 03H to 12H, leaving the value 15H in register R1.

6-15


AND

— Logical AND

AND

dst,src

Operation:

dst

← dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.

Flags:

C: Unaffected.


S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src


6 53 lr

6 55 IR

Examples:


AND R1,R2

→

AND R1,@R2

→

AND 01H,02H

→

AND 01H,@02H

→

AND 01H,#25H

→

R1 = 02H, R2 = 03H

R1 = 02H, R2 = 03H



Register 01H = 21H

In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1, R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

6-16


BAND

— Bit AND

BAND

dst,src.b

BAND

dst.b,src or

Flags:

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

src 3 6 67 r0 dst 3 6 67 r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

BAND

→

BAND 01H.1,R1

→

R1 = 06H, register 01H = 05H

Register 01H = 05H, R1 = 07H

In the first example, source register 01H contains the value 05H (00000101B) and destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value

06H (00000110B) in register R1.

6-17


BCP

— Bit Compare

BCP

dst,src.b

Operation:

dst(0) – src(b)

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.

The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.

Flags:

C: Unaffected.

Z: Set if the two bits are the same; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

opc dst | b | 0 src 3 6 17 r0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:


BCP R1,01H.1

→


If destination working register R1 contains the value 07H (00000111B) and the source register

01H contains the value 01H (00000001B), the statement "BCP R1, 01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

6-18


BITC

— Bit Complement

BITC

dst.b

Flags:

This instruction complements the specified bit within the destination without affecting any other bits in the destination.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

opc


Example:

Given: R1 = 07H

BITC R1.1

→

R1 = 05H

If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in register R1.

Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared.

6-19


BITR

— Bit Reset

BITR

dst.b

The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination.

No flags are affected.

Flags:

Format:

Bytes Addr Mode

(Hex) dst

opc


Example:

Given: R1 = 07H:

BITR R1.1

→

R1 = 05H

If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B).

6-20


BITS

— Bit Set

BITS

dst.b

The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination.


Flags:

Format:

Bytes Addr Mode

(Hex) dst

Example:


Given: R1 = 07H:

BITS R1.3

→

R1 = 0FH

If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B).

6-21


BOR

— Bit OR

BOR

BOR

dst,src.b dst.b,src or

Flags:

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.

No other bits of the destination are affected. The source is unaffected.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

opc src 3 6 07 r0

opc dst 3 6 07 r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:


BOR R1,

→

BOR 01H.2,

→



In the first example, destination working register R1 contains the value 07H (00000111B) and source register 01H the value 03H (00000011B). The statement "BOR R1, 01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value

(07H) in working register R1.

In the second example, destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2, R1" logically ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H.

6-22


BTJRF

— Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation: If src(b) is a "0", then PC

← PC + dst

The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed.


Flags:

Format:

(Note 1)

Bytes Addr Mode

(Hex) dst src

dst 3 10 37 rb

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRF SKIP,R1.3

→

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP, R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-23


BTJRT

— Bit Test, Jump Relative on True

BTJRT

dst,src.b

Operation: If src(b) is a "1", then PC

← PC + dst

The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed.


Flags:

Format:

(Note 1)

Bytes

(Hex)

Addr Mode dst src

dst 3 10 37 rb

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRT SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP, R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the

PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-24


BXOR

— Bit XOR

BXOR

BXOR


Flags:

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

opc src 3 6 27 r0

opc dst 3 6 27 r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):

BXOR

→

BXOR 01H.2,R1

→



In the first example, destination working register R1 has the value 07H (00000111B) and source register 01H has the value 03H (00000011B). The statement "BXOR R1, 01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected.

6-25


CALL

— Call Procedure

CALL

dst

Operation: SP

←

SP – 1

@SP

← PCH

PC

The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter.

Flags:


Format:

Bytes Addr Mode

(Hex) dst

Examples:

Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:

CALL

→

SP = 0000H

(Memory locations 0000H = 1AH, 0001H = 4AH, where

CALL

→

CALL #40H

→

SP = 0000H (0000H = 1AH, 0001H = 49H)

SP = 0000H (0000H = 1AH, 0001H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack.

The stack pointer now points to memory location 0000H. The PC is then loaded with the value

3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed.

Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H contains 35H and program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example.

6-26


CCF

— Complement Carry Flag

CCF

Flags:

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.

C: Complemented.

No other flags are affected.

Format:

Bytes Opcode

(Hex)

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.

6-27


CLR

— Clear

CLR

dst

The destination location is cleared to "0".


Flags:

Format:

Bytes Addr Mode

(Hex) dst

4 B1 IR

Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

CLR 00H

→

Register 00H = 00H


In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.

6-28


COM

— Complement

COM

dst

Flags:

The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.

C: Unaffected.



V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 61 IR

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM

→

COM @R1

→

R1 = 0F8H

R1 = 07H, register 07H = 0EH

In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-29


CP

— Compare

CP

dst,src

Operation: dst – src

The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.



V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

opc dst | src

6 A3 r lr

6 A5 R IR

Examples:

1. Given: R1 = 02H and R2 = 03H:

CP R1,R2

→

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the value

03H. The statement "CP R1, R2" subtracts the R2 value (source/subtrahend) from the R1 value

(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are

"1".

2. Given: R1 = 05H and R2 = 0AH:

CP R1,R2

SKIP

In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1, R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3, R1" executes, the value 06H remains in working register R3.

6-30


CPIJE

— Compare, Increment, and Jump on Equal

CPIJE

dst,src,RA

Operation: If dst – src = "0", PC

← PC + RA

The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the

CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 02H:

CPIJE R1,@R2,SKIP

→

R2 = 04H, PC jumps to SKIP location

In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1, @R2, SKIP" compares the @R2 value

02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-31


CPIJNE

— Compare, Increment, and Jump on Non-Equal

CPIJNE

dst,src,RA

Operation: If dst – src "0", PC

← PC + RA

The source operand is compared to (subtracted from) the destination operand. If the result is not

"0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

src dst

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 04H:

CPIJNE R1,@R2,SKIP

→

R2 = 04H, PC jumps to SKIP location

Working register R1 contains the value 02H, working register R2 (the source pointer) the value

03H, and general register 03 the value 04H. The statement "CPIJNE R1, @R2, SKIP" subtracts

04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.

(Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-32


DA

— Decimal Adjust

DA

dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits):

Instruction Carry

Before DA

Bits 4–7

Value (Hex)

H Flag

Before DA

Bits 0–3

Value (Hex)

Number Added to Byte

Carry

After DA

0 0–9 0 0–9 00 0

0 0–8 0 A–F 06 0

0 0–9 1 0–3 06 0

ADD 0 A–F 0 0–9 60 1

ADC 0 9–F 0 A–F 66 1

1 0–2 0 0–9 60 1

1 0–2 0 A–F 66 1

1 0–3 1 0–3 66 1

SUB

SBC

0

0

1

1

0–9

0–8

7–F

6–F

0

1

0

1

0–9

6–F

0–9

6–F

00 = – 00

FA = – 06

A0 = – 60

9A = – 66

0

0

1

1

Flags: C:

Set if there was a carry from the most significant bit; cleared otherwise (see table).

Z: Set if result is "0"; cleared otherwise.

S: Set if result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 41 IR

6-33


DA

— Decimal Adjust

DA

(Continued)

Example:

Given: Working register R0 contains the value 15 (BCD), working register R1 contains

27 (BCD), and address 27H contains 46 (BCD):

ADD R1,R0

← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH

DA R1 ; R1

← 3CH + 06

If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic:

0 0 0 1 0 1 0 1

0 0 1 1 1 1 0 0 =

15

+ 0 0 1 0 0 1 1 1 27

3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:

0 0 1 1 1 1 0 0

+ 0 0 0 0 0 1 1 0

0 1 0 0 0 0 1 0 = 42

Assuming the same values given above, the statements

SUB 27H,R0

← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = 1

DA @R1

← 31–0 leave the value 31 (BCD) in address 27H (@R1).

6-34


DEC

— Decrement

DEC

dst

Flags:

The contents of the destination operand are decremented by one.

C: Unaffected.


S: Set if result is negative; cleared otherwise.


D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 01 IR

Examples:


DEC R1

→

DEC @R1

→

R1 = 02H

Register 03H = 0FH

In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.

6-35


DECW

— Decrement Word

DECW

dst

Flags:

The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

8 81 IR

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

DECW

→

DECW @R2

→

R0 = 12H, R1 = 33H

Register 30H = 0FH, register 31H = 20H

NOTE:

In the first example, destination register R0 contains the value 12H and register R1 the value

34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H.

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example:

LOOP: RR0

LD R2,R1

OR R2,R0

6-36


DI

— Disable Interrupts

DI

Operation: SYM (0)

← 0

Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

Flags:


Format:

Bytes Opcode

(Hex)

Example:

Given: SYM = 01H:

DI

If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing.

Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

6-37


DIV

— Divide (Unsigned)

DIV

dst,src

Operation: dst ÷ src dst (UPPER)

← REMAINDER dst (LOWER)

← QUOTIENT

Flags:

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is

≥ 2

8

, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers.

C: Set if the V flag is set and quotient is between 2

8

and 2

9

–1; cleared otherwise.

Z: Set if divisor or quotient = "0"; cleared otherwise.

S: Set if MSB of quotient = "1"; cleared otherwise.

V: Set if quotient is

≥ 2

8 or if divisor = "0"; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.

Examples:

Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:

DIV RR0,R2

→

DIV RR0,@R2

→

DIV RR0,#20H

→

R0 = 03H, R1 = 40H

R0 = 03H, R1 = 20H

R0 = 03H, R1 = 80H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H

(R1), and register R2 contains the value 40H. The statement "DIV RR0, R2" divides the 16-bit

RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1).

6-38


DJNZ

— Decrement and Jump if Non-Zero

DJNZ

r,dst

Flags:

Format:

If r

≠ 0, PC ← PC + dst

The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to –128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement.

NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

No flags are affected. r | opc dst 2 8 (jump taken)

8 (no jump)

(Hex)

rA r = 0 to F

dst

RA

Example:

Given: R1 = 02H and LOOP is the label of a relative address:

SRP #0C0H

DJNZ R1,LOOP

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register

R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.

Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label.

6-39


EI

— Enable Interrupts

EI

Operation: SYM (0)

← 1

An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.

Flags:


Format:

Bytes Opcode

(Hex)

Example:

Given: SYM = 00H:

EI

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.)

6-40


ENTER

— Enter

ENTER

Operation: SP

←

SP – 2

This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two.


Flags:

Format:

Bytes Opcode

(Hex)

Example:

The diagram below shows one example of how to use an ENTER statement.

Before

Address

IP

0050

Data

PC

SP

0040

0022

Address

40

41

42

43

Enter

Address H

Address L

Address H

Data

1F

01

10

22

Data

Stack

Memory

Address

IP

0043

Data

After

PC

SP

0110

0020

Address

40

41

42

43

Enter

Address H

Address L

Address H

Data

1F

01

10

20

21

22

IPH

IPL

Data

Stack

00

50

110 Routine

Memory

6-41

INSTRUCTION SET

EXIT

— Exit

EXIT

Operation: IP

← @SP

S3F80N8_UM_REV1.10

This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.


Flags:

Format:

Bytes Cycles Opcode

1 stack) 2F

Example:

The diagram below shows one example of how to use an EXIT statement.

Address

IP 0050

Data

Before

PC

0040

Address

50

51

PCL old

PCH

Data

60

00

SP

0022

140 Exit 2F

20

21

22

IPH

IPL

Data

Stack

00

50

Memory

Address

IP 0052

Data

After

Address

PC

0060

60 Main

SP

0022

22

Data

Stack

Memory

Data

6-42


IDLE

— Idle Operation

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.

In application programs, a IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

Example:

The instruction

IDLE

NOP

NOP

NOP

; stops the CPU clock but not the system clock

6-43


INC

— Increment

INC

dst

Flags:

The contents of the destination operand are incremented by one.

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

dst | opc 1

Cycles Opcode

(Hex) dst

4 rE r r = 0 to F

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC R0

→

INC 00H

→

R0 = 1CH

Register 00H = 0DH

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement "INC

R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.

6-44


INCW

— Increment Word

INCW

dst

Flags:

The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

8 A1 IR

Examples:

Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:

INCW

→

INCW @R1

→

R0 = 1AH, R1 = 03H


NOTE:

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect

Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to

00H and register 02H from 0FH to 10H.

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an

INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example:

LOOP: INCW RR0

6-45

INSTRUCTION SET

IRET

— Interrupt Return

IRET

IRET (Normal) IRET (Fast)

PC

↔ IP

FLAGS

← FLAGS'

FIS

← 0

S3F80N8_UM_REV1.10

This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Flags:

Format:

IRET

(Normal)

opc

IRET

(Fast)

opc

Example:

12 (internal stack)

1 6 BF

In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address.

The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H.

0H

FFH

100H

IRET

Interrupt

Service

Routine

JP to FFH

NOTE:

FFFFH

In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the IPR register).

6-46


JP

— Jump

JP

cc,dst (Conditional)

JP

dst (Unconditional)

Operation: If cc is true, PC

← dst

The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the

PC.


Flags:

Format:

(1)

(2) cc | opc

(Hex) dst

dst 3 DA cc = 0 to F

NOTES:

1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

JP

JP

C,LABEL_W

→ LABEL_W = 1000H, PC = 1000H

@00H

→ PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C, LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-47


JR

— Jump Relative

JR

cc,dst

Operation: If cc is true, PC

← PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes).

The range of the relative address is +127, –128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement.


Flags:

Format:

(1) cc | opc

Bytes

(Hex)

cc = 0 to F

Addr Mode dst

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

If the carry flag is set (that is, if the condition code is true), the statement "JR C, LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.

6-48


LD

— Load

LD

dst,src

The contents of the source are loaded into the destination. The source's contents are unaffected.


Flags:

Format:

dst | opc src | opc opc src dst dst | src

Bytes Addr Mode

(Hex) dst src

2 4 rC r IM

2

2

4

4

4 r9 r = 0 to F

C7

D7

R r

Ir lr r r

6 E5 R IR opc opc dst | src src | dst x x

3

3

6

6

87

97 r x [r] x [r] r

6-49


LD

— Load

LD

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

LD R0,#10H

→

LD R0,01H

→

LD 01H,R0

→

LD R1,@R0

→

LD @R0,R1

→

LD 00H,01H

→

LD 02H,@00H

→

LD 00H,#0AH

→

LD @00H,#10H

→

LD @00H,02H

→

LD R0,#LOOP[R1]

R0 = 10H



R1 = 20H, R0 = 01H

R0 = 01H, R1 = 0AH, register 01H = 0AH



Register 00H = 0AH


Register 00H = 01H, register 01H = 02, register 02H = 02H

R0 = 0FFH, R1 = 0AH

Register 31H = 0AH, R0 = 01H, R1 = 0AH

6-50


LDB

— Load Bit

LDB

LDB


The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

opc

opc src dst

3 6 47 r0

3 6 47 r0

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0 = 06H and general register 00H = 05H:

LDB R0,00H.2

→

LDB 00H.0,R0

→



In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the

00H register into bit zero of the R0 register, leaving the value 07H in register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general register 00H.

6-51


LDC/LDE

— Load Memory

LDC/LDE

dst,src

This instruction loads a byte from program or data memory into a working register or vice-versa.

The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

1. opc

2. opc src | dst

3. opc

4. opc dst | src dst | src src | dst

5. opc dst | src

XS

3 12 E7 r

XS

3 12 F7

XL

L

XL

H

6. opc src | dst

XL

L

XL

H

7. opc dst | 0000

DA

L

DA

H

8. opc src | 0000

DA

L

DA

H

9. opc dst | 0001

DA

L

DA

H

10. opc src | 0001

DA

L

DA

H

NOTES:

1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.

2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one

byte.

3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two

bytes.

4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.

6-52


LDC/LDE

— Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations

0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

LDC R0,@RR2 ;

← contents of program memory location 0104H

LDE R0,@RR2

; R0 = 1AH, R2 = 01H, R3 = 04H

;

← contents of external data memory location 0104H

; R0 = 2AH, R2 = 01H, R3 = 04H

LDC @RR2,R0 ; 11H (contents of R0) is loaded into program memory

; (RR2),

; working registers R0, R2, R3

→ no change

LDE @RR2,R0 ; 11H (contents of R0) is loaded into external data memory

;

LDC R0,#01H[RR2]

(RR2),

; working registers R0, R2, R3

→ no change

; R0


; (01H + RR2),

LDE R0,#01H[RR2]

; R0 = 6DH, R2 = 01H, R3 = 04H

;

; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H

LDC

(note)

#01H[RR2],R0 ; 11H (contents of R0) is loaded into program memory location

; 0104H)

LDE #01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory

LDC R0,#1000H[RR2] location

;

(01H


LDE R0,#1000H[RR2]

; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

;

← contents of external data memory location 1104H

LDC R0,1104H

; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

;

← contents of program memory location 1104H,

LDE R0,1104H

; R0 = 88H

;

← contents of external data memory location 1104H,

; R0 = 98H

LDC 1105H,R0 ; 11H (contents of R0) is loaded into program memory location

; (1105H)

LDE 1105H,R0 ; 11H (contents of R0) is loaded into external data memory

; location 1105H, (1105H)

← 11H

NOTE: These instructions are not supported by masked ROM type devices.

6-53

INSTRUCTION SET

LDCD/LDED

— Load Memory and Decrement

LDCD/LDED

dst,src

S3F80N8_UM_REV1.10

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

opc dst | src 2 10 E2 r Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH:

LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6

← RR6 – 1)

LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one (RR6

← RR6 – 1)

; R8 = 0DDH, R6 = 10H, R7 = 32H

6-54


LDCI/LDEI

— Load Memory and Increment

LDCI/LDEI

dst,src

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes

'Irr' even for program memory and odd for data memory.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

opc dst | src 2 10 E3 r Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6

; R8 = 0CDH, R6 = 10H, R7 = 34H

← RR6 + 1)

LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6

← RR6 + 1)

; R8 = 0DDH, R6 = 10H, R7 = 34H

6-55

INSTRUCTION SET

LDCPD/LDEPD

— Load Memory with Pre-Decrement

LDCPD/

LDEPD

dst,src

S3F80N8_UM_REV1.10

These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location.

The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

opc src | dst 2 14 F2 Irr r

Examples:

Given: R0 = 77H, R6 = 30H, and R7 = 00H:

LDCPD

; 77H (contents of R0) is loaded into program memory location

;

; R0 = 77H, R6 = 2FH, R7 = 0FFH

LDEPD

; 77H (contents of R0) is loaded into external data memory

; location 2FFFH (3000H – 1H)

; R0 = 77H, R6 = 2FH, R7 = 0FFH

6-56


LDCPI/LDEPI

— Load Memory with Pre-Increment

LDCPI/

LDEPI

dst,src

These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

opc src | dst 2 14 F3 Irr r

Examples:

Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:

LDCPI

LDEPI @RR6,R0

; 7FH (contents of R0) is loaded into program memory

; location 2200H (21FFH + 1H)

; R0 = 7FH, R6 = 22H, R7 = 00H

; (RR6

← RR6 + 1)

; 7FH (contents of R0) is loaded into external data memory

; location 2200H (21FFH + 1H)

; R0 = 7FH, R6 = 22H, R7 = 00H

6-57


LDW

— Load Word

LDW

dst,src

The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

8 C5 IR

Examples:

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH:

LDW RR6,RR4

→

LDW 00H,02H

→

LDW RR2,@R7

→

LDW 04H,@01H

→

LDW RR6,#1234H

LDW 02H,#0FEDH

R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH

Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH

R2 = 03H, R3 = 0FH,

Register 04H = 03H, register 05H = 0FH

R6 = 12H, R7 = 34H

Register 02H = 0FH, register 03H = 0EDH

In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H.

The other examples show how to use the LDW instruction with various addressing modes and formats.

6-58


MULT

— Multiply (Unsigned)

MULT

dst,src

Flags:

The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers.

C: Set if result is

H: Unaffected.

> 255; cleared otherwise.


S: Set if MSB of the result is a "1"; cleared otherwise.

V: Cleared.

D: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

MULT 02H

→

MULT @01H

→

MULT #30H

→

Register 00H = 01H, register 01H = 20H, register 02H = 09H

Register 00H = 00H, register 01H = 0C0H


In the first example, the statement "MULT 00H, 02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The

16-bit product, 0120H, is stored in the register pair 00H, 01H.

6-59

INSTRUCTION SET

NEXT

— Next

NEXT

S3F80N8_UM_REV1.10

The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.


Flags:

Format:

Bytes Opcode

(Hex)

Example:

The following diagram shows one example of how to use the NEXT instruction.

Address

IP 0043

Data

PC

0120

Before

Address

43

44

45

Address H

Address L

Address H

01

10

Address

IP 0045

Data

After

PC

0130

Address

43

44

45

Address H

Address L

Address H

Data

120 Next

Memory

130 Routine

Memory

6-60


NOP

— No Operation

NOP

Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.

Flags:


Format:

Bytes Opcode

(Hex)

Example:

When the instruction

NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.

6-61


OR

— Logical OR

OR

dst,src

Flags:

The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored.

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src


6 43 lr

6 45 IR

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH:

OR R0,R1

→

OR R0,@R2

→

OR 00H,01H

→

OR 01H,@00H

→

OR 00H,#02H

→

R0 = 3FH, R1 = 2AH

R0 = 37H, R2 = 01H, register 01H = 37H

Register 00H = 3FH, register 01H = 37H

Register 00H = 08H, register 01H = 0BFH

Register 00H = 0AH

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0, R1" logical-ORs the R0 and R1 register contents and stores the result

(3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing modes and formats.

6-62


POP

— Pop From Stack

POP

dst

The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.

No flags affected.

Flags:

Format:

Bytes Addr Mode

(Hex) dst

8 51 IR

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H:

POP 00H

→

POP @00H

Register 00H = 55H, SP = 00FCH

Register 00H = 01H, register 01H = 55H, SP = 00FCH

In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location

00FCH.

6-63

INSTRUCTION SET

POPUD

— Pop User Stack (Decrementing)

POPUD

dst,src

S3F80N8_UM_REV1.10

This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

Example:

Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H:

Register 00H = 41H, register 02H = 6FH, register 42H = 6FH

If general register 00H contains the value 42H and register 42H the value 6FH, the statement

"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H.

6-64


POPUI

— Pop User Stack (Incrementing)

POPUI

dst,src

The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

Example:

Given: Register 00H = 01H and register 01H = 70H:

POPUI 02H,@00H

→


If general register 00H contains the value 01H and register 01H the value 70H, the statement

"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

6-65

INSTRUCTION SET

PUSH

— Push To Stack

PUSH

src

S3F80N8_UM_REV1.10

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.


Flags:

Format:

opc src 2 8 (internal clock)

8 (external clock)

8 (internal clock)

8 (external clock)

(Hex)

70

71

dst

R

IR

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:

PUSH

→

PUSH

→

Register 40H = 4FH, stack register 0FFH = 4FH,

SPH = 0FFH, SPL = 0FFH

Register 40H = 4FH, register 4FH = 0AAH, stack register

0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH

In the first example, if the stack pointer contains the value 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack.

6-66


PUSHUD

— Push User Stack (Decrementing)

PUSHUD

dst,src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:

PUSHUD @00H,01H

→


If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUD @00H, 01H" decrements the user stack pointer by one, leaving the value 02H. The

01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer.

6-67

INSTRUCTION SET

PUSHUI

— Push User Stack (Incrementing)

PUSHUI

dst,src

S3F80N8_UM_REV1.10

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:

PUSHUI @00H,01H

→


If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUI @00H, 01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer.

6-68


RCF

— Reset Carry Flag

RCF

RCF

The carry flag is cleared to logic zero, regardless of its previous value.


Format:

Bytes Opcode

(Hex)

Example:

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

6-69

INSTRUCTION SET

RET

— Return

RET

S3F80N8_UM_REV1.10

The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value.


Flags:

Format:

Bytes Cycles Opcode

Example:

Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:

RET

→

PC = 101AH, SP = 00FEH

The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the

PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH.

6-70


RL

— Rotate Left

RL

dst dst (n + 1)

← dst (n), n = 0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

7 0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 91 IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

RL 00H

→

RL @01H

Register 00H = 55H, C = "1"

Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.

6-71

INSTRUCTION SET

RLC

— Rotate Left Through Carry

RLC

dst

S3F80N8_UM_REV1.10

dst (n + 1)

← dst (n), n = 0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

7 0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".



V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 11 IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC 00H

→

RLC @01H


Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if general register 00H has the value 0AAH (10101010B), the statement

"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H

(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

6-72


RR

— Rotate Right

RR

dst dst (7)

← dst (0)

The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7 0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".





D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 E1 IR

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

RR @01H


Register 01H = 02H, register 02H = 8BH, C = "1"

In the first example, if general register 00H contains the value 31H (00110001B), the statement

"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

6-73


RRC

— Rotate Right Through Carry

RRC

dst

Operation: dst (7)

← C dst (n)

← dst (n + 1), n = 0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7

(MSB).

7 0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0" cleared otherwise.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 C1 IR

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC 00H

→

RRC @01H

Register 00H = 2AH, C = "1"

Register 01H = 02H, register 02H = 0BH, C = "1"

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".

6-74


SB0

— Select Bank 0

SB0

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.


Flags:

Format:

Bytes Opcode

(Hex)

SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing.

6-75


SB1

— Select Bank 1

SB1

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3F8-series microcontrollers.)


Flags:

Format:

Bytes Opcode

(Hex)

Example:

The statement

SB1

Sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.

6-76


SBC

— Subtract with Carry

SBC

dst,src

Flags:

The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry

("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.

C: Set if a borrow occurred (src

> dst); cleared otherwise.



V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign

of the result is the same as the sign of the source; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a "borrow".

Format:

Bytes Addr Mode

(Hex) dst src


6 33 lr

6 35 IR

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register

03H = 0AH:

SBC R1,R2 R1 = 0CH, R2 = 03H

SBC R1,@R2

→

R1 = 05H, R2 = 03H, register 03H = 0AH

SBC 01H,02H

→

SBC 01H,@02H

→

SBC 01H,#8AH

→

Register 01H = 1CH, register 02H = 03H

Register 01H = 15H,register 02H = 03H, register 03H = 0AH

Register 01H = 95H; C, S, and V = "1"

In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1, R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.

6-77


SCF

— Set Carry Flag

SCF

The carry flag (C) is set to logic one, regardless of its previous value.

Flags: C:

Set to "1".


Format:

Bytes Opcode

(Hex)

Example:

The statement

SCF

Sets the carry flag to logic one.

6-78


SRA

— Shift Right Arithmetic

SRA

dst

Operation: dst (7)

← dst (7) dst (n)

← dst (n + 1), n = 0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.

7 6 0

C

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 D1 IR

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA 00H

→

Register 00H = 0CD, C = "0"

Register 02H = 03H, register 03H = 0DEH, C = "0"

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.

6-79


SRP/SRP0/SRP1

— Set Register Pointer

SRP

SRP0

src src

SRP1

src

Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7)

← src

If src (1) = 0 and src (0) = 1 then: RP1 (3–7)

← src

If src (1) = 0 and src (0) = 0 then: RP0 (4–7)

← src

The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.


Flags:

Format:

Bytes Addr Mode

(Hex) src

Examples:

The statement

SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location

0D7H to 48H.

The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H.

6-80


STOP

— Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the nRESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.

In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus.


Flags:

Format:

Bytes Addr Mode

(Hex) dst src

Example:

The statement

STOP

NOP

NOP

NOP

; halts all microcontroller operations

6-81


SUB

— Subtract

SUB

dst,src

Flags:

The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

C: Set if a "borrow" occurred; cleared otherwise.



V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign

of the result is of the same as the sign of the source operand; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise indicating a "borrow".

Format:

Bytes Addr Mode

(Hex) dst src

opc dst | src

6 23 lr

6 25 IR

Examples:


SUB R1,R2

→

SUB R1,@R2

→

SUB 01H,02H

→

SUB 01H,@02H

→

SUB 01H,#90H

→

SUB 01H,#65H

→

R1 = 0FH, R2 = 03H

R1 = 08H, R2 = 03H

Register 01H = 1EH, register 02H = 03H


Register 01H = 91H; C, S, and V = "1"

Register 01H = 0BCH; C and S = "1", V = "0"

In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1, R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.

6-82


SWAP

— Swap Nibbles

SWAP

dst

Operation: dst (0 – 3)

↔ dst (4 – 7)

The contents of the lower four bits and upper four bits of the destination operand are swapped.

7 4 3 0

Flags:

C: Undefined.



V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst

4 F1 IR

Examples:

Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:

SWAP

→

SWAP

→

Register 00H = 0E3H

Register 02H = 03H, register 03H = 4AH

In the first example, if general register 00H contains the value 3EH (00111110B), the statement

"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value

0E3H (11100011B).

6-83


TCM

— Test Complement Under Mask

TCM

dst,src

Operation: (NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src


6 63 lr

6 65 IR

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:

TCM R0,R1

→

TCM R0,@R1

→

TCM 00H,01H

→

TCM 00H,@01H

→

TCM 00H,#34

→

R0 = 0C7H, R1 = 02H, Z = "1"

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "1"

Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1"

Register 00H = 2BH, Z = "0"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0, R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.

6-84


TM

— Test Under Mask

TM

dst,src

Operation: dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src


6 73 lr

6 75 IR

Examples:


TM R0,R1

→

TM R0,@R1

→

TM 00H,01H

→

TM 00H,@01H

→

TM 00H,#54H

→

R0 = 0C7H, R1 = 02H, Z = "0"

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "0"

Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, Z = "1"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0, R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.

6-85


WFI

— Wait for Interrupt

WFI

Operation:

The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt.


Flags:

Format:

Bytes Opcode

(Hex)

(

n = 1, 2, 3, … )

Example:

The following sample program structure shows the sequence of operations that follow a "WFI" statement:

.

.

.

Main program

EI

WFI

.

.

.

(Next instruction)

Interrupt occurs

.

.

.

Interrupt service routine

Clear interrupt flag

IRET

(Enable global interrupt)

(Wait for interrupt)

Service routine completed

6-86


XOR

— Logical Exclusive OR

XOR

dst,src

Flags:

The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

C: Unaffected.




D: Unaffected.

H: Unaffected.

Format:

Bytes Addr Mode

(Hex) dst src

opc dst | src 2 4 B2 r r

6 B3 r lr

6 B5 R IR

Examples:


XOR R0,R1

→

XOR R0,@R1

→

XOR 00H,01H

→

XOR 00H,@01H

→

XOR 00H,#54H

→

R0 = 0C5H, R1 = 02H

R0 = 0E4H, R1 = 02H, register 02H = 23H



Register 00H = 7FH

In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0, R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.

6-87

INSTRUCTION SET

NOTES

S3F80N8_UM_REV1.10

6-88

S3F80N8_UM_REV1.10

7

CLOCK CIRCUIT

OVERVIEW

The S3F80N8 microcontroller CPU and peripheral hardware operate on the system clock frequency supplied through the clock circuit. The maximum CPU clock frequency of S3F80N8 is determined by CLKCON register settings.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal, ceramic resonator, RC oscillation source, or an external clock source

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)

— System clock control register, CLKCON

— STOP control register, STOPCON

7-1

CLOCK CIRCUIT

MAIN OSCILLATOR CIRCUITS

S3F80N8_UM_REV1.10

X

IN

X

OUT

Figure 7-1. Crystal/Ceramic Oscillator (fosc)

R

V

CC

X

OUT

X

IN

Figure 7-3. RC Oscillator MODE 2(fosc)

X

IN

X

OUT

Figure 7-2. External Oscillator (fosc)

7-2

S3F80N8_UM_REV1.10

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter).

— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers, timer/ counters, and watch timer. Idle mode is released by a reset or by an external or internal interrupt.

INT

INT release

STOP enable

CLKCON.7

STOP OSC inst.

STOPCON

Stop Release

Main-System

Oscillator Circuit fosc

CLKCON.4-.3

Stop

1/2-1/4096

Frequency

Dividing Circuit

Basic Timer

Timer 0

System Clock

1/1 1/2 1/8 1/16

Selector

IDLE Instruction

CPU Clock

Figure 7-4. System Clock Circuit Diagram

7-3

CLOCK CIRCUIT S3F80N8_UM_REV1.10

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located at address D4H. It is read/write addressable and has the following functions:

— Oscillator frequency divide-by value

After the main oscillator is activated, the fosc is selected as the CPU clock. If necessary, you can then increase the CPU clock speed f

OSC

/16, f

OSC

/8 or f

OSC

/2.

MSB .7

System Clock Control Register (CLKCON)

D4H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not used Not used

Divide-by selection bits for

CPU clock frequency:

00 = f

OSC

/16

01 = f

OSC

/8

10 = f

OSC

/2

11 = f

OSC

/1

Figure 7-5. System Clock Control Register (CLKCON)

MSB .7

.6

STOP Control Register (STPCON)

FBH, R/W

.5

.4

.3

.2

.1

.0

LSB

STOP Control bits

Other values = Disable STOP instruction

10100101 = Enable STOP instruction

NOTE:

Before execute the STOP instruction, set this STPCON register as "10100101B"

Otherwise the STOP instruction will not execute as well as reset will be generated.

Figure 7-6. STOP Control Register (STPCON)

7-4

S3F80N8_UM_REV1.10 RESET and POWER-DOWN

8

RESET and POWER-DOWN

SYSTEM RESET

OVERVIEW

By smart option (3EH.5 in ROM), user can select internal RESET (LVR) or external RESET.

The S3F80N8 can be reset in four ways:

— by external power-on-reset

— by the external reset input pin pulled low

— by the digital watchdog timing out

— by the Low Voltage reset circuit (LVR)

During a power-on reset, the voltage at V

DD

goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through an Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3F80N8 into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance.

Whenever a reset occurs during normal operation (that is, when both V

DD

and nRESET are High level), the nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values.

The on-chip Low Voltage Reset, features static Reset when supply voltage is below a reference value (Typ. 2.2V,

3.9 V). Thanks to this feature, external reset circuit can be removed while keeping the application safety. As long as the supply voltage is below the reference value, there is an internal and static RESET. The MCU can start only when the supply voltage rises over the reference value.

When you calculate power consumption, please remember that a static current of LVR circuit should be added a

CPU operating current in any operating modes such as Stop, Idle, and normal RUN mode.

8-1

RESET and POWER-DOWN S3F80N8_UM_REV1.10

W atchdog RESET

RESET

V

DD

N.F

Longger than 1us

Internal System

RESETB

V

IN

V

REF

+

-

Comparator

N.F

Longger than 1us

V

DD

Smart Option 3EH.5, 3EH.6

W hen the V

DD

level is lower than V

LVR

V

REF

IVR

NOTES:

1. The target of voltage detection level is the one you selected at sm art option 3EH.

2. IVR is Internal voltage Reference

Figure 8-1. Low Voltage Reset Circuit

In summary, the following sequence of events occurs during a reset operation:

— All interrupt is disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0-3 are set to input mode (P2.5 is open-drain output mode), and pull-up resistors of P0, P1 and P2 are disabled for the I/O port, but pull-up resistors of P3 are enabled for the I/O port.

— Peripheral control and data register settings are disabled and reset to their default hardware values.

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed.

8-2


NORMAL MODE RESET OPERATION

In normal mode, the Test pin is tied to V

SS

. A reset enables access to the 8-Kbyte on-chip ROM.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the upper nibble of BTCON.

HARDWARE RESET VALUES

Table 8-1 and 8-2 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An "x" means that the bit value is undefined after a reset.

— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.

Table 8-1. S3F80N8 Register and Values after Reset

Register NAME

Timer 0 Counter Register


Timer 0 Control Register


Clock Control Register

System Flags Register

Register Pointer 0

Register Pointer 1

Stack Pointer Register(Low Byte)

Instruction Pointer(High Byte)

Instruction Pointer(Low Byte)


Interrupt Mask Register

System Mode Register

Register Page Register

Mnemonic

T0CNT

T0DATA R/W

T0CON

BTCON R/W

CLKCON

FLAGS R/W

RP0

RP1

R/W

R

R/W

R/W

R/W

R/W


Decimal Hex 7 6 5 4 3 2 1 0

208

209

210

211

212

213

214

215

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

Location D8H is not mapped.

0

1

0

0

0 x

1

1

0

1

0

0

– x

1

1

0

1

0

0

– x

0

0

0

1

0

0

0 x

0

0

0

1

0

0

0 x

0

1

0

1

0

0

– x

–

–

0

1

0

0

–

0

–

–

0

1

0

0

–

0

–

–

SPL

IPH

IPL

IRQ

IMR

SYM

PP

R/W

R/W

R/W

R

R/W

R/W

R/W

217

218

219

220

221

222

223

D9H

DAH

DBH

DCH

DDH

DEH

DFH x x x

0

0

0

0 x x x

0

0

–

0 x x x

0

0

–

0 x x x

0

0 x

0 x x x

0

0 x

0 x x x

0

0 x

0 x x x

0

0

0

0 x x x

0

0

0

0

8-3


Table 8-1. S3F80N8 Register and Values after nRESET (Continued)

Register NAME





Mnemonic R/W

P0

P1

P2

P3

R/W

R/W

R/W

R/W




Decimal Hex 7 6 5 4 3 2 1 0

224

225

E0H

E1H

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

226

227

228

229

E2H

E3H

E4H

E5H

–

–

0

0

–

–

0

0

0

–

0

0

0

–

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


P0PUR R/W 230 E6H 0 0 0 0 0 0 0

Location E7H is not mapped.

Port 1 control register (High byte) P1CONH R/W 232 E8H 0 0 0 0 0 0 0 0



P1PUR R/W

External interrupt enable register EXTINT R/W

External interrupt pending register EXTPND R/W

233

234

235

236

E9H

EAH 0

EBH

ECH

Location EDH is not mapped.

0

0

0

0

0

0

0

0

0 0 0 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0




P2PUR R/W

Port 3 control register

238

239

EEH

EFH

–

0

–

0

–

0

–

0

1

0

0

0

0

0

0

0

240 F0H – 0 0 0 0 0 0

Locations F1H is not mapped.

P3CON R/W 242 F2H 0 0 0 0 0 0 0 0


P3PUR R/W 243 F3H – – – 1 1 1 1

STOP control register

Basic timer counter register


Locations F4H-FAH are not mapped.

STOPCON R/W 251 FBH 0 0 0 0 0 0 0 0

Location FCH is not mapped.

BTCNT R 253 FDH 0 0 0 0 0 0 0 0

Location FEH is not mapped.

IPR R/W 255 FFH x x x x x x x x

8-4


POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted except the IVC (Interval Voltage Converter) module. That is, the on-chip oscillator for system clock stops and the supply current is reduced to about 2.5

μA. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by external interrupts.

NOTE

Do not use stop mode if you are using an external clock source because X

IN input must be restricted internally to V

SS

to reduce current leakage.

Using nRESET to Release Stop Mode

Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock fosc because CLKCON.0 and CLKCON.1 are cleared to

'00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode.

The external interrupts in the S3F80N8 interrupt structure that can be used to release Stop mode are:

— External interrupts P1.0–P1.7 (INT0–INT7)

Please note the following conditions for Stop mode release:

— If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged except STPCON register.

— If you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering stop mode.

— When the Stop mode is released by external interrupt, the CLKCON.1 and CLKCON.0 bit-pair setting remains unchanged and the currently selected clock value is used.

— The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed.

How to Enter into Stop Mode

Handling STPCON register then writing Stop instruction (keep the order).

STOP

NOP

NOP

NOP

8-5


IDLE MODE

Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered.

There are two ways to release idle mode:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock fosc because CLKCON.0 and

CLKCON.1 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode.

2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.1 and CLKCON.0 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed.

8-6

S3F80N8_UM_REV1.10

9

I/O PORTS

OVERVIEW

The S3F80N8 microcontroller has four bit-programmable ports, P0-3. This gives a total of 26 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3F80N8 can be configured to input or output mode.

Table 9-1 gives you a General overview of the S3F80N8 I/O port functions.

Table 9-1. S3F80N8 Port Configuration Overview

0

1

2

3

Bit programmable I/O port.

Normal CMOS input or push-pull, open-drain output mode selected by software; software assignable pull-ups.


Normal CMOS input or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternately P1.0-1.7 can be used as inputs for external interrupts INT0-NT7


Normal CMOS input or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternately P2.2, P2.3 can be used as CLO, T0CK. P2.4 can be used as

T0PWM or T0CAP. PORT2[5:0] can sink 80mA current.


Normal CMOS input or push-pull, open-drain output mode selected by software; software assignable pull-ups.

NOTE: PORT2[5:0] can sink 80mA current. However only one PORT can be used to sink as large as 80mA current in the same time.

9-1

I/O PORTS S3F80N8_UM_REV1.10

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all four S3F80N8 I/O port data registers. Data registers for ports 0, 1, 2, 3 have the general format shown in Figure 9-1.

Register Name





Table 9-2. Port Data Register Summary

Mnemonic

P0

P1

P2

P3

Decimal

240

241

242

243

Hex

E0H

E1H

E2H

E3H

R/W

R/W

R/W

R/W

R/W

9-2

S3F80N8_UM_REV1.10

PORT 0

Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E0H. P0.0-0.7 can serve as inputs and as outputs (push-pull or opendrain).

Port 0 Control Registers (P0CONH, P0CONL)

Port 0 has two 8-bit control registers: P0CONH for P0.4-0.7 and P0CONL for P0.0-0.3. A reset clears the

P0CONH and P0CONL registers to "00H". You use control registers setting to select input or output mode (pushpull or open-drain).

Port 0 Pull-Up Resistor Control Register (P0PUR)

Using the port0 pull-up resistor control register, P0PUR (E6H), you can configure pull-up resistors to individual port.

MSB .7

Port 0 Control Register, High-byte (P0CONH)

E4H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.4

P0.5

P0.6

P0.7

P0CONH bit-pair pin configuration

0 0

0 1

1 0

1 1

Normal input mode

Output mode, push-pull

Output mode, open-drain

Not used

Figure 9-1. Port 0 High-Byte Control Register (P0CONH)

9-3

I/O PORTS

MSB .7

Port 0 Control Register, Low-byte (P0CONL)

E5H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.0

P0.1

P0.2

P0.3

P0CONL bit-pair pin configuration

0 0

0 1

1 0

1 1

Normal input mode


Output mode, opne-drain

Not used

Figure 9-2. Port 0 Low-Byte Control Register (P0CONL)

MSB .7

Port 0 Pull-up Control Register (P0PUR)

E6H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

P0PUR bit configuration settings:

0

1

Disable pull-up resistor

Enable pull-up resistor

Figure 9-3. Port 0 Pull-up Control Register (P0PUR)

S3F80N8_UM_REV1.10

9-4

S3F80N8_UM_REV1.10

PORT 1

Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E2H. P1.0-1.7 can serve as inputs, as outputs (push-pull or open-drain) or it can be configured the following functions.

— External interrupt INT0-INT7



P1CONH and P1CONL registers to "00H", configuring P1.0-1.7 pins to input mode with interrupt on falling edge.

You use control registers setting to select input or output mode (push-pull or open-drain).

Port 1 Pull-Up Resistor Control Register (P1PUR)

Using the port1 pull-up resistor control register, P1PUR (EAH), you can configure pull-up resistors to individual port 1 pins.

Port 1 Interrupt Control Registers (EXTINT, EXTPND)

To process external interrupts at the port 1 pins, two additional control registers are provided: the external interrupt enable register (EBH) and the external interrupt pending register (ECH).

The EXTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the register at regular intervals.

In EXTINT, when the interrupt enable bit of any port 1 pin is “1”, a falling edge at that pin will generate an interrupt request. The corresponding pending bit is then automatically set to “1” and the IRQ level goes low to signal the

CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must clear the pending condition by writing a “0” to the corresponding EXTPND bit.

9-5


MSB .7


E8H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P1.7/INT7

P1.6/INT6

P1.5/INT5

P1.4/INT4

P1CONH bit-pair pin configuration

0 0

0 1

1 0

1 1

CMOS input;

External falling edge interrupt input

CMOS input;

External both falling edge an rising edge interrupt input




MSB .7


E9H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P1.3/INT3

P1.2/INT2

P1.1/INT1

P1.0/INT0

P1CONL bit-pair pin configuration

0 0

0 1

1 0

1 1

CMOS input;

External falling edge interrupt input

CMOS input;

External both falling edge an rising edge interrupt input




9-6

S3F80N8_UM_REV1.10

MSB .7


EAH, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0


0

1




MSB .7

External Interrupt Enable Register (EXTINT)

EBH, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

INTn bit configuration settings:

0

1

Disable interrupt

Enable interrupt

NOTE:

"n" is 0, 1, 2, 3, 4, 5, 6, and 7.

Figure 9-7. External Interrupt Enable Register (EXTINT)

9-7


MSB .7

External Interrupt Pending Register (EXTPND)

ECH, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

EXTPND bit configuration settings:

1

1

0

0

No interrupt pending (when read)

Pending bit clear (when write)

Interrupt is pending (when read)

No effect (when write)

NOTE:

"n" is 0, 1, 2, 3, 4, 5, 6, and 7.

Figure 9-8. External Interrupt Pending Register

9-8

S3F80N8_UM_REV1.10

PORT 2

•

•

•

Port 2 is an 6-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the Port 2 data register, P2 at location E2H. P2.0-2.5 can serve as inputs and as outputs (push pull or open-drain) or you can configure the following alternative functions:

P2.2: CLO

P2.3: T0CK

P2.4: T0PWM, T0CAP



P2CONH registers to “08H” and P2CONL registers to “00H”, configuring all pins to input mode (except that P2.5 open drain output). You use control registers settings to select input or output mode (push-pull or open drain) and enable the alternative functions.

When programming the port, please remember that any alternative peripheral I/O function you configure using the port 2 control registers must also be enabled in the associated peripheral module.

Port 2 Pull-up Resistor Control Register (P2PUR)

Using the port 2 pull-up resistor control register, P2PUR (F0H), you can configure pull-up resistors to individual port 2 pins.

MSB .7


EEH, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not used P2.5

P2.4/T0

P2CONH bit-pair pin configuration settings:

0 0

0 1

1 0

1 1

Normal input mode or T0 Capture input



Alternative function: T0 PWM output

NOTE:

The reset value of P2.5 is open-drain output.


9-9


MSB .7


EFH, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P2.1

P2.3/T0CLK

P2.2/CLO

P2CONL bit-pair pin configuration settings:

0 0

0 1

1 0

1 1

Input mode



Alternative function: T0CLK/CLO

P2.0


MSB .7


F0H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0


0

1




9-10

S3F80N8_UM_REV1.10

PORT3 (32-PIN S3F80N8)

Port 3 is a 4-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the Port 3 data register, P3 at location E3H. P3.0-3.3 can serve as inputs and as outputs (push pull or opendrain).

Port 3 Control Registers (P3CON)

Port 3 has an 8-bit control registers: P3CON for P3.0-3.3. A reset clears the P3CON registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull or open drain).

Port 3 Pull-up Resistor Control Register (P3PUR)

Using the port 3 pull-up resistor control register, P3PUR (F3H), you can configure pull-up resistors to individual port 3 pins.

MSB .7

.6

Port 3 Control Register (P3CON)

F2H, R/W

.5

.4

.3

.2

.1

.0

LSB

P3.1

P3.2

P3.3

P3CON bit-pair pin configuration settings:

0 0

0 1

1 0

1 1

Input mode



Not used

P3.0

Figure 9-12. Port 3 Control Register (P3CON)

9-11

I/O PORTS

MSB .7


F3H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P3.3

P3.2

P3.1

P3.0

Not used


0

1



NOTE:

The reset value of P3PUR is pull-up enable.


S3F80N8_UM_REV1.10

9-12

S3F80N8_UM_REV1.10 BASIC TIMER and TIMER 0

10

BASIC TIMER and TIMER 0

OVERVIEW

The S3F80N8 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0.

BASIC TIMER (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.

— To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (f osc

divided by 4096, 1024, 128) with multiplexer

— 8-bit basic timer counter, BTCNT (FDH, read-only)

— Basic timer control register, BTCON (D3H, read/write)

10-1

BASIC TIMER and TIMER 0 S3F80N8_UM_REV1.10

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in address

D3H, and is read/write addressable using Register addressing mode.

A reset clears BTCON to “00H”. This enables the watchdog function and selects a basic timer clock frequency of f osc

/4096. To disable the watchdog function, you must write the signature code “1010B” to the basic timer register control bits BTCON.7–BTCON.4.

The 8-bit basic timer counter, BTCNT (FDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for all timers input clock, you write a "1" to BTCON.0.

MSB .7

Basic Timer Control Register (BTCON)

D3H, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Watchdog timer enable bits:

1010B = Disable watchdog function

Others value = Enable watchdog function

Divider clear bit for timer:

0 = No effect

1 = Clear divider

Basic timer counter clear bits:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00 = f

OSC

/4096

01 = f

OSC

/1024

10 = f

OSC

/128

11 = Invalid selection

Figure 10-1. Basic Timer Control Register (BTCON)

10-2


BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to

“00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt.

In stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fosc/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when stop mode is released:

1. During stop mode, a power-on reset or external interrupt occurs to trigger the stop mode release and oscillation starts.

2. If a power-on reset occurred, the basic timer counter will increase at the rate of fosc/4096. If an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.

4. When BTCNT.4 is set, normal CPU operation resumes.

10-3


V

DD

RESET

Internal

Reset

Release

Oscillation Stabilization Time

0.8 V

DD

Reset Release Voltage

Normal Operating mode trst

~

RC

0.8 V

DD

Oscillator

(X

OUT

)

Oscillator Stabilization Time

BTCNT clock

BTCNT value

00000B t

WAIT

= (4096x16)/f

OSC

10000B

Basic timer increment and

CPU operations are IDLE mode

NOTE: Duration of the oscillator stabilization wait time, t

WAIT

, when it is released by a t

Power-on-reset is 4096 x 16/f

OSC

.

RST

~

Figure 10-2. Oscillation Stabilization Time on RESET

10-4


External

Interrupt

RESET

STOP

Release

Signal

V

DD

Normal

Operating

Mode

STOP

Instruction

Execution

STOP Mode

Oscillator

(X

OUT

)

Oscillation Stabilization Time

Normal

Operating

Mode

STOP Mode

Release Signal

BTCNT clock

BTCNT

Value

10000B

00000B t

WAIT

Basic Timer Increment

NOTE: Duration of the oscillator stabilzation wait time, t

WAIT

, it is released by an interrupt is determined by the setting in basic timer control register, BTCON.

BTCON.3

BTCON.2

0 0

0

1

1

1

0

1

t

WAIT

(4096 x 16)/fosc

(1024 x 16)/fosc

(128 x 16)/fosc

Invalid setting

t

WAIT

(When f

OSC

is 10 MHz)

6.55 ms

1.64 ms

0.2 ms

Figure 10-3. Oscillation Stabilization Time on STOP Mode Release

10-5


f

OSC

DIV

1/4096

1/1024

1/128

R

Bits 3, 2

MUX

Bit 1

RESET or STOP

Clear

Data Bus


(Write '1010xxxxB' to disable.)

8-Bit Up Counter

(BTCNT, Read-Only)

Start the CPU

(NOTE)

OVF

RESET

Bit 0

NOTE:

During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until BTCNT.4 is set).

Figure 10-4. Basic Timer Block Diagram

10-6


8-BIT TIMER/COUNTER 0

Timer/counter 0 has three operating modes, one of which you select using the appropriate T0CON setting:

— Interval timer mode

— Capture input mode with a rising or falling edge trigger at the P2.4 pin

Timer/counter 0 has the following functional components:

— Clock frequency divider (fosc divided by 4096, 256, 8 or external clock (P2.3/T0CK) with multiplexer

— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)

— I/O pins for capture input or PWM output (P2.4/T0CAP, T0PWM)

— Timer 0 overflow interrupt (IRQ2, vector EAH) and match/capture interrupt (IRQ2, vector ECH) generation

— Timer 0 control register, T0CON (D2H, read/write)

TIMER/COUNTER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt

— Clear timer 0 match/capture interrupt pending condition

10-7


T0CON is located at address D2H, and is read/write addressable using Register addressing mode.

A reset clears T0CON to “00H”. This sets timer 0 to normal interval timer mode, selects an input clock frequency of f

OSC

/4096, and disables timer 0 interrupt. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ2 and has the vector address EAH. When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer 0 match/capture interrupt (IRQ2, vector ECH), you must write T0CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit,

T0CON.0.

MSB .7

.6

Timer 0 Control Register (T0CON)

D2H, R/W

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

00 = f

OSC

/4096

01 = f

OSC

/256

10 = f

OSC

/8

11 = External clock (P2.3/T0CLK)

Timer 0 match interrupt pending bit:

0 = No interrupt pending (When read)

0 = Clear pending bit (when write)

1 = Interrupt is pending (When read)

1 = no effect (When write)

Timer 0 interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Timer 0 operating mode selection bits:

00 = Interval mode (match interrupt can occur)

01 = Capture mode (capture on rising edge,

counter running, capture interrupt can occur)

10 = Capture mode (capture on falling edge,

counter running, capture interrupt can occur)

11 = PWM mode (match and OVF interrupt can occur)

Figure 10-5. Timer 0 Control Register (T0CON)

10-8


TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ2, Vectors EAH and ECH)

The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/capture interrupt (T0INT). T0OVF belongs to interrupt level IRQ2, vector EAH. T0INT also belongs to interrupt level IRQ2, but is assigned to a separate vector address, ECH.

A Timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been service.

However, the timer 0 match/capture interrupt pending condition must be cleared by the application's interrupt service routine by writing a "0" to the T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector

ECH) and clears the counter.

If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches “10H”. At this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes.

CLK 8-Bit Up Counter

8-Bit Comparator

R (Clear)

Capture Signal

Match

M

U

X

Timer 0 Buffer Register

T0CON.5-.4

Match Signal

Overflow Signal

T0CON.3


Interrupt Enable/Disable

TOCON.1

TOCON.0

Pending

T0INT (IRQ2)

(Match INT)

T0 PWM

Output (P2.4)

Figure 10-6. Simplified Timer 0 Function Diagram: Interval Timer Mode

10-9


Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T0PWM (P2.4) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".

Although you can use the match signal to generate a timer 0 match interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T0PWM (P2.4) pin is held to Low level as long as the reference data value is less than or equal to (

≤ ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t

CLK

× 256 (see Figure 10-7).

CLK pending

T0OVF (IRQ2)

(Overflow INT)

8-Bit Up Counter

Capture Signal

T0CON.2

Overflow Interrupt Enable/Disable

8-Bit Comparator

Match

M

U

X


Match Signal

Overflow Signal

T0CON.3

T0CON.5-.4

Match Interrupt Enable/Disable

TOCON.1

TOCON.0

Pending

T0INT (IRQ2)

(Match INT)

T0 PWM

Output (P2.4)

High level when data

> counter,

Lower level when data

< counter


Figure 10-7. Simplified Timer 0 Function Diagram: PWM Mode

10-10


Capture Mode

In capture mode, a signal edge that is detected at the T0CAP (P2.4) pin opens a gate and loads the current counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation.

Timer 0 also gives you capture input source: the signal edge at the T0CAP (P2.4) pin. You select the capture input by setting the values of the timer 0 capture input selection bits in the timer 0 control register, T0CON.5-.4

(D2H).

The timer 0 match/capture interrupt is generated whenever the counter value is loaded into the timer 0 data register.

By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-8).

CLK

8-Bit Up Counter

T0 CAP input

(P2.4)

T0CON.5-.4

Match Signal


M

U

X

T0CON.5-.4

Interrupt Enable/Disable

T0CON.1

T0CON.0

Pending

T0INT (IRQ2)

(Capture INT)

Figure 10-8. Simplified Timer 0 Function Diagram: Capture Mode

10-11


fosc

R

DIV fosc/4096 fosc/1024 fosc/128

MUX

BTCON.0

P2.3/

T0CK

T0CAP

Bits 5, 4

T0CON.7-.6

T0CON.2

T0OVF

Data BUS

T0CON.3

8

8-bit Up Counter

(Read-Only)

R

Clear

8-Bit Comparator


M

U

X

T0CON.5-.4

Match signal

T0OVF

T0CON.3

T0CON.0

T0CON.1

T0INT

(IRQ2)

P2.4/

T0PWM


8

Data BUS

Figure 10-9. Timer 0 Block Diagram

10-12

S3F80N8_UM_REV1.10 LOW VOLTAGE RESET

11

LOW VOLTAGE RESET

OVERVIEW

The S3F80N8 can be reset in four ways:

— by external power-on-reset

— by the external reset input pin pulled low

— by the digital watchdog timing out

— by the Low Voltage reset circuit (LVR)

During an external power-on reset, the voltage VDD is High level and the nRESET pin is forced Low level. The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the S3F80N8 into a known operating status. To ensure correct start-up, the user should take that reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency.

The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation stabilization time for a reset is approximately 6.55 ms (

≅2

16

/fosc, fosc= 10MHz).

When a reset occurs during normal operation (with both VDD and nRESET at High level), the signal at the nRESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then set to their default hardware reset values (see Table 8-1).

The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction. If watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated.

The S3F80N8 has a built-in low voltage reset circuit that allows detection of power voltage drop of external V

DD input level to prevent a MCU from malfunctioning in an unstable MCU power level. This voltage detector works for the reset operation of MCU. This Low Voltage reset includes an analog comparator and Vref circuit. The value of a detection voltage is 2.2/3.9V. The on-chip Low Voltage Reset, features static reset when supply voltage is below a reference voltage value (Typical 2.2/ 3.9 V). Thanks to this feature, external reset circuit can be removed while keeping the application safety. As long as the supply voltage is below the reference value, there is an internal and static RESET. The MCU can start only when the supply voltage rises over the reference voltage.

When you calculate power consumption, please remember that a static current of LVR circuit should be added a

CPU operating current in any operating modes such as Stop, Idle, and normal RUN mode.

11-1

LOW VOLTAGE RESET S3F80N8_UM_REV1.10

Watchdog nRESET

nRESET

N.F

Longger than 1us

V

DD

V

IN

V

REF

+

Comparator

-

V

DD

V

REF

IVR

N.F

Longger than 1us

Internal System nRESET

When the VDD level is

Lower than 2.2/3.9V

NOTES:

1. The target of voltage detection level is 2.2/3.9V at VDD=5V.

2. IVR is the Internal voltage Reference.

Figure 11-1. Low Voltage Reset Circuit

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON.

11-2

S3F80N8_UM_REV1.10 ELECTRICAL

12

ELECTRICAL DATA

OVERVIEW

In this chapter, S3F80N8 electrical characteristics are presented in tables and graphs.

The information is arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Current Characteristics

— Data retention supply voltage in stop mode

— Oscillation stabilization time

— Input Low Width Electrical Characteristics

— Operating voltage range

— LVR circuit characteristics

— LVR reset timing

Table 12-1. Absolute Maximum Ratings

(T

A

= 25

°

C)

Parameter Symbol

Supply Voltage V

DD

Input Voltage

Output Voltage

Output Current High

V

I

V

O

I

OH

Conditions

–

All ports

All output ports

One I/O pin active

Output Current Low

Operating Temperature

Storage Temperature

I

OL

T

A

T

STG

All I/O pins active

One I/O pin active

All I/O pins active

–

–

Rating Unit

- 0.3 to + 7.0 V

- 0.3 to V

DD

+ 0.3

- 0.3 to V

DD

+ 0.3

- 25

V

V mA

- 80

+ 80

+ 100

- 40 to + 85

- 65 to + 150 mA

°

°

C

C

12-1

ELECTRICAL DATA S3F80N8_UM_REV1.10

Table 12-2. DC Electrical Characteristics

(T

A

= –40

°

C to + 85

°

C, V

DD

= 2.0 V to 5.5 V)


Operating

Voltage

Input High

Voltage

Vdd

V

IH1

T

A

= – 40 °C to + 85 °C

Ports 0, 1, 2, 3, nRESET

V

DD

Min Typ Max Unit

2.0 – 5.5 V

= 2.0 to 5.5 V 0.8 V

DD

–

V

DD

V

Input Low

Voltage

Output High

Voltage

V

IH2

X

IN

, X

OUT

V

IL1

Ports 0, 1, 2, 3, nRESET

V

IL2

X

IN

, X

OUT

V

OH

I

OH

= – 10 mA

Ports 0, 1, 2, 3

V

DD

= 2.0 to 5.5 V V

DD

-0.1

V

DD

= 2.0 to 5.5 V

V

V

DD

DD

= 2.0 to 5.5 V

= 3.0 to 5.5 V V

DD

–1.0

–

V

DD

0.2V

DD

– –

Output Low

Voltage(1)

Output Low

Voltage(2)

V

OL1

I

OL

= 20mA

Port 0, 1, 3

V

OL2

I

OL

= 80mA

Port 2

V

DD

= 4.5 to 5.5 V

Input High

Leakage Current

I

I

LIH1

LIH2

All input pins, except I

X

IN

, X

LIH2

OUT

V

DD

= 5.0 V

T

A

= 25

°

C

V

IN

= V

DD

V

IN

= V

DD

Input Low

Leakage Current

Output High

Leakage Current

Output Low

Leakage Current

Pull-up Resistor

I

I

I

LIL1

All input pins, except nRESET and

I

LIL2

I

LIL2

X

IN

, X

OUT

V

IN

= 0 V

LOH

LOL

All output pins

All output pins

V

IN

= 0 V

V

OUT

= V

DD

V

OUT

= 0 V

– – 1

100

Ω

R

P1

V

IN

= 0 V, all ports except nRESET

V

DD

= 5.0 V,

T

A

= 25

°

C

R

P2

V

IN

= 0 V, nRESET V

DD

= 5.0 V,

T

A

= 25

°

C

12-2


Table 12-3. Current Characteristics

(T

A

= –40

°

C to + 85

°

C, V

DD

= 2.0 V to 5.5 V)


Supply

Current

(1)

I

DD1

Run mode:

V

DD

Conditions

10 MHz

= 5 V

±

10%

Min

–

Typ

5.0

Max

10.0

Units

mA

3.5 7.0

C1 = C2 = 22pF

V

DD

= 3.3 V

±

10%

10 MHz 4.0 8.0

I

DD2

Idle mode:

V

DD

= 5 V

±

10%

C1 = C2 = 22pF

V

DD

= 3.3 V

±

10%

10 MHz

10 MHz

I

DD3

(2)

Stop mode:

V

DD

= 2.0 ~ 5.5 V

(LVR disable)

V

DD

= 2.0 ~ 5.5 V

(LVR enable)

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors.

2. I

DD3

is current when system clock oscillation stops.

2.0

1.0

0.8

4.0

2.0

1.6

2.5 10

35 70

μA

μA

12-3


(T

A

= – 40

°

C to + 85

°

C)

Table 12-4. Data Retention Supply Voltage in Stop Mode

Typ Unit

Data retention supply voltage

Data retention supply current

V

DDDR

I

DDDR

V

DDDR

= 1.2 V, (T

A

= 25

°

C)

Stop mode

– – 5 uA

~ ~

~ ~

Oscillation

Stabilization Time

Idle Mode

V

DD

Stop Mode

Data Retention Mode

V

DDDR

Execution of

STOP Instruction

Normal

Operating Mode

Interrupt

0.2 V

DD t

WAIT

NOTE:

t

WAIT

is the same as 16 x 1/BT clock

Figure 12-1. Stop Mode Release Timing When Initiated by External Interrupt

V

DD

~ ~

~ ~

Stop Mode

Data Retention Mode

V

DDDR

RESET

Occurs

Oscillation

Stabilization

Time

Normal

Operating Mode

Execution of

STOP Instrction nRESET

0.2 V

DD t

WAIT

NOTE:

t

WAIT

is the same as 4096 x 16 x 1/fxx

Figure 12-2. Stop Mode Release Timing When Initiated by RESET

12-4


Table 12-5. Input/output Capacitance

(T

A

= 25

°

C, V

DD

= 0 V)


Input

Capacitance

C

IN

Conditions

f = 1 MHz; unmeasured pins are connected to V

SS

C

OUT

Output

Capacitance

I/O Capacitance

C

IO


Table 12-6. System Oscillation Characteristics

(T

A

= –40

°

C to + 85

°

C)

Crystal C1

X

IN

Oscillation

Frequency

Condition (V

DD

) Min Typ Max Unit

4.5V–5.5 V 1 – 10 MHz

Ceramic

C2

C1

X

OUT

X

IN

Oscillation

Frequency

4.5V–5.5 V 1 – 10 MHz

External

Clock

C2

X

OUT

X

IN

X

IN

input

Frequency

4.5 V–5.5 V 1 – 10 MHz

X

OUT

12-5

ELECTRICAL DATA

C P U C lo c k

1 0 M H z

8 M H z

4 M H z

3 M H z

2 M H z

1 M H z

1 2 3 4 4 . 5 5 5 .5

6

S u p p ly V o lt a g e ( V )

7

Figure 12-3. Operating Voltage Range

R

V

CC

X

OUT

X

IN

Figure 12-4. RC Oscillation (Mode2)

S3F80N8_UM_REV1.10

12-6


Table 12-7. RC Oscillation (Mode2) Characteristics

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.0V to 5.5 V)

Parameter Symbol Conditions Min

RC oscillator frequency

(1) f

RC

T

A

= 25

°

C

Accuracy of RC

Oscillation

ACC

RC

V

DD

=5V

± 10%, T

A

= 25

°

C

-20 – +20 %

RC oscillator setup time

(2) t

SURC

T

A

= 25

°

C

NOTES:

1. The resistor is connected between V

DD

and X

IN

pin. We recommend using 40KΩ resistor for 4MHz and 20KΩ for

8MHz.

2. Data based on characterization results, not tested in production.

Table 12-8. Oscillation Stabilization Time

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.0V to 5.5 V)

Crystal

Ceramic fx > 1 MHz

Oscillation stabilization occurs when V

DD

is equal to the minimum oscillator voltage range.

External Clock X

IN

input High and Low width (t

XH

, t

XL

)

– – 40 ms

– – 10 ms

X

IN

1/fx t

XL t

XH

Figure 12-5. Clock Timing Measurement at X

IN

V

DD

-0.1V

0.1V

12-7


Table 12-9. Input Low Width Electrical Characteristics

(T

A

= – 40

°

C to + 85

°

C, V

DD

= 2.0V to 5.5 V)


Interrupt input low width t

INTH

, t

INTL

Conditions

All interrupt V

DD

= 5 V


500 – – ns nRESET input low width t

RSL

10 – – us

NOTE: If width of interrupt or reset pulse is greater than min. value, pulse is always recognized as valid pulse. t

INTL

0.8 V

DD

0.2 V

DD t

INTH

0.2 V

DD

Figure 12-6. Input Timing for External Interrupts

t

RSL nRESET

0.2 V

DD

Figure 12-7. Input Timing for nRESET

Table 12-10. LVR Circuit Characteristics

(T

A

= 25

°C, V

DD

= 2.0 V to 5.5 V)

Low voltage reset

V

LVR

– 2.0

3.6

2.2

3.9

2.4

4.2

V

12-8


V

DD

Figure 12-8. LVR Reset Timing

V

LVR,MAX

V

LVR

V

LVR,MIN

Figure 12-9. The Circuit Diagram to Improve EFT Characteristics

NOTE

:

To improve EFT characteristics, we recommend using power capacitor near S3F80N8 like Figure 12-9.

Table12-11. ESD Characteristics


Electrostatic discharge

V

ESD

−

−

−

V

V

V

12-9

ELECTRICAL DATA

NOTES

S3F80N8_UM_REV1.10

12-10

S3F80N8_UM_REV1.10 MECHANICAL

13

MECHANICAL DATA

OVERVIEW

The S3F80N8 microcontroller is currently available in 28-SOP, 32-SOP, and 32-SDIP package.

0-8

#28 #15

28-SOP-375

#14

0.15

+ 0.10

- 0.05

#1

18.02 MAX

17.62

± 0.20

0.10 MAX

(0.56)

0.41

+ 0.10

- 0.05

1.27

NOTE: Dimensions are in millimeters.

Figure 13-1. 28-SOP-375 Package Dimensions

13-1

MECHANICAL DATA

#32 #17

0-8

S3F80N8_UM_REV1.10

32-SOP-450A

#1 #16

0.25

+ 0.10

- 0.05

20.30 MAX

19.90

± 0.20

(0.43)

0.40

± 0.10

1.27


Figure 13-2. 32-SOP-450A Package Dimensions

0.10 MAX

13-2

S3F80N8_UM_REV1.10 MECHANICAL

#32 #17

32-SDIP-400

0-15

0

.2

+

0

.1

0

-

5

0

.0

5

#1 #16

29.80 MAX

29.40±0.20

(1.37)

0.45

± 0.10

1.00

± 0.10

1.778


Figure 13-3. 32-SDIP-400 Package Dimensions

13-3

MECHANICAL DATA

NOTES

S3F80N8_UM_REV1.10

13-4

S3F80N8_UM_REV1.10 S3F80N8 FLASH MCU

14

S3F80N8 FLASH MCU

OVERVIEW

The S3F80N8 single-chip CMOS microcontroller is the Flash MCU version. It has an on-chip Half Flash ROM instead of a masked ROM. The Half Flash ROM is accessed by serial data format.

V

SS

X

OUT

X

IN

(V

PP

) TEST

P0.0

P0.1

nRESET

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.5

P3.3

P3.2

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

S3F80N8

32-SOP/SDIP

20

19

18

17

24

23

22

21

28

27

26

25

32

31

30

29

V

DD



P1.2/INT2

P1.3/INT3

P1.4/INT4

P1.5/INT5

P1.6/INT6

P1.7/INT7

P2.0

P2.1

P2.2/CLO

P2.3/T0CLK

P2.4/T0

P3.0

P3.1

Figure 14-1. S3F80N8 Pin Assignments (32-pin SOP/SDIP)

14-1

S3F80N8 FLASH MCU S3F80N8_UM_REV1.10

V

SS

X

OUT

X

IN

(V

PP

) TEST

P0.0

P0.1

nRESET

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.5

7

8

5

6

9

10

3

4

1

2

11

12

13

14

S3F80N8

28-SOP

24

23

22

21

20

19

28

27

26

25

18

17

16

15

V

DD



P1.2/INT2

P1.3/INT3

P1.4/INT4

P1.5/INT5

P1.6/INT6

P1.7/INT7

P2.0

P2.1

P2.2/CLO

P2.3/T0CLK

P2.4/T0

Figure 14-2. Pin Assignment (28-pin SOP)

Table 14-1. Descriptions of Pins Used to Read/Write the Flash ROM

Main Chip

Pin Name Pin Name Pin No.

During Programming

I/O Function

P1.1 SDAT I/O Serial data pin (output when reading, Input

26 (28-pin) when writing) Input and push-pull output port can be assigned

P1.0 SCLK I Serial clock pin (input only pin)

TEST VPP

31 (32-pin)

27 (28-pin)

4 I Power supply pin for flash ROM cell writing

(indicates that MTP enters into the writing mode). When 11 V

±0.25V is applied, MTP is in writing mode and when 5 V is applied,

MTP is in reading mode. (Option) nRESET nRESET

VDD/VSS

V

DD

/V

SS

7

32/1 (32-pin)

28/1 (28-pin)

I Initialization.

- Logic power supply pin.

NOTE: S3F80N8’s flash ROM must be programmed by VPP=11.0V

±0.25V. Some tools, for example, Openice-i500 only support VPP=12.5V, so it must not be connected to TEST pin directly. We suggest to use SPW-uni, AS-pro, US-pro and other tools which support VPP=11.0V for S3F80N8 programming.

14-2

S3F80N8_UM_REV1.10 S3F80N8 FLASH MCU

ON BOARD WRITING

The S3F80N8 needs only 6 signal lines including VDD and GND pins for writing internal flash memory with serial protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of application board is designed.

Circuit design guide

At the flash writing, the writing tool needs 6 signal lines that are GND, VDD, RESET, TEST, SDA and SCL. When you design the PCB circuits, you should consider the usage of these signal lines for the on-board writing.

In case of TEST pin, normally test pin is connected to GND but in writing mode and programming these two cases, a resistor should be inserted between the TEST pin and GND.

Please be careful to design the related circuit of these signal pins because rising/falling timing of VPP, SCL and

SDA is very important for proper programming.

SCL(I/O)

SDA(I/O)

RESET

R

Vpp

Vpp(TEST)

C

Vpp

V

DD

V

SS

Vdd

Vpp

SDA

RESET

SCL

GND

To Application circuit



SPW- uni , GW -uni , AS -pro , US -pro

Figure 14-3. PCB Design Guide for on Board Programming

NOTE

The recommended value of Rvpp is 330 ohm; The recommended value of Cvpp is 0.1uF.

14-3

S3F80N8 FLASH MCU

NOTES

S3F80N8_UM_REV1.10

14-4

S3F80N8_UM_REV1.10 DEVELOPMENT TOOLS

15

DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500 and

SK-1200, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting software that includes debugger, an assembler, and a program for setting options.

TARGET BOARDS

Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables and adapters are included on the device-specific target board. TB80N8 is a specific target board for the development of application systems using S3F80N8.

PROGRAMMING SOCKET ADAPTER

When you program S3F80N8’s flash memory by using an emulator or OTP/MTP writer, you need a specific programming socket adapter for S3F80N8.

15-1


[Development System Configuration]

S3F80N8_UM_REV1.10

Figure 15-1. Development System Configuration

15-2


TB80N8 TARGET BOARD

The TB80N8 target board can be used for development of S3F80N8.

The TB80N8 target board is operated as target CPU with Emulator (SK-1200, OPENIce I-500)

In-Circuit Emulator

(SK-1200,OPENIce I-500)

Off

To User_Vcc

On

U2

RESET

TEST_MODE

JP1

74HC11

Y1

25

RUN_MODE

J1A

1

128QFP

S3E80N8

EVA Chip

U1

MAIN_MODE

JP6

EVA_MODE

SW3

3EH

IDLE STOP

+

+

EXT

JP0

INT

1

J2

50

ON

25 26

Figure 15-2. TB80N8 Target Board Configuration

NOTES

1. TB80N8 should be supplied 5.0V normally.

2. The symbol ‘ ‘ marks start point of jumper signals.

15-3

DEVELOPMENT TOOLS S3F80N8_UM_REV1.10

Table 15-1. Components of TB80N8

J1A

Symbols Usage

100-pin connector

Description

Connection between emulator and TB80N8 target board.

J2

RESET

VCC, GND

50-pin connector

Push button

POWER connector

Connection between target board and user application system

Generation low active reset signal to S3F80N8 EVA-chip

IDLE, STOP LED

JP1, JP6

STOP/IDLE Display

MODE Selection

External power connector for TB80N8

Indicate the status of STOP or IDLE of S3F80N8 EVA-chip on TB80N8 target board

Selection of Flash tool/user mode and Eva/Main-chip mode

15-4


Table 15-2. Setting of the Jumper in TB80N8

JP# Description 1-2 Connection

JP1 Target board mode selection H: Test-Mode

H: Main Mode

2-3 Connection

L: User Mode

L: EVA Mode

Default

Setting

Join 2-3

Join 2-3

JP0 Clock source selection When using the internal clock source which is generated from Emulator, join connector 2-3 and 4-5 pin. If user wants to use the external clock source like a crystal, user should change the jumper setting from 1-2 to 5-6 and connect Y1 to an external clock source.

SW3 Smart option at address 3EH Dip switch for smart option. This 1byte is mapped address

3EH for special function. Refer to the page 2-3.

Connecting points for external clock source Y1 External clock source

To User

Vcc

Target System is supplied

VDD

Target Board is not supplied

VDD from user System.

Target Board is supplied

VDD from user System.

Emulator

2-3

4-5

Join 2-3

This is LED is ON when the evaluation chip (S3F80N8) is in idle mode.

This LED is ON when the evaluation chip (S3F80N8) is in stop mode.

15-5


J101

Vss

NC(X

OUT

)

NC(X

IN

)

TEST

P0.0

P0.1

DEMO_RSTB

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.5

P3.3

P3.2

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

18

19

20

21

14

15

16

17

22

23

10

11

12

13

8

9

6

7

3

4

1

2

5

24

25

33

32

31

30

37

36

35

34

29

28

41

40

39

38

45

44

43

42

50

49

48

47

46

27

26

USER_VDD

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT3

P1.4/INT4

P1.5/INT5

P1.6/INT6

P1.7/INT7

P2.0

P2.1

P2.2/CLO

P2.3/T0CLK

P2.4/T0

P3.0

P3.1

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Figure 15-3. 50-Pin Connector Pin Assignment for user System

Target Board

J2

1 50

User System

1 50

Target Cable for 50-Pin Connector

25 26 25 26

Figure 15-4. TB80N8 Probe Adapter Cable

15-6


Third parties for Development Tools

SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an

OTP/MTP programmer.

In-Circuit Emulator for SAM8 family

— OPENice-i500

— SmartKit

OTP/MTP Programmer

— SPW-uni

— AS-pro

— US-pro

— GW-uni (8 - gang programmer)

Development Tools Suppliers

Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools.

8-bit In-Circuit Emulator

OPENice - i500

AIJI System

• TEL: 82-31-223-6611

• FAX: 82-331-223-6613

• E-mail : [email protected]

• URL : http://www.aijisystem.com

SK-1200

Seminix

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819

• E-mail: [email protected]

• URL: http://www.seminix.com

15-7


OTP/MTP PROGRAMMER (WRITER)

SPW-uni

Single OTP/ MTP/FLASH Programmer

• Download/Upload and data edit function

• PC-based operation with USB port

• Full function regarding OTP/MTP/FLASH MCU

programmer

(Read, Program, Verify, Blank, Protection..)

• Fast programming speed (4Kbyte/sec)

• Support all of SAMSUNG OTP/MTP/FLASH MCU

devices

• Low-cost

• NOR Flash memory (SST,Samsung…)

• NAND Flash memory (SLC)

• New devices will be supported just by adding

device files or upgrading the software.

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.


• URL:

http://www.seminix.com

AS-pro

On-board programmer for Samsung Flash MCU

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.

• E-mail:

• Portable & Stand alone Samsung

OTP/MTP/FLASH Programmer for After Service

• Small size and Light for the portable use

• Support all of SAMSUNG OTP/MTP/FLASH

devices

• HEX file download via USB port from PC

• Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

• Internal large buffer memory (118M Bytes)

• Driver software run under various O/S [email protected]

• URL:


(Windows 95/98/2000/XP)

• Full function regarding OTP/MTP programmer


• Two kind of Power Supplies

(User system power or USB power adapter)

• Support Firmware upgrade

15-8


OTP/MTP PROGRAMMER (WRITER) (Continued)

US-pro

Portable Samsung OTP/MTP/FLASH Programmer

• Portable Samsung OTP/MTP/FLASH Programmer

• Small size and Light for the portable use

• Support all of SAMSUNG OTP/MTP/FLASH

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.

• E-mail:

devices

• Convenient USB connection to any IBM compatible

PC or Laptop computers.

• Operated by USB power of PC

• PC-based menu-drive software for simple operation

• Very fast program and verify time

( OTP:2Kbytes per second, MTP:10Kbytes per

second)

• Support Samsung standard Hex or Intel Hex format

• Driver software run under various O/S [email protected]

• URL:


(Windows 95/98/2000/XP)

• Full function regarding OTP/MTP programmer


• Support Firmware upgrade

GW-uni

Gang Programmer for OTP/MTP/FLASH MCU

• 8 devices programming at one time

• Fast programming speed (1.2Kbyte/sec)

• PC-based control operation mode or Stand-alone

• Full Function regarding OTP/MTP program

(Read, Program, Verify, Protection, Blank.)

• Data back-up even at power break

After setup in Design Lab, it can be moved to the

factory site.

• Key Lock protecting operator's mistake

• Good/Fail quantity displayed and memorized

• Buzzer sounds after programming

• User friendly single-menu operation (PC)

• Operation status displayed in LCD panel

Flash writing adapter board

• Special flash writing socket only for S3F80N8

- 32SDIP, 32SOP, 28SOP

SEMINIX

• TEL: 82-2-539-7891

• FAX: 82-2-539-7819.


• URL:


C&A technology

• TEL: 82-2-2612-9027

• FAX: 82-2-2612-9044

• E-mail:

[email protected]

• URL:

http://www.cnatech.com

15-9


NOTES

S3F80N8_UM_REV1.10

15-10

USER`S MANUAL

USER’S MANUAL

8-Bit CMOS Microcontrollers

November, 2008

REV 1.10

Confidential Proprietary of Samsung Electronics Co., Ltd

Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

Important Notice

NOTIFICATION OF REVISIONS

ORIGINATOR:

PRODUCT NAME:

DOCUMENT NAME:

DOCUMENT NUMBER:

EFFECTIVE DATE:

DIRECTIONS:

REVISION HISTORY

REVISION DESCRIPTIONS FOR REVISION 1.0

REVISION DESCRIPTIONS FOR REVISION 1.1

Preface

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

Chapter 2 Address Spaces

Chapter 3 Addressing Modes

Table of Contents

(Continued)

Chapter 4 Control Registers

Chapter 5 Interrupt Structure

Chapter 6 Instruction Set

Table of Contents

(Continued)

Part II Hardware Descriptions

Chapter 7 Clock Circuit

Chapter 8

Reset and Power-Down

Chapter 9 I/O Ports

Chapter 10 Basic Timer and Timer 0

Table of Contents

(Continued)

Chapter 11 Low Voltage Reset

Chapter 12 Electrical Data

Chapter 13 Mechanical Data

Chapter 14 S3F80N8 Flash MCU

Chapter 15 Development Tools

List of Figures

List of Figures

(Continued)

List of Figures

(Continued)

List of Tables

List of Programming Tips

List of Register Descriptions

List of Instruction Descriptions

List of Instruction Descriptions

(Continued)

PRODUCT OVERVIEW

S3F8-SERIES MICROCONTROLLERS

S3F80N8 MICROCONTROLLER

FEATURES

BLOCK DIAGRAM

PIN ASSIGNMENT

32-SOP/SDIP

28-SOP

PIN DESCRIPTIONS

PIN CIRCUITS

NOTES

ADDRESS SPACES

OVERVIEW

PROGRAM MEMORY (ROM)

SMART OPTION

REGISTER ARCHITECTURE

REGISTER ADDRESSING

SYSTEM AND USER STACK

ADDRESSING MODES

OVERVIEW

REGISTER ADDRESSING MODE (R)

INDIRECT REGISTER ADDRESSING MODE (IR)

INDIRECT REGISTER ADDRESSING MODE (Continued)

INDIRECT REGISTER ADDRESSING MODE (Continued)

~