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S3F80N8_UM_REV1.10 RESET and POWER-DOWN
NORMAL MODE RESET OPERATION
In normal mode, the Test pin is tied to V
SS
. A reset enables access to the 8-Kbyte on-chip ROM.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the upper nibble of BTCON.
HARDWARE RESET VALUES
Table 8-1 and 8-2 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An "x" means that the bit value is undefined after a reset.
— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.
Table 8-1. S3F80N8 Register and Values after Reset
Register NAME
Timer 0 Counter Register
Timer 0 Data Register
Timer 0 Control Register
Basic Timer Control Register
Clock Control Register
System Flags Register
Register Pointer 0
Register Pointer 1
Stack Pointer Register(Low Byte)
Instruction Pointer(High Byte)
Instruction Pointer(Low Byte)
Interrupt Request Register
Interrupt Mask Register
System Mode Register
Register Page Register
Mnemonic
T0CNT
T0DATA R/W
T0CON
BTCON R/W
CLKCON
FLAGS R/W
RP0
RP1
R/W
R
R/W
R/W
R/W
R/W
Address Reset Value (bit)
Decimal Hex 7 6 5 4 3 2 1 0
208
209
210
211
212
213
214
215
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
Location D8H is not mapped.
0
1
0
0
0 x
1
1
0
1
0
0
– x
1
1
0
1
0
0
– x
0
0
0
1
0
0
0 x
0
0
0
1
0
0
0 x
0
1
0
1
0
0
– x
–
–
0
1
0
0
–
0
–
–
0
1
0
0
–
0
–
–
SPL
IPH
IPL
IRQ
IMR
SYM
PP
R/W
R/W
R/W
R
R/W
R/W
R/W
217
218
219
220
221
222
223
D9H
DAH
DBH
DCH
DDH
DEH
DFH x x x
0
0
0
0 x x x
0
0
–
0 x x x
0
0
–
0 x x x
0
0 x
0 x x x
0
0 x
0 x x x
0
0 x
0 x x x
0
0
0
0 x x x
0
0
0
0
8-3
RESET and POWER-DOWN S3F80N8_UM_REV1.10
Table 8-1. S3F80N8 Register and Values after nRESET (Continued)
Register NAME
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Mnemonic R/W
P0
P1
P2
P3
R/W
R/W
R/W
R/W
Port 0 control register (High byte) P0CONH R/W
Port 0 control register (Low byte) P0CONL R/W
Address Reset Value (bit)
Decimal Hex 7 6 5 4 3 2 1 0
224
225
E0H
E1H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
226
227
228
229
E2H
E3H
E4H
E5H
–
–
0
0
–
–
0
0
0
–
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 0 pull-up resistor enable register
P0PUR R/W 230 E6H 0 0 0 0 0 0 0
Location E7H is not mapped.
Port 1 control register (High byte) P1CONH R/W 232 E8H 0 0 0 0 0 0 0 0
Port 1 control register (Low byte) P1CONL R/W
Port 1 pull-up resistor enable register
P1PUR R/W
External interrupt enable register EXTINT R/W
External interrupt pending register EXTPND R/W
233
234
235
236
E9H
EAH 0
EBH
ECH
Location EDH is not mapped.
0
0
0
0
0
0
0
0
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 2 control register (High byte) P2CONH R/W
Port 2 control register (Low byte) P2CONL R/W
Port 2 pull-up resistor enable register
P2PUR R/W
Port 3 control register
238
239
EEH
EFH
–
0
–
0
–
0
–
0
1
0
0
0
0
0
0
0
240 F0H – 0 0 0 0 0 0
Locations F1H is not mapped.
P3CON R/W 242 F2H 0 0 0 0 0 0 0 0
Port 3 pull-up resistor enable register
P3PUR R/W 243 F3H – – – 1 1 1 1
STOP control register
Basic timer counter register
Interrupt priority register
Locations F4H-FAH are not mapped.
STOPCON R/W 251 FBH 0 0 0 0 0 0 0 0
Location FCH is not mapped.
BTCNT R 253 FDH 0 0 0 0 0 0 0 0
Location FEH is not mapped.
IPR R/W 255 FFH x x x x x x x x
8-4
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