USER`S MANUAL

S3F80N8_UM_REV1.10 BASIC TIMER and TIMER 0

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to

“00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt.

In stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fosc/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when stop mode is released:

1. During stop mode, a power-on reset or external interrupt occurs to trigger the stop mode release and oscillation starts.

2. If a power-on reset occurred, the basic timer counter will increase at the rate of fosc/4096. If an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.

4. When BTCNT.4 is set, normal CPU operation resumes.

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BASIC TIMER and TIMER 0 S3F80N8_UM_REV1.10

V

DD

RESET

Internal

Reset

Release

Oscillation Stabilization Time

0.8 V

DD

Reset Release Voltage

Normal Operating mode trst

~

RC

0.8 V

DD

Oscillator

(X

OUT

)

Oscillator Stabilization Time

BTCNT clock

BTCNT value

00000B t

WAIT

= (4096x16)/f

OSC

10000B

Basic timer increment and

CPU operations are IDLE mode

NOTE: Duration of the oscillator stabilization wait time, t

WAIT

, when it is released by a t

Power-on-reset is 4096 x 16/f

OSC

.

RST

~

Figure 10-2. Oscillation Stabilization Time on RESET

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S3F80N8_UM_REV1.10 BASIC TIMER and TIMER 0

External

Interrupt

RESET

STOP

Release

Signal

V

DD

Normal

Operating

Mode

STOP

Instruction

Execution

STOP Mode

Oscillator

(X

OUT

)

Oscillation Stabilization Time

Normal

Operating

Mode

STOP Mode

Release Signal

BTCNT clock

BTCNT

Value

10000B

00000B t

WAIT

Basic Timer Increment

NOTE: Duration of the oscillator stabilzation wait time, t

WAIT

, it is released by an interrupt is determined by the setting in basic timer control register, BTCON.

BTCON.3

BTCON.2

0 0

0

1

1

1

0

1

t

WAIT

(4096 x 16)/fosc

(1024 x 16)/fosc

(128 x 16)/fosc

Invalid setting

t

WAIT

(When f

OSC

is 10 MHz)

6.55 ms

1.64 ms

0.2 ms

Figure 10-3. Oscillation Stabilization Time on STOP Mode Release

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BASIC TIMER and TIMER 0 S3F80N8_UM_REV1.10

f

OSC

DIV

1/4096

1/1024

1/128

R

Bits 3, 2

MUX

Bit 1

RESET or STOP

Clear

Data Bus

Basic Timer Control Register

(Write '1010xxxxB' to disable.)

8-Bit Up Counter

(BTCNT, Read-Only)

Start the CPU

(NOTE)

OVF

RESET

Bit 0

NOTE:

During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until BTCNT.4 is set).

Figure 10-4. Basic Timer Block Diagram

10-6