4.2 Timer Pacer Mode. ADLINK Technology PCI-7200

The digital OUT operation is: outport (BASE+14, 0xAAAAAAAA ) // (A : 0 ~ F)

The digital IN operation is:

value = inport (BASE+10) // The input status is save in the

// value variable

4.2 Timer Pacer Mode

The digital I/O access control is clocked by timer pacer, which is generated by a interval programming timer/counter chip 8254.

There are three timers on the 8254. The timer 0 is used to generate timer pacer for digital input, and timer 1 is used for digital output. The configuration is illustrated as below.

8254 Timer/Counter

4MHz Clock

CLK0

GATE0

Timer 0

OUT0 “H”

“H”

CLK1

GATE1

Timer 1

OUT1

“H”

CLK2

GATE2

Timer 2

OUT2

Digital Input Timer Pacer

Digital Output Timer Pacer

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Operation Theorem

The operation sequences are:

1. Define the frequency (timer pacer rate)

2. The digital input data are saved in FIFO after a timer pacer pulse is generated. The sampling is controlled by timer pacer.

3. The data saved in FIFO will be transferred to main memory of your computer system directly and automatically. This is controlled by bus mastering DMA control, this function is supported by PCI controller chip.

The operation flow is show as below:

8254 Timer/Counter

CLK0

GATE0

Timer 0

OUT0

1

To Digital Input Trigger

Latch Digital Input

3

PC's Main Memory

Bus mastering

DMA data Transfer

Digital Input FIFO

2

Operation Theorem

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