- Computers & electronics
- Computer components
- Interface components
- Digital & analog I/O modules
- ADLINK Technology
- PCI-7200
- Specification
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•
M2, M1 & M0 - Select Operating Mode (Bit 3, Bit 2, & Bit 1)
M2 x x
0
0
1
1
M1
1
1
0
0
0
0
M0
0
1
0
1
0
1
•
BCD - Select Binary/BCD Counting (Bit 0)
MODE
2
3
0
1
4
5
0
1
BINARY COUNTER 16-BITS
BINARY CODED DECIMAL (BCD) COUNTER (4
DECADES)
Note:
1. The count of the binary counter is from 0 up to 65,535.
2. The count of the BCD counter is from 0 up to 99,999.
A.3 Mode Definition
In 8254, there are six different operating modes can be selected.
The they are :
•
Mode 0 : interrupt on terminal count
The output will be initially low after the mode set operation.
After the count is loaded into the selected count register, the output will remain low and the counter will count. When terminal count is reached, the output will go high and remain high until the selected count register is reloaded with the mode or a new count is loaded. The counter continues to decrement after terminal count has been reached.
8254 Programmable Interval Time
••
77
Rewriting a counter register during counting results in the following:
(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
•
Mode 1 : Programmable One-Shot.
The output will go low on the count following the rising edge of the gate input. The output will go high on the terminal count. If a new count value is loaded while the output is low it will not affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at anytime without affecting the one-shot pulse.
The one-shot is re-triggerable, hence the output will remain low for the full count after any rising edge of the gate input.
•
Mode 2 : Rate Generator.
Divided by N counter. The output will be low for one period of the input clock. The period from one output pulse to the next equals the number of input counts in the count register. If the count register is reloaded between output pulses the present period will not be affected, but the subsequent period will reflect the new value.
The gate input when low, will force the output high. When the gate input goes high, the counter will start form the initial count. Thus, the gate input can be used to synchronized by software.
When this mode is set, the output will remain high until after the count register is loaded. The output then can also be synchronized by software.
78
••
8254 Programmable Interval Time
•
Mode 3 : Square Wave Rate Generator.
Similar to MODE 2 except that the output will remain high until one half the count has been completed (or even numbers) and go low for the other half of the count. This is accomplished by decrement the counter by two on the falling edge of each clock pulse. When the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated.
if the count is odd and the output is high, the first clock pulse
(after the count is loaded) decrements the count by 1.
Subsequent clock pulses decrement the clock by 2 after timeout, the output goes low and the full count is reloaded. The first clock pulse (following the reload) decrements the counter by 3. Subsequent clock pulses decrement the count by 2 until time-out. Then the whole process is repeated. In this way, if the count is odd, the output will be high for (N + 1)/2 counts and low for (N - 1)/2 counts.
In Modes 2 and 3, if a CLK source other then the system clock is used, GATE should be pulsed immediately following
Way Rate of a new count value.
•
Mode 4 : Software Triggered Strobe.
After the mode is set, the output will be high. When the count is loaded, the counter will begin counting. On terminal count, the output will go low for one input clock period, then will go high again.
If the count register is reloaded during counting, the new count will be loaded on the next CLK pulse. The count will be inhibited while the GATE input is low.
8254 Programmable Interval Time
••
79
•
Mode 5 : Hardware Triggered Strobe.
The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached. The counter is re-triggerable. the output will not go low until the full count after the rising edge of any trigger.
The detailed description of the mode of 8254, please refer the Intel
Microsystem Components Handbook.
80
••
8254 Programmable Interval Time
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Table of contents
- 11 CHAPTER 1 Introduction
- 12 Applications
- 12 Features
- 13 Specifications
- 15 CHAPTER 2 Installation
- 15 What You Have
- 16 Unpacking
- 16 Device Driver Installation for Windows
- 18 PCI-7200’s Layout
- 20 PCI-7200 Installation Outline
- 20 2.5.1 Hardware configuration
- 20 2.5.2 Slot selection
- 20 2.5.3 Installation Procedure
- 21 2.5.4 Running the 7200UTIL.EXE
- 21 Connector Pin Assignment
- 21 2.6.1 PCI-7200 Pin Assignment
- 23 2.6.2 cPCI-7200 Pin Assignment
- 23 8254 for Timer Pacer Generation
- 25 CHAPTER 3 Register Structure & Format
- 25 I/O Registers Format
- 26 Digital Input Register (BASE + 10)
- 26 Digital Output Register (BASE + 14)
- 27 DIO Status & Control Register (BASE + 18)
- 29 Interrupt Status & Control Register (BASE + 1C)
- 33 CHAPTER 4 Operation Theorem
- 33 4.1 Direct Program Control
- 34 4.2 Timer Pacer Mode
- 36 4.3 External Trigger
- 37 4.4 Handshaking
- 39 4.5 Timing Characteristic
- 43 CHAPTER 5 C/C++ & DLL Libraries
- 43 Installation
- 43 5.1.1 Installation
- 45 Running Testing Utility (7200UTIL.EXE)
- 46 Software Driver Naming Convention
- 46 _7200_Initial
- 48 _7200_Switch_Card_No
- 49 _7200_AUX_DI
- 50 _7200_AUX_DI_Channel
- 51 _7200_AUX_DO
- 52 _7200_AUX_DO_Channel
- 53 5.10 _7200_DI
- 54 5.11 _7200_DI_Channel
- 55 5.12 _7200_DO
- 56 5.13 _7200_DO_Channel
- 57 5.14 _7200_Alloc_DMA_Mem
- 59 5.15 _7200_Free_DMA_Mem
- 60 5.16 _7200_Alloc_DBDMA_Mem
- 61 5.17 _7200_Free_DBDMA_Mem
- 62 5.18 _7200_DI_DMA_Start
- 66 5.19 _7200_DI_DMA_Status
- 67 5.20 _7200_DI_DMA_Stop
- 68 5.21 _7200_DblBufferMode
- 69 5.22 _7200_CheckHalfReady
- 70 5.23 _7200_DblBufferTransfer
- 71 5.24 _7200_GetOverrunStatus
- 72 5.25 _7200_DO_DMA_Start
- 74 5.26 _7200_DO_DMA_Status
- 75 5.27 _7200_DO_DMA_Stop
- 76 5.28 _7200_DI_Timer
- 78 5.29 _7200_DO_Timer
- 81 CHAPTER 6 Double Buffer Mode Principle
- 83 CHAPTER 7 Limitation
- 85 The Intel (NEC)
- 86 The Control Byte
- 87 Mode Definition
- 91 Product Warranty/Service