STMicroelectronics L99DZ81EP Datasheet

L99DZ81EP
Door actuator driver
Datasheet - production data
Applications
 Door actuator driver with 3 bridges for double
door lock control, 4 high-side drivers for bulbs
and LEDs control.
 H-bridge control for external power transistors
*$3*&)7
TQFP-64
Description
Features
 One full bridge for 6 A load (RON = 150 m)
 One half bridges for 3 A load (RON = 300 m)
 One configurable high-side driver for up to
1.5 A (RON = 500 m) or 0.35 A
(RON = 1600 m) load
 One configurable high-side driver for 0.7 A
(RON = 800 m) or 0.35 A (RON = 1600 m)
load
The L99DZ81EP is a microcontroller driven
multifunctional door actuator driver for automotive
applications. Up to two DC motors and four
grounded resistive loads can be driven with three
half bridges and four high-side drivers. Four
external MOS transistors in bridge configuration
can be driven. The integrated SPI controls all
operating modes (forward, reverse, brake and
high impedance). Also all diagnostic information
is available via SPI read.
 Two high-side drivers for 0.5 A load
(RON = 1600 m)
 Programmable softstart function to drive loads
with higher inrush currents as current limitation
value
 Very low VS current consumption in standby
mode (IS < 6 µA typ; Tj  85°C)
 Current monitor output for all high-side drivers
 Central two-stage charge pump
 Motor bridge driver with full Rdson down to 6 V
 Device contains temperature warning and
protection
 Open-load detection for all outputs
 Overcurrent protection for all outputs
Table 1. Device summary
 Separated half bridges for door lock motor
 Programmable PWM control of all outputs
 STM standard serial peripheral interface
(ST-SPI 3.1)
Order codes
Package
TQFP-64
Tray
Tape and reel
L99DZ81EP
L99DZ81EPTR
 Prepared for additional fail-safe path for
H-bridge
September 2013
This is information on a product in full production.
DocID023145 Rev 2
1/62
www.st.com
Contents
L99DZ81EP
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1
3
2/62
TQFP-64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6
Outputs OUT4 - OUT10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7
H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8
SPI / logic – electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1
Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2
Wake up and Active mode/standby mode . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5
Overvoltage and undervoltage detection at VS . . . . . . . . . . . . . . . . . . . . 31
3.6
Overvoltage and undervoltage detection at VCC . . . . . . . . . . . . . . . . . . . 31
3.7
Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12
PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.13
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.14
Programmable soft-start function to drive loads with higher inrush current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.15
H-bridge control (DIR, PWMH, bits SD, SDS) . . . . . . . . . . . . . . . . . . . . . 34
3.16
H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.17
Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID023145 Rev 2
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Contents
3.18
Short circuit detection/drain source monitoring . . . . . . . . . . . . . . . . . . . . 36
3.19
H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.20
Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.21
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1
4.2
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.2
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.3
Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.4
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.5
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1
4.3
5
6
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1
Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3
Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.4
Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.5
Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.6
Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.7
Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.8
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.9
Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.10
Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.11
Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.12
Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1
ECOPACK® package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2
TQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3
TQFP-64 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DocID023145 Rev 2
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Contents
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L99DZ81EP
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DocID023145 Rev 2
L99DZ81EP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
On-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Gate drivers for the external Power-MOS (H-bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . . 20
Drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Open-load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Delay time from Standby to Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Inputs: DI, CSN, CLK, DIR and PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
H-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
H-bridge DS-monitor threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Cross-current protection time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DocID023145 Rev 2
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List of figures
L99DZ81EP
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
6/62
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TQFP-64 2 layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TQFP-64 4 layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TQFP-64 thermal impedance junction to ambient vs PCB copper area . . . . . . . . . . . . . . . 14
IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPI delay description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power-output (OUT<10:4>) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
H-bridge open-load detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
H-bridge open-load detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
H-bridge open-load detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
H-bridge open-load detection with H-OLTH HIGH = ‘1’ (short to VS detected) . . . . . . . . . 39
Write and read SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
TQFP-64 power lead-less tray shipment (no suffix) (part 1) . . . . . . . . . . . . . . . . . . . . . . . . 57
TQFP-64 power lead-less tray shipment (no suffix) (part 2) . . . . . . . . . . . . . . . . . . . . . . . . 58
TQFP-64 power lead-less tape and reel shipment (suffix “TR”) (part 1). . . . . . . . . . . . . . . 59
TQFP-64 power lead-less tape and reel shipment (suffix “TR”) (part 2). . . . . . . . . . . . . . . 60
DocID023145 Rev 2
L99DZ81EP
1
Block diagram and pin description
Block diagram and pin description
Figure 1. Block diagram
VBAT
~ 100nF
~ 100nF
> 10k
VS
CP2P
CP
CP2M
CP1P
~ 100nF
L99PM62
Charge
Pump
CP1M
150mΩ
GH1/2
>15
SH1/2
M
GL1/2
>15
>15
SL1/2
2x
FSO
SPI
adjustable
Slew
Rate
SPI
Fail Safe
Circuitry
VCC
PWMH
100
1k
1k
1k
1k
1k
SPC560D
1k
DIR
CSN
CLK
DI
DO
CM
150mΩ
OUT4
OUT5
300mΩ
OUT6
M
M
500 / 1600mΩ
10 Watt Bulb
OUT7
800 / 1600mΩ
OUT8
5 Watt Bulb
1600mΩ
OUT9
1600mΩ
OUT10
SPI Interface
TO Watchdog
1k
Driver Interface, Logic & Diagnostic
>15
Window
Watchdog
=> Fail Safe
CM
MUX
GND
GAPGCFT00674
Table 2. Pin definitions and functions
Pin
Symbol
Function
58
GND1
17, 18, 26, 31,
32
GND2
Ground: reference potential. GND1 and GND2 are internally
connected. GND2 supplies OUT4-6.
Important: For the capability of driving the full current at the outputs,
all pins of GND must be externally connected!
17, 57
SGND
Signal Ground: this pin is shared with GND2 pin.
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Block diagram and pin description
L99DZ81EP
Table 2. Pin definitions and functions (continued)
8/62
Pin
Symbol
Function
2, 46, 51, 52
VS1
11, 12, 23, 36,
37
VS2
19, 20, 21, 22
OUT4
27, 28, 29, 30
OUT5
24, 25
OUT6
40
DO
Serial data output: the diagnosis data is available via the SPI and this
3-state-output. The output remains in 3-state, if the chip is not
selected by the input CSN (CSN = high).
34
CM
Current monitor output: depending on the selected multiplexer bits of
the Control Register this output sources an image of the instant
current through the corresponding high side driver with a fixed ratio.
35
CSN
Chip-Select-Not input: this input is low active and requires CMOS
logic levels. The serial data transfer between the device and the
micro controller is enabled by pulling the input CSN to low level.
41
DI
Serial data input: the input requires CMOS logic levels and receives
serial data from the microcontroller. The data is a 24 bit control word
and the most significant bit (MSB, bit 23) is transferred first.
38
CLK
Serial clock input: this input controls the internal shift register of the
SPI and requires CMOS logic levels.
33
DIR
Direction Input: this input controls the H-Bridge Drivers.
39
VCC
Supply Voltage: 5 V supply. A ceramic capacitor as close as possible
to GND is recommended.
44
OUT9
High-side-driver output 9: the output is built by a high side switch and
is intended for resistive loads; hence the internal reverse diode from
GND to the output is missing. For ESD reason a diode to GND is
present but the energy which can be dissipated is limited. The highside driver is a power DMOS transistor with an internal parasitic
reverse diode from the output to VS (bulk-drain-diode). The output is
over current and open load protected.
42
PWMH
PWMH input: this input signal can be used to control the H-Bridge
Gate drivers.
3, 43, 45, 48,
49, 50, 53, 54,
55, 56, 59, 60
NC
62, 63
OUT7
61
OUT8
47
OUT10
Power supply voltage for power stage outputs (external reverse
protection required): for this input a ceramic capacitor as close as
possible to GND is recommended. VS1 supplies OUT7-10 and the
internal VS supply, VS2 supplies OUT4-6.
Important: For the capability of driving the full current at the outputs
all pins of VS must be externally connected!
Half-bridge outputs 4,5,6: the output is built by a high side and a low
side switch, which are internally connected. The output stage of both
switches is a power DMOS transistor. Each driver has an internal
parasitic reverse diode (bulk-drain-diode: high side driver from output
to VS, low side driver from GND to output). This output is over current
and open load protected.
Not connected.
High side driver output 8: see OUT9.
Important: This output can be configured to supply a bulb with low onresistance or a LED with higher on-resistance in a different
application.
High-side-driver-output 10: see OUT9.
DocID023145 Rev 2
L99DZ81EP
Block diagram and pin description
Table 2. Pin definitions and functions (continued)
Pin
Symbol
Function
13
GH2
GH2: gate driver for power MOS high side switch in half-bridge 2.
14
SH2
SH2: source of high-side switch in half-bridge 2.
15
GL2
GL2: gate driver for power MOS low side switch in half-bridge 2.
16
SL2
SL2: source of low side switch in half-bridge 2.
64
GH1
GH1: gate driver for power MOS high side switch in half-bridge 1.
1
SH1
SH1: source of high-side switch in half-bridge 1.
4
GL1
GL1: gate driver for power MOS low side switch in half-bridge 1.
5
SL1
SL1: source of low side switch in half-bridge 1.
7
CP1P
CP1P: charge pump pin for capacitor 1, positive side.
8
CP1M
CP1M: charge pump pin for capacitor 1, negative side.
9
CP2P
CP2P: charge pump pin for capacitor 2, positive side.
10
CP2M
CP2M: charge pump pin for capacitor 2, negative side.
6
CP
CP: charge pump output.
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61
Block diagram and pin description
L99DZ81EP
49
64
SH1
NC
NC
VS1
VS1
NC
NC
NC
NC
SGND
GND1
NC
NC
OUT8
OUT7
OUT7
GH1
Figure 2. Pin connection (top view)
1
48
NC
VS1
OUT10
NC
VS1
GL1
NC
SL1
OUT9
CP
NC
PWMH
CP1P
TQFP64
CP1M
CP2P
DI
DO
CP2M
VCC
VS2
CLK
VS2
VS2
GH2
VS2
SH2
CSN
GL2
CM
16
33
32
GND2
OUT5
OUT5
OUT5
OUT5
GND2
OUT6
OUT6
VS2
OUT4
OUT4
OUT4
GND2
OUT4
17
GND2/SGND
DIR
GND2
SL2
GAPGCFT00673
10/62
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Table 3. Absolute maximum ratings
Value
[DC Voltage]
Unit
DC supply voltage
-0.3 to +28
V
Single pulse / tmax < 400 ms “transient load dump”
-0.3 to +40
V
-0.3 to VS + 0.3
V
-0.3 to VCC + 0.3
V
-0.3 to VS + 0.3
V
-6 to 40
V
VSxy - 1 to VSxy + 10;
VCP + 0.3
V
Symbol
VS1, VS2
VCC
Parameter/test condition
Stabilized supply voltage, logic supply
VDI, VCLK, VCSN, VDO,
Logic input / output voltage range
VCM, VDIR, VPWMH, VDIR
VOUTn
VSL1, VSH1, VSL2, VSH2
(VSxy)
Output voltage (n = 4 to 10)
High voltage signal pins
VGL1, VGH1, VGL2, VGH2
High voltage signal pins
(VGxy)
VCP1P
High voltage signal pins
VS - 0.3 to VS + 10
V
VCP2P
High voltage signal pins
VS - 0.6 to VS + 10
V
VCP1M, VCP2M
High voltage signal pins
-0.3 to VS + 0.3
V
High voltage signal pin
VS1,2 26 V
VS - 0.3 to VS + 14
V
VCP
VS1,2 > 26 V
VS - 0.3 to +40
V
IOUT9,10
Output
current(1)
±1.25
A
Output
current(1) (low
±5
A
±5
A
±2.5
A
IOUT6,7
(1)
IOUT7
Output current
IOUT8
Output current(1)
IOUT4,5
IVS1cum
IVS2cum
Output
on-resistance mode)
(high on-resistance mode)
current(1)
Maximum cumulated input current at VS1
±10
A
pins(1)
±12.5
A
(1)
±12.5
A
±5
A
±12.5
A
Maximum cumulated input current at VS2 pins
IGND1cum
Maximum cumulated output current at GND1 pins(1)
IGND2cum
pins(1)
Maximum cumulated output current at GND2
1. Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power
dissipation or other limits.
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61
Electrical specifications
2.2
L99DZ81EP
ESD protection
Table 4. ESD protection
Parameter
All pins
Power output pins: OUT4 – OUT10
Value
Unit
±2(1)
kV
(1)
kV
±4
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2.3
Thermal data
Table 5. Operating junction temperature
Symbol
Tj
Parameter
Operating junction temperature
Value
Unit
-40 to 150
°C
Table 6. Temperature warning and thermal shutdown
Symbol
Parameter
Test condition
TjTW ON
Temperature warning threshold
(junction temperature)
TjTS ON
Thermal shutdown threshold
(junction temperature)
Tjtft
Thermal warning / shutdown
filter time
Min.
Typ.
Max.
Unit
130
150
°C
150
170
°C
32
µs
Table 7. Package thermal impedance
Symbol
Rthj-amb
12/62
Parameter
Thermal resistance junction to ambient (max)
DocID023145 Rev 2
Value
Unit
See Figure 5
K/W
L99DZ81EP
Electrical specifications
2.4
Package and PCB thermal data
2.4.1
TQFP-64 thermal data
Figure 3. TQFP-64 2 layer PCB
*$3*&)7
Figure 4. TQFP-64 4 layer PCB
*$3*&)7
Note:
Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10%,
board double layer and four layers, board dimension 77 mm x114 mm, board material FR4,
Cu thickness 0.070mm (outer layers), Cu thickness 0.035mm (inner layers), thermal vias
separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias
0.025 mm, footprint dimension 6 mm x 6 mm). 4-layer PCB: Cu on mid1 layer, Cu on mid2
layer and Cu on bottom layer: 62 cm2. Zth measured on the major power dissipator
contributor
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Electrical specifications
L99DZ81EP
Figure 5. TQFP-64 thermal impedance junction to ambient vs PCB copper area
14/62
DocID023145 Rev 2
L99DZ81EP
2.5
Electrical specifications
Electrical characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V  VS  18 V, 4.75 V  VCC  5.5 V; all outputs open;
Tj = -40 °C to 150 °C, unless otherwise specified.
Table 8. Supply
Symbol
Parameter
Test condition
Min.
Typ.
Unit
28
V
VS
Operating voltage range
IVS(act)
Current consumption in
active mode
VS = 13.5 V(1)
5
10
mA
Current consumption in
standby mode
VS = 16 V; VCC = 5.3 V;
standby mode;
OUT4 - OUT10 floating;
TTEST = -40 °C to 25 °C
4
12
µA
TTEST = 85 °C(1)
6
25
µA
5.5
V
IVS(stby)
VCC
5
Max.
Operating voltage range
4.5
IVCC(active) VCC supply current
IVCC(stby) VCC standby current
VS = 16 V; VCC = 5.3 V;
CSN = VCC; active mode;
OUT4 - OUT10 floating
5
10
mA
VS = 16 V; VCC = 5.0 V;
CSN = VCC; active mode;
OUT4 - OUT10 floating;
TTEST = -40 °C to 25 °C
3
6
µA
TTEST = 85 °C(1)
4
8
µA
25
µA
Max.
Unit
VS = 16 V; VCC = 5.3 V;
CSN = VCC; active mode;
OUT4 - OUT10 floating;
TTEST = -40 °C to 125 °C
1. This parameter is guaranteed by design
Table 9. Overvoltage and undervoltage detection
Symbol
VSUV ON
Parameter
VS UV threshold
Test condition
voltage(1)
VSUV OFF
VS UV threshold voltage
VSUV hyst
VS UV hysteresis(1)
tvsuvfilt
VSOV OFF
(1)
Min.
VS increasing
5.6
7.2
V
VS decreasing
5
5.9
V
VSUV ON-VSUV OFF
VS UV filter time
VS OV threshold voltage
voltage(1)
VSOV ON
VS OV threshold
VSOV hyst
VS OV hysteresis(1)
tvsovfilt
VS OV filter time
VVCCRESHU
Upper VCC reset
threshold(2)
(1)
Typ.
0.5
V
48
µs
VS increasing
18.5
24.5
V
VS decreasing
18.0
23.5
V
VSOV OFF-VSOV ON
VCC increasing
DocID023145 Rev 2
5.8
1
V
48
µs
7.5
V
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Electrical specifications
L99DZ81EP
Table 9. Overvoltage and undervoltage detection (continued)
Symbol
Parameter
Test condition
Min.
VVCCRESHD Upper VCC reset threshold VCC decreasing
VVCCRES
Typ.
5.5
Max.
Unit
7.1
V
Upper reset hysteresis
VVCCRESHU - VVCCRESHD
VPOROFF
Power-on-reset threshold
VCC increasing
3.4
4.4
V
VPORON
Power-on-reset threshold
VCC decreasing
3.1
4.1
V
hysth
VPOR hystL
0.1
Power-on-reset hysteresis VPOROFFL - VPORONL
V
0.3
V
1. VS = 5V to 28V
2. If VCC exceeds this value all registers are reset and the device enters standby mode.
Table 10. Current monitor output (CM)
Symbol
VCM
Parameter
Test condition
Functional voltage range
Min.
0
Current monitor output ratio:
ICM/IOUT4,5,6,7 (low on-resistance)
ICM r
ICM/IOUT8 (low on-resistance)
Typ.
Max.
Unit
VCC - 1 V
V
1/10000
0 V  VCM  VCC - 1 V
1/6500
ICM/IOUT7,8,9,10 and 7,8 (high on-
1/2000
resistance)
Current monitor accuracy
accICMOUT4,5,6 and 7(low on-resistance)
ICM acc
accICMOUT7,8,9,10(high on-resistance
tcmb
0 V  VCM  VCC - 1 V;
IOUTmin = 500 mA;
IOUT4,5max = 5.9 A;
IOUT6max = 2.9 A;
IOUT7max = 1.4 A
0 V  VCM  VCC - 1 V;
IOUT.min = 100 mA;
IOUT9,10max = 0.4A;
IOUT7max = 0.3 A;
IOUT8(low rdson)max = 0.6 A;
IOUT8(high rdson)max = 0.3 A
Current monitor blanking time
4%+
1 % FS
8%+
2 % FS
(1)
(1)
32
µs
1. FS (full scale) = IOUTmax * ICMr
Table 11. Charge pump
Symbol
16/62
Parameter
Test condition
Min.
Typ.
Max.
Unit
VS = 6 V; ICP = -10 mA
VS + 6
VS + 7
VS + 7.85
V
VS  10 V; ICP = -15 mA
VS + 11
VS + 12 VS + 13.5
V
VCP
Charge pump output
voltage
ICP
Charge pump output
current(1)
VCP = VS + 10 V;
VS = 13.5 V;
C1 = C2 = CCP = 100 nF
25
47
mA
ICPlim
Charge pump output
current limitation(2)
VCP = VS; VS = 13.5 V;
C1 = C2 = CCP = 100 nF
29
70
mA
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
Table 11. Charge pump (continued)
Symbol
VCP_low
TCP
Parameter
Test condition
Charge pump low
threshold voltage
Min.
Typ.
Max.
Unit
VS + 4.6
VS + 5
VS + 5.4
V
Charge pump low filter
time
64
µs
1. ICP is the minimum current the device can provide to an external circuit without VCP going below VS + 10 V
2. ICPlim is the maximum current, which flows out of the device in case of a short to VS
2.6
Outputs OUT4 - OUT10
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V  VS  18 V, 4.75 V  VCC  5.5 V; all outputs open;
Tj = -40°C to 150°C, unless otherwise specified.
Table 12. On-resistance
Symbol
rON OUT4,5
rON OUT6
Parameter
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply in
low resistance mode
rON OUT7
On-resistance to supply in
high resistance mode
On-resistance to supply in
low resistance mode
rON OUT8
On-resistance to supply in
high resistance mode
Test condition
Min.
Typ. Max. Unit
VS = 13.5 V; Tamb = +25 °C;
IOUT4,5 = ±3.0 A
150
200
m
VS = 13.5 V; Tamb = +125 °C;
IOUT4,5 = ±3.0 A
225
300
m
VS = 13.5 V; Tamb = +25 °C;
IOUT6 = ±1.5 A
300
400
m
VS = 13.5 V; Tamb = +125 °C;
IOUT6 = ±1.5 A
450
600
m
VS = 13.5 V; Tamb = +25 °C;
IOUT7 = -0.8 A
500
700
m
VS = 13.5 V; Tamb = +125 °C;
IOUT7 = -0.8 A
700
950
m
VS = 13.5 V; Tamb = +25 °C;
IOUT7 = -0.2 A
1600 2400 m
VS = 13.5 V; Tamb = +125 °C;
IOUT7 = -0.2 A
2500 3400 m
VS = 13.5 V; Tamb = +25 °C;
IOUT8 = -0.4 A
800 1200 m
VS = 13.5 V; Tamb = +125 °C;
IOUT8 = -0.4 A
1200 1700 m
VS = 13.5 V; Tamb = +25 °C;
IOUT8 = -0.2 A
1600 2400 m
VS = 13.5 V; Tamb = +125 °C;
IOUT8 = -0.2 A
2500 3400 m
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Electrical specifications
L99DZ81EP
Table 12. On-resistance (continued)
Symbol
rON OUT9,10
Parameter
On-resistance to supply
Test condition
Min.
Typ. Max. Unit
VS = 13.5 V; Tamb = +25 °C;
IOUT9,10 = -0.4 A
1600 2200 m
VS = 13.5 V; Tamb = +125 °C;
IOUT9,10 = -0.4 A
2500 3400 m
IQLH
Switched-off output current VOUT = 0 V; standby mode
high side drivers of
VOUT = 0 V; active mode
OUT4,6,9,10
IQLH7,8
Switched-off output current VOUT = 0 V; standby mode
high side drivers of OUT7,8 V
OUT = 0 V; active mode
IQLL
VOUT = VS; standby mode
Switched-off output current
low side drivers of OUT4-6 VOUT = VS - 0.5 V;
active mode
-5
-2
µA
-10.2
-7
µA
-5
-2
µA
-15
-10
µA
80
-10
165
-7
µA
µA
Table 13. Power outputs switching times
Symbol
Parameter
Test condition
Output delay time high side
driver on (all OUT except
OUT7,8)
td ON H
Output delay time high side
driver on (OUT7,8 in high
RDSON mode)
VS = 13.5 V; VCC = 5 V;
corresponding low side
driver is not active(1)(2)(3)
Output delay time high side
driver on (OUT7,8 in low RDSON
mode)
td OFF H
Output delay time high side
driver off (OUT4,5,6)
Output delay time high side
driver off (OUT7,8,9,10)
td ON L
Output delay time low side
driver on
td OFF L
Output delay time low side
driver (OUT4-6) off
td HL
td LH
Cross current protection time
(OUT4-6)
VS = 13.5 V;
VCC = 5 V(1)(2)(3)
VS = 13.5 V; VCC = 5 V;
corresponding low side
driver is not active(1)(2)(3)
VS = 13.5 V; VCC = 5 V
(1)(2)(3)
tcc ONLS_OFFHS – td OFF H(4)
tcc ONHS_OFFLS – td OFF L(4)
VS = 13.5 V;
VCC = 5 V(1)(2)(3)
Max
Unit
.
10
40
80
µs
15
35
60
µs
10
35
80
µs
50
150
300
µs
40
70
100
µs
15
30
70
µs
40
150
300
µs
40
200
400
µs
0.08
0.2
0.6
V/µs
dVOUT/dt
Slew rate of OUTx
fPWMx(low)
Low PWM switching frequency VS = 13.5 V; VCC = 5 V
122
Hz
fPWMx(high)
High PWM switching frequency VS = 13.5 V; VCC = 5 V
244
Hz
1. Rload = 16  at OUT6 and OUT7,8 in low on-resistance mode
18/62
Min. Typ.
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
2. Rload = 4  at OUT4,5
3. Rload = 64  at OUT9,10 and OUT7,8 in high on-resistance mode
4. tCC is the switch-on delay time if complement in half bridge has to switch off
Table 14. Current monitoring
Symbol
Max.
Unit
6
9.2
A
3
5.3
A
Overcurrent threshold to supply
in low on-resistance mode
1.5
2.5
A
Overcurrent threshold to supply
in high on-resistance mode
0.35
0.65
A
0.7
1.3
A
Overcurrent threshold to supply
in high on-resistance mode
0.35
0.65
A
|IOC9|,
|IOC10|
Overcurrent threshold to supply
0.5
1.0
A
tFOC
Filter time of overcurrent signal
100
µs
frec0
Recovery frequency for OC;
recovery frequency bit = 0
1
4
kHz
frec1
Recovery frequency for OC;
recovery frequency bit = 1
2
6
kHz
|IOC4|,
|IOC5|
Parameter
Overcurrent threshold to supply
or GND
|IOC6|
|IOC7|
Overcurrent threshold to supply
in low on-resistance mode
|IOC8|
|IOLD4|,
|IOLD5|
|IOLD6|
|IOLD7|
|IOLD8|
|IOLD9|,
|IOLD10|
tFOL
Test condition
VS = 13.5 V;
VCC = 5 V; sink and
source
VS = 13.5 V;
VCC = 5 V;
source
Duration of
overcurrent condition
to set the status bit
VS = 13.5 V;
Undercurrent threshold to supply
VCC = 5 V;
or GND
sink and source
Min.
10
Typ.
55
60
150
300
mA
8
30
80
mA
Undercurrent threshold to supply
in low on-resistance mode
15
40
60
mA
Undercurrent threshold to supply
in high on-resistance mode
5
10
15
mA
10
30
45
mA
5
10
15
mA
10
20
30
mA
0.5
2.0
3.0
ms
VS = 13.5 V;
Undercurrent threshold to supply
VCC = 5 V;
in low on-resistance mode
source
Undercurrent threshold to supply
in high on-resistance mode
Undercurrent threshold to supply
Filter time of open-load signal
Duration of openload condition to set
the status bit
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61
Electrical specifications
2.7
L99DZ81EP
H-bridge driver
Table 15. Gate drivers for the external Power-MOS (H-bridge)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Drivers for external high-side Power-MOS
IGHx(Ch)
RGHx
Average charge current
(charge stage)
On-resistance (dischargestage)
Tj = 25 °C
0.3
VSHx = 0 V; IGHx = 50 mA;
Tj = 25 °C
4
VSHx = 0 V; IGHx = 50 mA;
Tj = 125 °C
VGHxH
Gate-on voltage
Outputs floating
RGSHx
Passive gate-clamp
resistance
VGHx = 0.5 V
A
6
8

8
10

VSHx + VSHx + VSHx +
8
10
11.5
V
15
k
0.3
A
Drivers for external low-side Power-MOS
IGLx(Ch)
RGLx
Average charge-current
(charge stage)
On-resistance (dischargestage)
VGHLx
Gate-on voltage
RGSLx
Passive gate-clamp
resistance
Tj = 25 °C
VSLx = 0 V; IGHx = 50 mA;
Tj = 25 °C
4
VSLx = 0 V; IGHx = 50 mA;
Tj = 125 °C
Outputs floating
6
8

8
10

VSLx +
11.5
V
VSLx + VSLx +
8
10
15
k
Table 16. Gate drivers for the external Power-MOS switching times
Symbol
20/62
Parameter
Test condition
Min. Typ. Max.
Unit
TG(HL)xHL
Propagation delay time high to VS = 13.5 V; VSHx = 0;
low (switch mode)(1)
RG = 0 ; CG = 2.7 nF
1.5
µs
TG(HL)xLH
Propagation delay time low to
high (switch mode)(1)
VS = 13.5 V; VSLx = 0;
RG = 0 ; CG = 2.7 nF
1.5
µs
IGHxrmax
Maximum charge current
(current mode)
VS = 13.5 V; VSHx = 0;
VGHx = 1 V;
SLEW < 4:0  1 FH
24.5
31
38.5
mA
IGHxfmax
Maximum discharge current
(current mode)
VS = 13.5 V; VSHx = 0;
VGHx = 2 V;
SLEW < 4:0  1 FH
18.5
25
33
mA
dIIGHxr
Charge current accuracy
VS = 13.5 V; VSHx = 0;
VGHx = 1V
See Figure 6
dIIGHxf
Discharge current accuracy
VS = 13.5 V; VSHx = 0;
VGHx = 2 V
See Figure 7
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
Table 16. Gate drivers for the external Power-MOS switching times
Symbol
Parameter
Test condition
Switching Voltage (VS - VSH)
VDSHxrSW between current mode and
switch mode (rising)
VTDSHxf(2)
Trigger Voltage to sample the
VGSH for switching between
switch mode and current
mode (falling)
VTGSHxacc Sampled trigger voltage
(2)
accuracy
Min. Typ. Max.
Unit
VS = 13.5 V
1.5
V
VS = 13.5 V; VGHx = 4 V
1.5
V
VS = 13.5 V; VSHx = 0
1
V
t0GHxr
Rise time (switch mode)
VS = 13.5 V; VSHx = 0;
RG = 0 ; CG = 2.7 nF
45
ns
t0GHxf
Fall time (switch mode)
VS = 13.5 V; VSHx = 0;
RG = 0 ; CG = 2.7 nF
85
ns
t0GLxr
Rise time
VS = 13.5 V; VSLx = 0;
RG = 0 ; CG = 2.7 nF
45
ns
t0GLxf
Fall time
VS = 13.5 V; VSLx = 0;
RG = 0 ; CG = 2.7 nF
85
ns
tCCP
Programmable cross-current
protection time
fPWMH
VS = 13.5 V; VSLx = 0;
PWMH switching frequency(1) RG = 0 ; CG = 2.7 nF;
PWMH - duty cycle = 50 %
0.1
5
µs
50
kHz
1. Without cross-current protection time tCCP
2. Parameter not tested, typical value validated by characterization.
DocID023145 Rev 2
21/62
61
Electrical specifications
L99DZ81EP
Figure 6. IGHxr ranges
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Figure 7. IGHxf ranges
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DATAINPUT
'!0'#&4
22/62
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
Figure 8. H-driver delay times
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Table 17. Drain source monitoring
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSCd1
Drain-source threshold voltage
VS = 13.5 V
0.3
0.5
0.7
V
VSCd2
Drain-source threshold voltage
VS = 13.5 V
0.8
1
1.2
V
VSCd3
Drain-source threshold voltage
VS = 13.5 V
1.2
1.5
1.8
V
VSCd4
Drain-source threshold voltage
VS = 13.5 V
1.6
2
2.4
V
tSCd
Drain-source monitor filter time
3
5.5
8
µs
tscs
Drain-source comparator settling VS = 13.5 V; VSH = jump
time
from GND to VS
—
5
µs
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61
Electrical specifications
L99DZ81EP
Table 18. Open-load monitoring
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VODSL
Low-side drain-source monitor low
VSLx = 0 V; VS = 13.5 V
off-threshold voltage
0.14 * VS 0.18 * VS
0.21 * VS
V
VODSH
Low-side drain-source monitor
high off-threshold voltage
VSLx = 0 V; VS = 13.5 V
0.75 * VS 0.85 * VS
0.95 * VS
V
VOLSHx
Output voltage of selected SHx in
open-load test mode
VSLx = 0 V; VS = 13.5 V
0.5 * VS
V
RpdOL
Pull-down resistance of the nonselected SHx pin in open-load
mode
VSLx = 0 V; VS = 13.5 V;
VSHX = 4.5 V
20
k
2
ms
TOL
24/62
Open-load filter time
DocID023145 Rev 2
L99DZ81EP
2.8
Electrical specifications
SPI / logic – electrical characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V  VS  18 V, 4.75 V  VCC  5.5 V; all outputs open;
Tj = -40 °C to 150 °C, unless otherwise specified.
Table 19. Delay time from Standby to Active mode
Symbol
tset
twakup
tawake
Parameter
Test condition
Min
Typ
Max
Unit
Delay time
Switching time from standby to
active mode. Time until output
drivers are enabled after CSN
going to high and set bit 0 = 1 of
control register 0.
250
310
410
µs
Wake-up time
Switching from standby to active
mode. Time after the first falling
edge of CSN until the first
positive CLK edge, which latches
EN = 1 correctly into the device
—
20
µs
Stay awake time
Switching from standby to active
mode. After the first rising edge
of CSN a second SPI frame with
EN = 1 is correctly recognized
—
256
µs
Table 20. Inputs: DI, CSN, CLK, DIR and PWMH
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Inputs: CSN, CLK, DI, DIR, PWMH
VIL
Input voltage low level
VS = 13.5 V; VCC = 5.0 V
VIH
Input voltage high level
VS = 13.5 V; VCC = 5.0 V
Input hysteresis
VS = 13.5 V; VCC = 5.0 V
500
RCSN in
CSN pull-up resistor
VS = 13.5 V; VCC = 5.0 V;
0 V  VCSN  0.7 * VCC
60
110
215
k
RCLK in
CLK pull-down resistor
VS = 13.5 V; VCC = 5.0 V;
0.3 * VCC  VCLK  VCC
60
110
215
k
RDI in
DI pull-down resistor
VS = 13.5 V; VCC = 5.0 V;
0.3 * VCC  VDI  VCC
60
110
215
k
RDIR
DIR pull-down resistor
VS = 13.5 V; VCC = 5.0 V;
0.3 * VCC  VDIR  VCC
60
110
215
k
PWMH pull-down resistor
VS = 13.5 V; VCC = 5.0 V;
0.3 * VCC  VPWMH  VCC
60
110
215
k
0.3 * VCC
V
VIHYS
RPWMH
0.3 * VCC
V
0.7 * VCC
V
mV
Output: DO
VOL
Output voltage low level
IOL = 5 mA; VS = 13.5 V;
VCC = 5.0 V
VOH
Output voltage high level
IOH = -5 mA; VS = 13.5 V;
VCC = 5.0 V
IDOLK
3-state leakage current
VCSN = VCC; 0 < VDO < VCC
DocID023145 Rev 2
0.7 * VCC
-10
V
10
µA
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Electrical specifications
L99DZ81EP
Table 21. AC-Characteristics
Symbol
COUT(1)
CIN(1)
Parameter
Test condition
Min.
Typ.
Max.
Unit
Output capacitance
(DO)
—
—
10
pF
Input capacitance (DI,
CSN, CLK, DIR, PWMH)
—
—
10
pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
For definition of the parameters please see Figure 9, Figure 10 and Figure 11.
Table 22. Dynamic characteristics
Symbol
26/62
Parameter
Test condition
Min. Typ. Max. Unit
tCSNQVL
DO enable from 3-state to
low level
CDO = 100 pF; IDO = 1 mA;
pull-up load to VCC; VS = 13.5 V;
VCC = 5 V
100
250
ns
tCSNQVH
DO enable from 3-state to
high level
CDO = 100pF; IDO = -1 mA;
pull-down load to GND;
VS = 13.5 V; VCC = 5 V
100
250
ns
tCSNQTL
CDO = 100pF; IDO = 4 mA;
DO disable from low level to
pull-up load to VCC; VS = 13.5 V;
3-state
VCC = 5 V
380
450
ns
tCSNQTH
CDO = 100 pF; IDO = -4 mA;
DO disable from high level to
pull-down load to GND;
3-state
VS = 13.5 V; VCC = 5 V
380
450
ns
50
250
ns
tCLKQV
CLK falling until DO valid
VDO < 0.3 * VCC or
VDO > 0.7 * VCC; CDO = 100 pF;
VS = 13.5 V; VCC = 5 V
tSCSN
CSN setup time, CSN low
before rising edge of CLK
VS = 13.5 V; VCC = 5 V
400
ns
tSDI
DI setup time, DI stable
before rising edge of CLK
VS = 13.5 V; VCC = 5 V
200
ns
TCLK
Clock Period
VS = 13.5 V; VCC = 5 V
1000
ns
tHCLK
minimum CLK high time
VS = 13.5 V; VCC = 5 V
115
ns
tLCLK
minimum CLK low time
VS = 13.5 V; VCC = 5 V
115
ns
tHCSN
minimum CSN high time
VS = 13.5 V; VCC = 5 V
4
µs
tSCLK
CLK setup time before CSN
rising
VS = 13.5 V; VCC = 5 V
400
ns
tr DO
DO rise time
CDO = 100 pF; VS = 13.5 V;
VCC = 5 V
80
140
ns
tf DO
DO fall time
CDO = 100 pF; VS = 13.5 V;
VCC = 5 V
50
100
ns
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
Table 22. Dynamic characteristics (continued)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
tr in
rise time of input signal
DI, CLK, CSN
VS = 13.5 V; VCC = 5 V
100
ns
tf in
fall time of input signal
DI, CLK, CSN
VS = 13.5 V; VCC = 5 V
100
ns
Figure 9. SPI timing parameters
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DocID023145 Rev 2
27/62
61
Electrical specifications
L99DZ81EP
Figure 10. SPI input and output timing parameters
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28/62
DocID023145 Rev 2
L99DZ81EP
Electrical specifications
Table 23. Watchdog
Symbol
TCWDTO
Parameter
Test condition
Min.
Typ.
Max.
Unit
50
64
100
ms
Watchdog time out
Figure 12. Power-output (OUT<10:4>) timing
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DocID023145 Rev 2
29/62
61
Application information
L99DZ81EP
3
Application information
3.1
Dual power supply: VS and VCC
The power supply voltage VS supplies the power drivers and the Power-MOS gate drivers.
For supplying the high-side drivers for the power- and gate-driver outputs, an internal
charge-pump is used. The SPI interface and the logic circuitry is supplied by VCC.
Due to the independent VCC supply the control and status information are not lost, if there
are spikes or glitches on the power supply voltage.
3.2
Wake up and Active mode/standby mode
After power up of VS and VCC the device operates in standby-mode. Pulling the signal CSN
to low level wakes the device up and the analog part is activated (active mode). After at
least 10 µs, the first SPI communication is valid and the EN-bit can be used to set the ENmode.
The device can be set into active mode writing a ‘1’ into the EN-register. If the EN-register is
not set to ‘1’, the device goes back to standby mode typical 256 µs after the rising edge of
CSN and all latched data are cleared. In standby mode the current at VS (VCC) is less than
6 µA (5 µA) for CSN = high (DO in 3-state). It is recommended to switch all outputs off
before entering standby mode.
3.3
Charge pump
The charge pump uses two external capacitors, which are switched with a frequency of
typically 125 kHz. The output of the charge pump has a current limitation. In standby mode
and after a thermal shutdown has been triggered the charge pump is disabled. If the charge
pump output voltage remains too low for longer than TCP, the power-MOS outputs, the ECcontrol are switched off and the H-Bridge gate drivers are switched to resistive low. The
CP_LOW bit has to be cleared through a software reset to reactivate the drivers.
3.4
Diagnostic functions
All diagnostic functions (overcurrent, open-load, power supply overvoltage /undervoltage,
temperature warning and thermal shutdown) are internally filtered. The condition has to be
valid for at least the associated filter time before the corresponding status bit in the status
registers is set. The filters are used to improve the noise immunity of the device. The openload and temperature warning functions are intended for information purpose and do not
change the state of the output drivers. On contrary, the overcurrent condition disables the
corresponding driver and thermal shutdown disables all drivers. Without setting the
overcurrent recovery bits in the input data register, the microcontroller has to clear the
overcurrent status bits to reactivate the corresponding drivers.
30/62
DocID023145 Rev 2
L99DZ81EP
3.5
Application information
Overvoltage and undervoltage detection at VS
If the power supply voltage VS rises above the overvoltage threshold VSOV_OFF, the outputs
OUT4 to OUT10 are switched to high impedance state, the charge pump is disabled and the
H-Bridge gate drivers are switched into sink condition to protect the H-bridge and the load.
When the voltage VS drops below the undervoltage threshold VSUV_OFF (UV-switch-OFF
voltage), the output stages are switched to high impedance to avoid the operation of the
power devices without sufficient gate driving voltage (increased power dissipation). If the
supply voltage VS recovers to normal operating voltage, the charge pump is switched on
again, the CP_LOW bit is cleared and the output stages return to the programmed state. If
the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers
is deactivated.
If the undervoltage/overvoltage recovery disable bit (OV_UV_RD) is set, the microcontroller
needs to clear the status bits to reactivate the drivers. It is recommended to set OV_UV_RD
bit to avoid a possible high current oscillation in case of a shorted output to GND and low
battery voltage.
3.6
Overvoltage and undervoltage detection at VCC
At power-on (VCC increases from undervoltage to VPOROFF) the circuit is initialized by an
internally generated power-on-reset (POR). If the voltage VCC decreases below the low
threshold (VPORON), the outputs are switched to 3-state (high impedance) and the status
registers are cleared. If the voltage at pin VCC increases above the VCC reset high threshold
VVCCRESHU, the device enters the reset state, all outputs are switched off and all internal
registers are cleared. After the voltage at pin VCC has decreased below VVCCRESHL, the
device enters normal operating mode again and the internal registers are reset.
3.7
Temperature warning and shutdown
If the junction temperature rises above the temperature warning threshold (TjTW), a
temperature warning flag is set after the temperature warning filter time (Tjtft) and can be
read via SPI. If the junction temperature increases above the temperature shutdown
threshold (TjTS), the thermal shutdown bit is set and the power transistors of all output
stages are switched off to protect the device after the thermal shutdown filter time. The
gates of the H-Bridge are discharged by the ‘Resistive Low’ mode.
The temperature warning and thermal shutdown flags are latched and must be cleared by
the microcontroller. This is done by a read and clear command on an arbitrary register,
because both bits are part of the global status register.
After these bits have been cleared, the output stages are reactivated. If the temperature is
still above the thermal warning threshold, the thermal warning bit is set after Tjtft. Once this
bit is set and the temperature is above the temperature shutdown threshold, temperature
shutdown is detected after Tjtft and the outputs are switched off. Therefore the minimum
time after which the outputs are switched off after the bits have been cleared in case the
temperature is still above the thermo-shutdown threshold is twice the thermo-warning/shutdown filter time Tjtft.
DocID023145 Rev 2
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Application information
3.8
L99DZ81EP
Inductive loads
Each half bridge is built by internally connected high- and low-side power DMOS transistors.
Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at
the outputs OUT4 to OUT6 without external freewheeling diodes. The high-side drivers
OUT7 to OUT10 are intended to drive resistive loads. Therefore only a limited energy
(E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L > 100 µH) an external freewheeling diode connected between GND and
the corresponding output is required.
3.9
Open-load detection
The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least tFOL the corresponding openload bit is set in the status register. Due to mechanical/electrical inertia of typical loads a
short activation of the outputs (e.g. 3 ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.
3.10
Overcurrent detection
In case of an overcurrent condition, a flag is set in the status register. If the overcurrent
signal is valid for at least TFOC, the overcurrent flag is set and the corresponding driver is
switched off to reduce the power dissipation and to protect the integrated circuit. If the
overcurrent recovery bit of the output is cleared, the microcontroller has to clear the status
bits to reactivate the corresponding driver.
3.11
Current monitor
The current monitor output sources a current image at the current monitor output, which has
three fixed ratios of the instantaneous current of the selected high-side driver. Outputs with
a resistance of 500 mand higher have a ratio of 1/2000, except for OUT8, which has a
ratio of 1/6500, and those with a lower resistance one of 1/10000. The signal at output CM is
blanked after switching on the driver until correct settlement of the circuitry. The bits
CM_SEL<3:0> define which of the outputs are multiplexed to the current monitor output CM.
The current monitor output allows a more precise analysis of the actual state of the load
rather than the detection of an open- or overload condition. For example, it can be used to
detect the motor state (starting, free running, stalled). Moreover, it is possible to control the
power of the defroster more precisely by measuring the load current. The current monitor
output is enabled after the current-monitor blanking time, when the selected output is
switched on. If this output is off, the current monitor output is in high-impedance mode.
3.12
PWM mode of the power outputs
Each driver has a corresponding PWM enable bit, which can be programmed by the SPI
interface. If the PWM enable bit is set, the output is controlled by the logically ANDcombination of an internally generated PWM signal and the output control bit of the
corresponding driver. The PWM-Frequency of all outputs can be programmed to either
122 Hz of 244 Hz typically. The on-duty-cycle is set by the four 7-bit registers, which control
one PWM counter each. Therefore the maximum on-time is 100% - 1 LSB.
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Application information
1 LSB = 100/128 %. Which output uses which corresponding PWM driver can be seen in
the SPI register definition. When programming a specific duty-cycle, the output on/off times
as well as the slopes must be taken into account.
3.13
Cross-current protection
The six half-brides of the device are crosscurrent protected by an internal delay time. If one
driver (LS or HS) is turned off, the activation of the other driver of the same half bridge is
automatically delayed by the crosscurrent protection time. After the crosscurrent protection
time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turnoff phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior,
it is always guaranteed that the previously activated driver is completely turned off before
the opposite driver starts to conduct
3.14
Programmable soft-start function to drive loads with higher
inrush current
Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps,
Start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding overcurrent recovery bit. If this bit is set, the device automatically switches
the outputs on again after a programmable recovery time. The duty cycle in overcurrent
condition can be programmed by the SPI interface to about 12 % or 25 %. The PWM
modulated current provides sufficient average current to power up the load (e.g. heat up the
bulb) until the load reaches operating condition. The PWM frequency settles at 1.7 kHz and
3 kHz. The device itself cannot distinguish between a real overload and a non linear load
like a light bulb. A real overload condition can only be qualified by time. For overload
detection the microcontroller can switch on the light bulbs by setting the overcurrent
recovery bit for the first e.g. 50 ms. After clearing the recovery bit the output is automatically
switched off, if the overload condition remains. This overcurrent detection procedure has to
be followed in order to make it possible to switch on the low side driver of a bridge output, if
the associated high-side driver has been used in recovery mode before.
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Application information
L99DZ81EP
Figure 13. Overcurrent recovery mode
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3.15
H-bridge control (DIR, PWMH, bits SD, SDS)
The PWMH input controls the drivers of the external H-bridge transistors. The motor
direction can be chosen with the direction input (DIR), the duty cycle and frequency with the
PWMH input. With the SPI-registers SD and SDS four different slow-decay modes (via
drivers and via diode) can be selected using the high side or the low side transistors.
Unconnected inputs are defined by internal pull-down current.
Table 24. H-bridge control truth table
Control
pins
Control bits
Output pin
PWMH
HEN
SD
SDS
CP_LOW
OV
UV
DS
TSD
GH1
GL1
GH2
GL2
Comment
DIR
N°
Failure bits
1
X
X
0
X
X
X
X
X
X
X
RL
RL
RL
RL H-bridge disabled
2
X
X
1
X
X
1
0
0
0
0
RL
RL
RL
RL Charge pump voltage too low
3
X
X
1
X
X
0
X
X
X
1
RL
RL
RL
RL Thermo-shutdown
4
X
X
1
X
X
0
1
0
0
0
L
L
L
L
Overvoltage
(1)
(1)
(1)
(1)
Short-circuit(1)
L
L
X
X
1
X
X
0
0
0
1
0
6
0
1
1
X
X
0
0
0
0
0
L
H
H
L
Bridge H2/L1 on
7
X
0
1
0
0
0
0
0
0
0
L
H
L
H
Slow-decay mode LS1 and LS2 on
8
0
0
1
0
1
0
0
0
0
0
L
H
L
L
Slow-decay mode LS1 on
34/62
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L
5
DocID023145 Rev 2
L99DZ81EP
Application information
Table 24. H-bridge control truth table (continued)
Control
pins
Control bits
Output pin
PWMH
HEN
SD
SDS
CP_LOW
OV
UV
DS
TSD
GH1
GL1
GH2
GL2
Comment
DIR
N°
Failure bits
9
1
0
1
0
1
0
0
0
0
0
L
L
L
H
Slow-decay mode LS2 on
10
1
1
1
X
X
0
0
0
0
0
H
L
L
H
Bridge H1/L2 on
11
X
0
1
1
0
0
0
0
0
0
H
L
H
L
Slow-decay mode HS1 and HS2
on
12
0
0
1
1
1
0
0
0
0
0
L
L
H
L
Slow-decay mode HS2 on
13
1
0
1
1
1
0
0
0
0
0
H
L
L
L
Slow-decay mode HS1 on
1. Only the half-bridge (low and high-side), in which one MOSFET is in short circuit condition is switched off. Both MOSFETs
of the other half-bridge remain active and driven by DIR and PWMH
3.16
H-bridge driver slew-rate control
The rising and falling slope of the drivers for the external high-side Power-MOS can be slew
rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is
driven by a current source instead of a low-impedance output driver switch as long as the
drain-source voltage over this Power-MOS is below the switch threshold. The current is
programmed using the bits SLEW<4:0>, which represent a binary number. This number is
multiplied by the minimum current step. This minimum current step is the maximum source/sink-current (IGHxrmax / IGHxfmax) divided by 31. Programming SLEW<4:0> to 0 disables the
slew rate control and the output is driven by the low-impedance output driver switch.
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Application information
L99DZ81EP
Figure 14. H-bridge GSHx slope
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3.17
Resistive low
The resistive output mode protects the L99DZ81EP and the H-bridge in the standby mode
and in some failure modes (thermal shut down (TSD), charge pump low (CP_LOW) and
stuck-at-‘1’ at pin DI). When a gate driver changes into the resistive output mode due to a
failure a sequence is started. In this sequence the concerning driver is switched into sink
condition for 32 µs to 64 µs to ensure a fast switch-off of the H-bridge transistor. If slew rate
control is enabled, the sink condition is slew-rate controlled. Afterwards the driver is
switched into the resistive output mode (resistive path to source).
3.18
Short circuit detection/drain source monitoring
The drain source voltage of each activated external MOSFET of the H-bridge is monitored
by comparators to detect shorts to ground or battery. If the voltage-drop over the external
MOSFET exceeds the threshold voltage VSCd for longer than the short current detection
time tSCd the corresponding gate driver switches the external MOSFET off and the
corresponding drain source monitoring flag (DS_MON[3:0]) is set. The DS_MON bits have
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L99DZ81EP
Application information
to be cleared through the SPI to reactivate the gate drivers. The drain source monitoring has
a filter time of typ. 6 µs. This monitoring is only active while the corresponding gate driver is
activated. If a drain-source monitor event is detected, the corresponding gate-driver remains
activated for at maximum the filter time. When the gate driver switches on, the drain-source
comparator requires the specified settling time until the drain-source monitoring is valid.
During this time, this drain-source monitor event may start the filter time. The threshold
voltage VSCd can be programmed using the SPI.
Table 25. H-bridge DS-monitor threshold
DIAG<1>
DIAG<0>
Monitoring threshold voltage (typical)
0
0
VSCD1 = 0.5 V
0
1
VSCD2 = 1.0 V
1
0
VSCD3 = 1.5 V
1
1
VSCD4 = 2.0 V
Figure 15. H-bridge diagnosis
9V
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3.19
H-bridge monitoring in off-mode
The drain source voltages of the H-Bridge driver external transistors can be monitored,
while the transistors are switched off. If either bit OL_H1L2 or OL_H2L1 is set to ‘1’, while bit
HEN = ‘1’, the H-drivers enter resistive low mode and the drain-source voltages can be
monitored. Since the pull-up resistance is equal to the pull-down resistance on both sides of
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61
Application information
L99DZ81EP
the bridge a voltage of 2/3 VS on the pull-up high-side and 1/3 VS on the low side is
expected, if they drive a low-resistive inductive load (e.g. motor). If the drain source voltage
on each of these Power-MOS is less than 1/6 VS, the drain-source monitor bit of the
associated driver is set.
In case of a short to ground the drain-source monitor bits of both low-side gate drivers are
set. A short to VS can be diagnosed by setting the “H-Bridge OL high threshold (H-OLTH
HIGH)” bit to one.
Figure 16. H-bridge open-load detection (no open-load detected)
9V
N
9V
9V
0
P
'60 N
N
97 9V
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Figure 17. H-bridge open-load detection (open-load detected)
9V
N
0
9V
2SHQ
P
'60 97 9V
N
N
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L99DZ81EP
Application information
Figure 18. H-bridge open-load detection (short to ground detected)
9V
N
*1'
0
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P
'60 N
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Figure 19. H-bridge open-load detection with H-OLTH HIGH = ‘1’ (short to VS detected)
9V
6KRUW
N
9V
9V
0
P
'60 N
97 9V
'60 N
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3.20
Programmable cross current protection
Both external MOSFET transistors in one half-bridge are disabled for the cross-current
protection time (tCCP) after one MOSFET inside this halfbridge is switched off to prevent
current flowing from the high-side to the low-side MOSFET.
The cross current protection time tCCP can be programmed by SPI using bits COPT<3:0>.
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Application information
L99DZ81EP
Table 26. Cross-current protection time
3.21
COPT<3>
COPT<2>
COPT<1>
COPT<0>
Min
Typ
Max
unit
0
0
0
0
150
250
360
ns
0
0
0
1
390
500
670
ns
0
0
1
0
590
750
980
ns
0
0
1
1
800
1000
1280
ns
0
1
0
0
1000
1250
1600
ns
0
1
0
1
1210
1500
1910
ns
0
1
1
0
1420
1750
2220
ns
0
1
1
1
1630
2000
2540
ns
1
0
0
0
1830
2250
2850
ns
1
0
0
1
2050
2500
3120
ns
1
0
1
0
2250
2750
3450
ns
1
0
1
1
2460
3000
3760
ns
1
1
0
0
2660
3250
4100
ns
1
1
0
1
2880
3500
4370
ns
1
1
1
0
3080
3750
4680
ns
1
1
1
1
3200
4000
5000
ns
Watchdog
The watchdog monitors the µC during normal operation within a nominal trigger cycle of
60ms. The watchdog is triggered by toggling the watchdog bit, which restarts the watchdog
timer (i.e. content of the watchdog trigger bit has to be inverted). If no watchdog bit inversion
has been occurred during the watchdog time-out time TWDTO the H-bridge drivers switch
into resistive-low condition, all power outputs are switched off.
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Functional description of the SPI
4
Functional description of the SPI
4.1
General description
The SPI complies with Standard ST-SPI Interface Version 3.1.
Its communication is based on a Serial Peripheral Interface structure using CSN (Chip
Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial Clock) signal
lines.
4.1.1
Chip Select Not (CSN)
The CSN input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal wakes up the device and a serial
communication can be started. The state when CSN is going low until the rising edge of
CSN is called a communication frame.
4.1.2
Serial Data In (DI)
The DI input pin is used to transfer data serially into the device. The data applied to the DI is
sampled at the rising edge of the CLK signal. A stuck-at ‘0’ or ‘1’ enters the standby mode.
4.1.3
Serial Clock (CLK)
The CLK input signal provides the timing of the serial interface. The Data Input (DI) is
latched at the rising edge of Serial Clock CLK. The SPI can be driven by a micro controller
with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial
Data Out (DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock
CLK must be active only during a frame (CSN low). Any other switching of CLK close to any
CSN edge could generate set up/hold violations in the SPI logic of the device. The clock
monitor counts the number of clock pulses during a communication frame (while CSN is
low). If the number of CLK pulses does not correspond to the frame width indicated in the
<SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in the
<Global Status Byte> is set.
Note:
Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.1.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and goes from high
impedance to a low or high level depending on the global status bit 7 (Global Error Flag).
The content of the selected status or control register is transferred into the data out shift
register after the address bits have been transmitted. Each subsequent falling edge of the
CLK shifts the next bit out.
4.1.5
SPI communication flow
At the beginning of each communication the master can read the contents of the
<SPIframe-ID> register (ROM address 03H) of the slave device.
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Functional description of the SPI
L99DZ81EP
This 8-bit register indicates the SPI frame length (24 bit) and the availability of additional
features. Each communication frame consists of a command byte, which is followed by two
data bytes.
The data returned on DO within the same frame always starts with the <Global Status>
Byte. It provides general status information about the device. It is followed by two data bytes
(i. e. ‘In-frame-response’).
For write cycles the <Global Status> Byte is followed by the previous content of the
addressed register.
Figure 20. Write and read SPI
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L99DZ81EP
4.2
Functional description of the SPI
Command byte
Table 27. Command byte
Command byte
Bit
23
22
Data byte 1
21 20 19 18 17 16 15
14
13
12
11
Data byte 2
10
9
8
7
6
5
4
3
2
1
0
Name OC1 OC0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OCx: operation code
Ax: address
Dx: data bit
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Read>, <Write>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 bits are required, the remaining bits are
unused but are reserved.
4.2.1
Operation code definition
Table 28. Operation code definition
OC1
OC0
Meaning
0
0
<Write Mode>
0
1
<Read Mode>
1
0
<Read and Clear Mode>
1
1
<Read Device Information>
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.
A <Read and Clear Mode> operation is used to read a status register and subsequently
clear its content.
The <Read Device Information> allows access to the ROM area which contains device
related information such as <ID-Header>, <Product Code>, <Silicon Version> and <SPIframe-ID>.
4.3
Device memory map
Table 29. RAM memory map
Address
Name
Access
Content
00h
Control Register 0
Read/write
Device enable, output bridge and H-bridge open-load
control
01h
Control Register 1
Read/write High-side/ low-side
02h
Control Register 2
Read/write Bridge recovery mode, PWM
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Functional description of the SPI
L99DZ81EP
Table 29. RAM memory map (continued)
Address
Name
Access
Content
03h
Control Register 3
Read/write
04h
Control Register 4
Read/write H-bridge driver control
05h
Control Register 5
Read/write PWM register
06h
Control Register 6
Read/write PWM register
10h
Status Register 0
Read/clear
11h
Status Register 1
Read/clear Output bridge and H-bridge open-load diagnosis
12h
Status Register 2
Read/clear High-side overcurrent/open-load
13h
Status Register 3
Read/clear VS and chargepump diagnosis
3Fh
Configuration Reg.
Read/write Mask bits in global status register
High-side recovery mode, PWM setup and currentmonitor selection
Output bridge overcurrent and H-bridge drain-source
diagnosis
Table 30. ROM memory map
Address
44/62
Name
Access
Content
00h
ID Header
Read only
4300h (ASSP ST_SPI)
01h
Version
Read only
0200h
02h
Product Code 1
Read only
0100h (01 ST_SPI)
03h
Product Code 2
Read only
5500h (U ST_SPI)
3Eh
SPI-Frame ID.
Read only
4200h SPI-Frame-ID (ST_SPI)
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L99DZ81EP
5
SPI - control and status registers
SPI - control and status registers
Table 31. Global status byte
Bit
7
6
5
4
3
2
1
0
Name
GL_ER
CO_ER
C_RESET
TSD
TW
UOV_OC_DS
OL
NR
Reset
0
0
1
0
0
0
0
0
GL_ER:
Global Error Flag.
Failures of bits 6 to 0 are always linked to the Global Error Flag. This flag is
set, if at least one of these bits indicates a failure. It is reflected via the DO
pin while CSN is held low and no SPI clock signal is applied. This operation
does not cause the Communication Error bit in the <Global Status> to be
set. The signal TW bit3 and OL bit1can be masked.
CO_ER:
Communication Error.
If the number of clock pulses during the previous frame is not 24, the frame
is ignored and this bit is set.
C_RESET:
Chip RESET.
If a stuck at ‘1’ on input DI during any SPI frame occurs, or if a Power On
Reset (VCC monitor) occurs. C_RESET is reset (‘1’) with any SPI command.
When C_RESET is active (‘0’), the gate drivers are switched off (resistive
path to source). After a startup of the circuit C_RESET is active due to the
power-up reset pulse. Therefore, the gate drivers are switched off. They can
only be activated after the C_RESET has been reset by an SPI command.
TSD:
Thermal shutdown.
All gate drivers and the charge pump are switched off (resistive path to
source). The TSD bit has to be cleared through a read and clear command
to reactivate the gate drivers and the chargepump.
TW:
Thermal Warning.
This bit can be masked using the configuration register.
UOV_OC_DS: Logical OR of the filtered undervoltage/overvoltage, chargepump-low,
overcurrent of the power outputs and the H-bridge drain-source monitor
signals.
OL:
Open-load.
Logical OR of the filtered output driver open-load signals. This bit can be
masked using the configuration register.
NR:
Not Ready.
After switching the device from standby mode to active mode an internal
timer is started to allow the chargepump to settle before the outputs can be
activated. This bit is cleared automatically after the startup time.
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SPI - control and status registers
5.1
L99DZ81EP
Control Register 0
Table 32. Control Register 0
Bit
Name
Access
Reset
15
0
—
0
14
0
—
0
13
0
—
0
12
0
—
0
11
0
—
0
10
0
—
0
9
OUT4_HS on/off
Read/write
0
8
OUT4_LS on/off
Read/write
0
7
OUT5_HS on/off
Read/write
0
6
OUT5_LS on/off
Read/write
0
5
OUT6_HS on/off
Read/write
0
4
OUT6_LS on/off
Read/write
0
3
0
—
0
2
0
—
0
1
0
—
0
0
EN
Read/write
0
Content
Reserved (must be set to ‘0’)
5.2
The corresponding output driver is activated, if this bit is set.
Setting the PWM enable bit, the driver is only switched on, if the
PWM timer enables it. An internal cross-current protection
prevents, that both the low- and high-side of the half-bridges
OUT4-OUT6 are switched on simultaneously.
Reserved (must be set to ‘0’)
The device is switched into active mode, if EN is ‘1’. It enters the
standby mode, if the EN bit is ‘0’. In standby mode all bits are
reset.
Control Register 1
Table 33. Control Register 1
Bit
Name
Access
Reset
15
OUT7_HS1 on/off
Read/write
0
14
OUT7_HS2 on/off
Read/write
0
13
OUT8_HS1 on/off
Read/write
0
12
OUT8_HS2 on/off
Read/write
0
11
OUT9_HS on/off
Read/write
0
10
OUT10_HS on/off
Read/write
0
9
0
—
0
8
0
—
0
Content
HS1
HS2
Mode
0
0
Off
0
1
Low on-resistance
1
0
High on-resistance
1
1
Off
The corresponding output driver is activated, if this bit is set.
Setting the PWM enable bit, the driver is only switched on, if
the PWM timer enables it.
Reserved (must be set to ‘0’)
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SPI - control and status registers
Table 33. Control Register 1 (continued)
Bit
Name
Access
Reset
7
0
—
0
6
0
—
0
5
0
—
0
4
0
—
0
3
0
—
0
2
0
—
0
1
0
—
0
0
0
—
0
Content
Reserved (must be set to ‘0’)
5.3
Control Register 2
Table 34. Control Register 2
Bit
Name
Access
Reset
15
0
—
0
14
0
—
0
13
0
—
0
12
OUT4_OCR
Read/write
0
11
OUT5_OCR
Read/write
0
10
OUT6_OCR
Read/write
0
9
0
—
0
8
0
—
0
7
0
—
0
6
0
—
0
5
0
—
0
4
OUT4_PWM1
Read/write
0
3
OUT5_PWM2
Read/write
0
2
OUT6_PWM3
Read/write
0
1
0
—
0
0
0
—
0
Content
Reserved (must be set to ‘0’)
Setting this bit to high enables the overcurrent recovery mode for
the corresponding output.
Reserved (must be set to ‘0’)
Setting this bit to ‘1’ enables the PWM mode for the
corresponding output.
Reserved (must be set to ‘0’)
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SPI - control and status registers
5.4
L99DZ81EP
Control Register 3
Table 35. Control Register 3
Bit
Name
Access
Reset
15
OUT7_OCR
Read/write
0
14
OUT8_OCR
Read/write
0
13
OUT9_OCR
Read/write
0
12
OUT10_OCR
Read/write
0
11
0
—
0
10
OUT7_PWM1
Read/write
0
9
OUT8_PWM2
Read/write
0
8
OUT9_PWM3
Read/write
0
7
OUT10_PWM4
Read/write
0
6
0
—
0
Reserved (must be set to ‘0’)
5
OCR_FREQ
Read/write
0
This bit defines the overcurrent recovery frequency (0: 1.7kHz
(typ.) 1: 3kHz (typ.))
4
OV_UV_RD
Read/write
0
If this bit is set, the associated status bit has to be cleared after
an overvoltage /undervoltage event to enable the output drivers
again.
3
CM_SEL<3>
Read/write
0
2
CM_SEL<2>
Read/write
0
1
0
48/62
CM_SEL<1>
CM_SEL<0>
Read/write
Read/write
0
0
Content
Setting this bit to high enables the overcurrent recovery mode
for the corresponding output.
Reserved (must be set to ‘0’)
Setting this bit to ‘1’ enables the PWM mode for the
corresponding output.
A current image of the selected binary coded output is
multiplexed to the CM output. If a corresponding output does not
exist, the current monitor is deactivated (especially ‘0000’).
CM_SEL<3:0>
Selected output
0000
3-state
0001
Reserved
0010
Reserved
0011
Reserved
0100
OUT<4>
0101
OUT<5>
0110
OUT<6>
0111
OUT<7>
1000
OUT<8>
1001
OUT<9>
1010
OUT<10>
1011
Reserved
1100
Reserved
1101-1111
3-state
DocID023145 Rev 2
L99DZ81EP
5.5
SPI - control and status registers
Control Register 4
Table 36. Control Register 4
Bit
Name
Access
Reset
Content
15
SLEW<4>
Read/write
0
14
SLEW<3>
Read/write
0
13
SLEW<2>
Read/write
0
12
SLEW<1>
Read/write
0
11
SLEW<0>
Read/write
0
10
H-OLTH
HIGH
Read/write
0
H-bridge OL high threshold (5/6 * VS) select
9
OL_H1L2
Read/write
0
Test open-load condition between H1 and L2
8
OL_H2L1
Read/write
0
Test open-load condition between H2 and L1
7
SD
Read/write
0
Slow decay
6
SDS
Read/write
0
Slow decay single
5
COPT<3>
Read/write
1
4
COPT<2>
Read/write
1
3
COPT<1>
Read/write
1
2
COPT<0>
Read/write
1
1
DIAG<1>
Read/write
0
0
DIAG<0>
Read/write
0
Binary coded Slew Rate Current of the H-Bridge
Cross-current protection time (default 4000ns)
Drain-source monitoring threshold voltage
5.6
Control Register 5
Table 37. Control Register 5
Bit
Name
Access
Reset
15
0
—
0
14
PWM2<6>
Read/write
0
13
PWM2<5>
Read/write
0
12
PWM2<4>
Read/write
0
11
PWM2<3>
Read/write
0
10
PWM2<2>
Read/write
0
9
PWM2<1>
Read/write
0
8
PWM2<0>
Read/write
0
7
PWMFREQ
Read/write
0
Content
Reserved (must be set to ‘0’)
Binary coded PWM2 on-duty-cycle
PWM-frequency (0: 122 Hz or 1: 244 Hz)
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SPI - control and status registers
L99DZ81EP
Table 37. Control Register 5 (continued)
Bit
Name
Access
Reset
6
PWM1<6>
Read/write
0
5
PWM1<5>
Read/write
0
4
PWM1<4>
Read/write
0
3
PWM1<3>
Read/write
0
2
PWM1<2>
Read/write
0
1
PWM1<1>
Read/write
0
0
PWM1<0>
Read/write
0
5.7
Content
Binary coded PWM1 on-duty-cycle
Control Register 6
Table 38. Control Register 6
Bit
Name
Access
Reset
15
0
—
0
14
PWM4<6>
Read/write
0
13
PWM4<5>
Read/write
0
12
PWM4<4>
Read/write
0
11
PWM4<3>
Read/write
0
10
PWM4<2>
Read/write
0
9
PWM4<1>
Read/write
0
8
PWM4<0>
Read/write
0
7
0
—
0
6
PWM3<6>
Read/write
0
5
PWM3<5>
Read/write
0
4
PWM3<4>
Read/write
0
3
PWM3<3>
Read/write
0
2
PWM3<2>
Read/write
0
1
PWM3<1>
Read/write
0
0
PWM3<0>
Read/write
0
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Reserved (must be set to ‘0’)
Binary coded PWM4 on-duty-cycle
Reserved (must be set to ‘0’)
Binary coded PWM3 on-duty-cycle
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5.8
SPI - control and status registers
Configuration Register
Table 39. Configuration Register
Bit
Name
Access
Reset
Content
15
0
—
0
14
0
—
0
13
0
—
0
12
0
—
0
11
0
—
0
10
0
—
0
9
0
—
0
8
0
—
0
7
0
—
0
6
HEN
Read/write
0
5
0
—
0
4
0
—
0
3
MASK TW
Read/write
0
Masks thermo warning to global status register
2
0
—
0
Reserved (must be set to ‘0’)
1
MASK OL
Read/write
0
Masks all open-load diagnosis to global status register
0
WD
Read/write
0
Watchdog
Reserved (must be set to ‘0’)
A ‘1’ enables the H-bridge
Reserved (must be set to ‘0’)
5.9
Status Register 0
Table 40. Status Register 0
Bit
Name
Access
15
0
Read
14
0
Read
13
0
Read
12
0
Read
11
0
Read
10
0
Read
9
OUT4_HS OC
Read/clear
8
OUT4_LS OC
Read/clear
7
OUT5_HS OC
Read/clear
6
OUT5_LS OC
Read/clear
5
OUT6_HS OC
Read/clear
4
OUT6_LS OC
Read/clear
Content
Reserved
Overcurrent status bit of the corresponding output driver. A ‘1’ indicates
that an overcurrent has occurred.
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Table 40. Status Register 0 (continued)
Bit
Name
Access
3
DS_MON_HS<2>
Read/clear
2
DS_MON_HS<1>
Read/clear
1
DS_MON_LS<2>
Read/clear
0
DS_MON_LS<1>
Read/clear
5.10
Content
DS-Monitoring bit. A ‘1’ indicates that a drain-monitoring event (shortcircuit or open-load) has occurred.
Status Register 1
Table 41. Status Register 1
Bit
Name
Access
15
0
Read
14
0
Read
13
0
Read
12
0
Read
11
0
Read
10
0
Read
9
OUT4_HS OL
Read/clear
8
OUT4_LS OL
Read/clear
7
OUT5_HS_OL
Read/clear
6
OUT5_LS OL
Read/clear
5
OUT6_HS OL
Read/clear
4
OUT6_LS OL
Read/clear
3
0
Read
2
0
Read
1
0
Read
0
0
Read
Content
Reserved
Open-Load status bit of the corresponding output driver. A ‘1’ indicates
that an open-load event has occurred.
Reserved
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5.11
SPI - control and status registers
Status Register 2
Table 42. Status Register 2
Bit
Name
Access
Content
15
OUT7 OC
Read/clear
14
OUT7 OL
Read/clear
13
OUT8 OC
Read/clear
12
OUT8 OL
Read/clear
11
OUT9 OC
Read/clear
10
OUT9 OL
Read/clear
9
OUT10 OC
Read/clear
8
OUT10 OL
Read/clear
7
0
Read
6
0
Read
5
0
Read
4
0
Read
3
VS UV
Read/clear
2
VS OV
Read/clear
1
0
Read
0
0
Read
Overcurrent and open-load status bit of the corresponding output driver
Reserved
VS undervoltage and overvoltage status bit.
Reserved
5.12
Status Register 3
Table 43. Status Register 3
Bit
Name
Access
15
0
Read
14
0
Read
13
0
Read
12
0
Read
11
0
Read
10
0
Read
9
0
Read
8
0
Read
7
0
Read
6
0
Read
Content
Reserved
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Table 43. Status Register 3 (continued)
Bit
Name
Access
5
0
Read
4
0
Read
3
0
Read
2
0
Read
1
0
Read
0
CP LOW
Read/clear
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Reserved
This bit indicates, that the charge pump voltage is too low
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Package and packing information
6
Package and packing information
6.1
ECOPACK® package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.2
TQFP-64 mechanical data
Table 44. TQFP-64 mechanical data
Millimeters
Symbol
Min.
Typ.
A
Max.
1,20
A1
0,05
A2
0,95
1,00
1,05
b
0,17
0,22
0,27
c
0,09
D
11,80
12,00
12,20
D1
9,80
10,00
10,20
D2(1)
5,85
6,00
6,15
D3
0,15
0,20
7,50
E
11,80
12,00
12,20
E1
9,80
10,00
10,20
5,85
6,00
6,15
(1)
E2
E3
7,50
e
0,50
L
0,45
L1
k
0,60
0,75
1,00
0°
ccc
3,50°
7°
0,08
1. The size of exposed pads is variable depending on lead frame design and pad size end user should verify
"D2" and "E2" dimensions for each device application
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Figure 21. TQFP-64 package dimension
*$3*&)7
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6.3
Package and packing information
TQFP-64 packing information
The devices can be packed in tray or tape and reel shipments (see the Figure 1: Device
summary on page 1 for packaging quantities).
Figure 22. TQFP-64 power lead-less tray shipment (no suffix) (part 1)
*$3*&)7
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Figure 23. TQFP-64 power lead-less tray shipment (no suffix) (part 2)
*$3*&)7
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Package and packing information
Figure 24. TQFP-64 power lead-less tape and reel shipment (suffix “TR”) (part 1)
$
%
.
)
3
:
*$3*&)7
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Package and packing information
L99DZ81EP
Figure 25. TQFP-64 power lead-less tape and reel shipment (suffix “TR”) (part 2)
'LPHQVLRQOLVW
$QQRWH
0LOLPHWHU
$QQRWH
0LOLPHWHU
$
.
$
3
$
3
%
3
%
3
%
(
'
)
'
7
.
:
.
*$3*&)7
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7
Revision history
Revision history
Table 45. Document revision history
Date
Revision
Change
12-Jun-2013
1
Initial release.
19-Sep-2013
2
Updated Disclaimer.
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