STMicroelectronics LNBH26 Datasheet

LNBH26

Dual LNBS supply and control IC with step-up and I²C interface

Features

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Complete interface between LNB and I²C bus

Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @

0.5 A)

Selectable output current limit by external resistor

Compliant with main satellite receivers output voltage specification (15 programmable levels)

Accurate built-in 22 kHz tone generator suits widely accepted standards

22 kHz tone waveform integrity guaranteed also at no load condition

Low drop post regulator and high efficiency step-up PWM with integrated power N-MOS allowing low power losses

LPM function (low power mode) to reduce dissipation

Overload and overtemperature internal protection with I²C diagnostic bits

LNB short-circuit dynamic protection

+/- 4 kV ESD tolerant on output power pins

Applications

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STB satellite receivers

TV satellite receivers

PC card satellite receivers

QFN24 (4 x 4 mm)

Description

Intended for analog and digital dual satellite receivers/Sat-TV, and Sat-PC cards, the LNBH26 is a monolithic voltage regulator and interface IC, assembled in QFN24 4x4 specifically designed to provide the 13/18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dishes or to the multi-switch box. In this application field, it offers a complete solution for dual tuner satellite receivers with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

Table 1.

Device summary

Order code

LNBH26PQR

February 2012

Package

QFN24 (4 x 4)

Doc ID 022771 Rev 1

Packaging

Tape and reel

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5

6

3

4

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Contents

Contents

LNBH26

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Application information (valid for each section A/B) . . . . . . . . . . . . . . . 4

2.1

DISEQC™ data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2

Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4

2.3

Data encoding by external DiSEqC envelope control through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4

LPM (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5

DISEQC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.6

Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7

Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.8

Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.9

Surge protections and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10

FLT: Fault FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11

VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.12

TMON: 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.13

TDET: 22 kHz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.14

IMON: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.15

PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8

2.16

Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8

2.17

PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.18

ISW: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.19

COMP: boost capacitor ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.20

OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9

2.21

OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Doc ID 022771 Rev 1

LNBH26

7

8

9

10

Contents

6.1

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2

Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3

Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5

Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1

Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2

Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3

Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4

Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.1

Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 022771 Rev 1 3/38

Block diagram

Figure 1.

Block diagram

LX-A

PGND

VUP-A

VOUT-A

Linear

Regulator

DSQIN-A ADDR SCL SDA DSQIN-B

I²C Digital core

DAC

Drop control

Tone ctrl

Diagnostics

Protections

Linear

Regulator

DETIN-A

DSQOUT-A

BPSW-A

Tone detector

Current

Limit selection

Voltage reference

ISEL GND BYP VCC

LX-B

PGND

VUP-B

VOUT-B

Tone detector

DETIN-B

DSQOUT-B

BPSW-B

FLT

AM10475v1

LNBH26

4/38 Doc ID 022771 Rev 1

LNBH26

2

Application information (valid for each section A/B)

Application information (valid for each section A/B)

The LNBH26 includes two completely independent sections. Except for ISEL, V

CC

and I²C inputs, each circuit can be separately controlled and have their independent external components. All the specifications below must be considered equal for both sections (A/B).

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (V

UP

) that let the integrated LDO post-regulator (generating the 13 V

/ 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at V

UP

- V

OUT

=

1 V typ.). The LDO power dissipation can be further reduced when 22 kHz tone output is disabled by setting the LPM bit to “1” (see LPM function description). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied V

CC drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start function reduces the in-rush current during startup. The SS time is internally fixed at 4 ms typ. to switch from

0 to 13 V, and 6 ms typ. to switch from 0 to 18 V.

2.1

2.2

DISEQC™ data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC™ standards, and can be activated in 3 different ways:

1.

by an external 22 kHz source DiSEqC™ data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1.

2. by an external DiSEqC™ data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1.

3. through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled HIGH and the EXTM bit set to “0”.

Each of the above solutions requires that during the 22 kHz tone activation and/or

DiSEqC™ data transmission, the LPM bit must be set to “0” [see

2.4: LPM (low power mode)

].

Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.

The DSQIN is a logic input pin which activates the 22 kHz tone to the V

OUT

pin, by using the

LNBH26 integrated tone generator.

The output tone waveforms are internally controlled by the LNBH26 tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26 activates the 22 kHz tone on the V

OUT

output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired (refer to

Figure 2

).

Doc ID 022771 Rev 1 5/38

Application information (valid for each section A/B)

Figure 2.

Tone enable and disable timing (using external waveform)

DSQIN

~ 60 µs

Tone

Output

~ 1 µs

AM10426v1

2.3

2.4

LNBH26

Data encoding by external DiSEqC envelope control through the DSQIN pin

If an external DiSEqC™ envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC™ envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and

TEN=1. In this way the internal 22 kHz signal is superimposed on the V

OUT

DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH the internal control circuit activates the 22 kHz tone output.

The 22 kHz tone on the V

OUT

pin is activated with a delay of about 6 µs from DSQIN TTL signal rising edge, and it stops with a delay time in the range of 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired (refer to

Figure 3

).

Figure 3.

Tone enable and disable timing (using envelope signal)

DSQIN

15 µs ~ 60 µs

Tone

Output

~ 6 µs

AM10427v1

LPM (low power mode)

In order to reduce total power loss, each section of the LNBH26 is provided with the LPM I²C bit that can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time periods. The LPM bit can be set to “1” when the DiSEqC™ data transmission is not requested (no 22 kHz tone output is present); in this condition the drop voltage across the integrated LDO regulator (V

UP

- V

OUT

) is reduced to 0.6 V typ. and, consequently, the power loss inside the relative LNBH26 channel regulator is reduced too. For example, at 500 mA load, LPM=1, allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0” before starting the 22 kHz DiSEqC™ data transmission; in this condition the drop voltage across the LDO is kept to 1 V typ. Keep

LPM=0 at all times in case the LPM function is not used.

6/38

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing.

Each LNBH26 section DETIN pin must be AC coupled to the DiSEqC™ bus, and extracted

PWK data is available on the corresponding DSQOUT pin. To comply with the bi-directional

DiSEqC™ 2.0 bus hardware requirements, an output R-L filter is needed (per each voltage

Doc ID 022771 Rev 1

LNBH26 Application information (valid for each section A/B) output pin). In order to avoid 22 kHz waveform distortion during tone transmission, each

LNBH26 section is provided with a BPSW pin to be connected to an external transistor, which allows the bypassing of the corresponding output RL filter in DiSEqC 2.x applications while in transmission mode. Before starting tone transmission by means of the DSQIN pin, provide that the TEN bit is preventively set to “1” and after ending tone transmission, provide that the TEN bit is set to “0”.

2.6 Output current limit selection

The linear regulators current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation:

Equation 1

I

MAX

( typ .)

=

16578

RSEL

1 .

206 with ISET=0

Equation 2

I

MAX

( typ .)

=

6452

RSEL

1 .

159 with ISET=1

(Refer also to the ISET bit description in

Table 9

.)

where RSEL is the resistor connected between ISEL and GND expressed in k

Ω and

I

MAX

(typ.) is the typical current limit threshold expressed in mA. I

MAX

can be set up to 1 A for each channel. However, it is recommended to not exceed, for a long period, a total amount of current of 1 A from both sections (I

OUT_A

+ I

OUT_B

< 1 A) in order to avoid the overtemperature protection triggering and to thoroughly validate the PCB layout thermal management in real application environment conditions.

2.8

Each linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 + 4 bits of an internal DATA1 register

(see

Section 7.3: Data registers

and

Table 14: Output voltage selection table (Data1 register, write mode)

for exact programmable values). Register writing is accessible via the

I²C bus.

Diagnostic and protection functions

The LNBH26 has 14 diagnostic internal functions provided via the I²C bus, by reading 14 bits on two STATUS registers (in read mode). All the diagnostic bits are, in normal operation

(that is, no failure detected), set to LOW. One diagnostic bit is dedicated to the overtemperature status (OTF), one bit is dedicated to the input voltage power not good function (PNG), while the remaining 12 bits (6 per channel) are dedicated to the overload

Doc ID 022771 Rev 1 7/38

Application information (valid for each section A/B) LNBH26 protection status (OLF), to the output voltage level (VMON), to 22 kHz tone characteristics

(TMON), to the minimum load current (IMON), to external voltage source presence on the

V

OUT

pin (PDO), and to 22 kHz tone presence on the DETIN pin (TDET). Once the OLF (or the OTF or PNG) bit has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is done.

2.9 Surge protections and TVS diodes

Each LNBH26 device section is directly connected to the antenna cable in a set-top box.

Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are

usually used, as shown in the following schematic (

Figure 4

), to protect each section of STB output circuits where the LNBH26 and other devices are electrically connected to the antenna cable.

Figure 4.

Surge protection circuit

For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically designed by ST. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details).

In order to get an immediate feedback on a diagnostic status, the LNBH26 is equipped with a dedicated fault flag pin (FLT). In the case an overload (OLF bit=1), overheating (OTF bit=1) or power not good (PNG bit=1) condition is detected, the FLT pin (open drain output) is set to low and is kept low until the relevant activating diagnostic bit is cleared. Be aware that diagnostic bits OLF, OTF and PNG, once activated, are kept latched to “1” until the origin cause is removed and a new register reading operation is performed by the microprocessor.

The FLT pin must be connected to a positive voltage (5 V max.) by means of a pull-up resistor.

2.11 VMON: output voltage diagnostic

When one device output voltage is activated (V

OUT

pin), its value is internally monitored and, as long as the output voltage level is below the guaranteed limits, the relevant VMON

I²C bit is set to “1” (see

Table 17

for more details).

8/38 Doc ID 022771 Rev 1

LNBH26 Application information (valid for each section A/B)

2.12 TMON: 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored if one (or both) DETIN pin are

connected to the LNB output bus (see

Figure 7

) through a decoupling capacitor.

The tone diagnostic function is provided with the corresponding TMON I²C bit. If the 22 kHz

tone amplitude and/or the tone frequency is out of the guaranteed limits (see

Table 19

), the

corresponding TMON I²C bit is set to “1”.

2.13 TDET: 22 kHz tone detection

When a 22 kHz tone presence is detected on one DETIN pin, the corresponding TDET I²C bit is set to “1”.

2.14 IMON: minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) each LNBH26 section is provided with a minimum output current flag by the corresponding IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than 12 mA (typ.). It is recommended to use the IMON function only with the

22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the output current is below the minimum current threshold. To activate the IMON diagnostic function, set to “1” the EN_IMON I²C bit in the DATA4 register. Be aware that as soon as the

IMON function is activated by means of EN_IMON=1, the V

OUT

is immediately increased to

21 V (typ.) independently on the VSEL bit setting. This operation is applied in order to be sure that the LNBH26 output has the higher voltage present in the LNB bus. Do not use this function in an application environment where a 21 V voltage level is not supported by other peripherals connected to the LNB bus.

2.15 PDO: overcurrent detection on output pull-down stage

When an overcurrent occurs on one section pull-down output stage due to an external voltage source greater than the LNBH26 nominal V

OUT

, and for a time longer than

I

SINK_TIME_OUT

(10 ms typ.), the corresponding PDO I²C bit is set to “1”. This may happen due to an external voltage source presence on the LNB output (V

OUT

pin).

For current threshold and deglitch time details, see

Table 13

.

2.16 Power-on I²C interface reset and undervoltage lockout

The I²C interface built into the LNBH26 is automatically reset at power-on. As long as the

V

CC

stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor.

Doc ID 022771 Rev 1 9/38

Application information (valid for each section A/B) LNBH26

2.17 PNG: input voltage minimum detection

When input voltage (V

CC

pin) is lower than LPD (low power diagnostic) minimum thresholds,

the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to

Table 3

for threshold details.

2.18 ISW: inductor switching current limit

In order to allow low saturation current inductors to be used, the maximum DC-DC inductor switching current limit threshold can be set by means of one I²C bit per section (ISW). Two values are available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).

2.19 COMP: boost capacitor ESR

The DC-DC converter compensation loop can be optimized in order to work well with high or low ESR capacitors (on the V

UP pin). For this purpose, one I²C bit in the DATA4 register

(COMP) can be set to “1” or “0”. It is recommended to reset this bit to “0” unless using high

ESR capacitors.

2.20 OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. It is possible to set the short-circuit current protection either statically (simple current clamp) or dynamically by the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T

ON

time (90 ms or 180 ms typ., according to the corresponding TIMER bit programmed in the DATA3 register) and after that, the output is set in shutdown for a T

OFF

time of typically 900 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1” and the FLT pin is set to low level. After this time has elapsed, the involved output is resumed for a time T

ON

. At the end of T

ON

, if the overload is still detected, the protection circuit cycles again through

T

OFF

and T

ON

. At the end of a full T

ON

in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after register reading is done. Typical

T

ON

+T

OFF

time is 990 ms (if TIMER=0) or 1080 ms (if TIMER=1) and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in shortcircuit condition, still ensuring excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and then, switching to dynamic mode (PCL=0) after a chosen amount of time, depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns LOW when the overload condition is cleared and register reading is done.

After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register.

If OLR=1, all VSEL bits corresponding to the involved section are reset to “0” and the LNB section output (V

OUT

pin) is disabled. To re-enable the output stage, the VSEL bits must be set again by the microprocessor and the OLF bit is reset to “0” after a register reading operation.

10/38 Doc ID 022771 Rev 1

LNBH26 Application information (valid for each section A/B)

If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation.

2.21 OTF: thermal protection and diagnostic

The LNBH26 is also protected against overheating: when the junction temperature exceeds

150 °C (typ.), the step-up converter and both liner regulators are shut off, the diagnostic

OTF bit in the STATUS1 register is set to “1” and the FLT pin is set to low level. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register.

If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (V

OUT

pins) are disabled.

To re-enable output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation.

If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.

Doc ID 022771 Rev 1 11/38

Pin configuration LNBH26

Figure 5.

Pin connections (top view)

DSQIN B DSQOUT - A VUP -A

FLT

LX

PGND

-A

VCC

BYP

GND

ADDR

NC

BPSW -B

SCL SDA ISEL VUP B VOUT B DETIN B

AM10476v1

Table 2.

Pin

Pin description

Symbol Name

1

2

3

4

5

6

7

8

9

Pin function

DSQOUT-B

FLT

LX-A

P-GND

LX-B

ADDR

SCL

SDA

ISEL

DiSEqC output

FLT

Open drain output of channel A tone detector to the main microcontroller for DiSEqC 2.0 data decoding. It is low when tone is detected on the

DETIN-B input pin. Set to ground if not used.

Open drain output for IC fault conditions. It is set low in case of overload

(OLF bit) or overheating status (OTF bit) or power not good (PNG bit) is detected. To be connected to pull-up resistor (5 V max.).

N-Mos drain

Power ground

N-Mos drain

Address setting

Serial clock

Serial data

Channel A, integrated N-channel Power MOSFET drain.

DC-DC converter power ground. To be connected directly to the exposed pad.

Channel B, integrated N-channel Power MOSFET drain.

Two I

2

C bus addresses available by setting the address pin level voltage.

See Table 16 .

Clock from I²C bus.

Bi-directional data from/to I²C bus.

Current selection for both channel

A and B

The resistor “RSEL” connected between ISEL and GND defines the linear

regulator current limit threshold. Refer to Section 2.5

. Also see the ISET

bit description in Table 9 . The RSEL resistor defines the same current

limit both for channels A and B.

12/38 Doc ID 022771 Rev 1

LNBH26 Pin configuration

Table 2.

Pin

Pin description (continued)

Symbol Name Pin function

10

11

12

13

14

V

V

UP-B

OUT-B

DETIN-B

BPSW-B

N.C.

Channel B step-up voltage

Input of channel B linear post-regulator. The voltage on this pin is monitored by the internal channel B step-up controller to keep a minimum dropout across the linear pass transistor.

Channel B,

LNB output port

Tone detector input

Switch control

Output of channel B integrated very low drop linear regulator. See

Table 14

for voltage selection and description.

Channel B, 22 kHz tone decoder input, must be AC coupled to the

DiSEqC 2.0 bus. Set to ground if not used.

To be connected to an external transistor to be used to bypass the channel B output RL filter needed in DiSEqC 2.x applications during the

DiSEqC transmitting mode (see Section 5

). Set to ground if not used.

Open drain pin.

Not internally connected

Not internally connected pin. Set floating if not used.

Analog ground Analog circuits ground. To be connected directly to the exposed pad.

15 GND

16

17

18

BYP

V

CC

BPSW-A

Bypass capacitor

Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.

Supply input

Switch control

8 to 16 V IC DC-DC power supply.

To be connected to an external transistor to be used to bypass the channel A output RL filter needed in DiSEqC 2.x applications during the

DiSEqC transmitting mode (see Section 5

). Set to ground if not used.

Open drain pin.

19

20

DETIN-A

V

OUT-A

Tone detector input

Channel A,

LNB output port

Channel A, 22 kHz tone decoder input, must be AC coupled to the

DiSEqC 2.0 bus. Set to ground if not used.

Output of channel A integrated very low drop linear regulator. See

Table 14

for voltage selection and description.

21

22

23

V

UP-A

DSQIN-A

DSQOUT-A

Channel A step-up voltage

DiSEqC output

Input of channel A linear post-regulator. The voltage on this pin is monitored by the internal channel A step-up controller to keep a minimum dropout across the linear pass transistor.

DSQIN for

DiSEqC envelope input or external 22 kHz

TTL input

It is intended for channel A 22 kHz tone control.

It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-A I²C bit setting as follows:

If EXTM-A=0, TEN-A=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH26 uses this code to modulate the internally generated 22 kHz carrier.

If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which

activate the 22 kHz tone output (refer to Section 2.2

).

Pull up high if the tone output is activated only by the TEN-A I²C bit.

Open drain output of channel A tone detector to the main microcontroller for DiSEqC 2.0 data decoding. It is low when tone is detected to the

DETIN-A input pin. Set to ground if not used.

Doc ID 022771 Rev 1 13/38

Pin configuration LNBH26

Table 2.

Pin

24

Epad

Pin description (continued)

Symbol

DSQIN-B

Epad

Name Pin function

DSQIN for

DiSEqC envelope input

Or external 22 kHz

TTL input

It is intended for channel B 22 kHz tone control.

It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-B I²C bit setting as follows:

If EXTM-B=0, TEN-B=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH26 uses this code to modulate the internally generated 22 kHz carrier.

If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which

activate the 22 kHz tone output (refer to Section 2.2

).

Pull up high if the tone output is activated only by the TEN-B I²C bit.

Exposed pad

To be connected with power grounds and to the ground layer through vias to dissipate the heat.

14/38 Doc ID 022771 Rev 1

LNBH26 Maximum ratings

Table 3.

Symbol

V

CC

V

UP

I

OUT

V

OUT

V

I

V

O

V

BPSW

V

DETIN

I

O

LX

V

BYP

ISEL

T

STG

T

J

ESD

Absolute maximum ratings

Parameter

DC power supply input voltage pins

DC input voltage

Output current

DC output pin voltage

Logic input pin voltage (SDA, SCL, DSQIN, ADDR pins)

Logic output pin voltage (FLT, DSQOUT)

BPSW pin voltage

Detector input signal amplitude

Logic output pin current (FLT, DSQOUT, BPSW)

LX input voltage

Internal reference pin voltage

Current selection pin voltage

Storage temperature range

Operating junction temperature range

ESD rating with human body model (HBM) for all pins, except power output pins

ESD rating with human body model (HBM) for power output pins

Value

-0.3 to 20

-0.3 to 40

Internally limited

-0.3 to 40

-0.3 to 7

-0.3 to 7

-0.3 to 40

-0.6 to 2

10

-0.3 to 30

-0.3 to 4.6

-0.3 to 3.5

-50 to 150

-25 to 125

Unit

V

V mA

V

V

V

V

V mA

V

V

V

°C

°C

2

4 kV

Table 4.

Symbol

R thJC

R thJA

Thermal data

Parameter

Thermal resistance junction-case

Thermal resistance junction-ambient with device soldered on 2s2p 4layer PCB provided with thermal vias below exposed pad.

Note:

Value

2

40

Unit

°C/W

°C/W

Absolute maximum ratings are those values beyond which damage to the device may occur.

These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.

Doc ID 022771 Rev 1 15/38

Typical application circuits LNBH26

Figure 6.

DiSEqC 1.x application circuit

D2-A

LNBOUT-A

Vin

12V

C1

D1-A

L1-A

L1-B

21 V

UP-A

C2-A C3-A

3 LX-A

R1 (RSEL)

C7

9 ISEL

16 Byp

17 Vcc

C4

I 2 C Bus

{ 8

7

SDA

SCL

5 LX-B

LNBH26

V

OUT-A 20

DSQIN-A 22

DSQIN-B 24

ADDR 6

FLT 2

C5-A

D3-A

Tone enable control

DiSEqC

22KHz TTL or

DiSEqC

Envelope TTL

D1-B

C2-B C3-B

10 V

UP-B

P-GND A-GND

4 15

V

OUT-B 11

C5-B D3-B

D2-B

LNBOUT-B

AM10477v1

Table 5.

Component

DiSEqC 1.x bill of material (valid for A and B channels except for C1, C4,

C7 and R1)

Notes

R1 (RSEL)

SMD resistor. Refer to Table 13

and ISEL pin description in

Table 2

C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable

C3

C5

From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.

From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.

C4, C7

D1

D3

D2

L1

220 nF ceramic capacitors

STPS130A or similar schottky diode

BAT54, BAT43, 1N5818, or any low power schottky diode with I

F

(AV) > 0.2 A,

V

RRM

> 25 V, V

F

< 0 .5 V . To be placed as close as possible to V

OUT

pin

1N4001-07, S1A-S1M, or any similar general purpose rectifier

10 µH inductor with I sat

> I peak

where I peak

is the boost converter peak current

16/38 Doc ID 022771 Rev 1

LNBH26 Typical application circuits

Figure 7.

DiSEqC 2.x application circuit

D2-A

Vin

12V

C1

D1-A

L1-A

L1-B

D1-B

L2-A

LNBOUT-A

21 V

UP-A

V

OUT-A 20

C5-A D3-A

15 Ω

C2-A C3-A

3 LX-A

R1 (RSEL)

C7

9 ISEL

16 Byp

17 Vcc

C4

I 2 C Bus

{ 8

7

SDA

SCL

5 LX-B

C2-B C3-B

LNBH26

BPSW-A 18

4.7k

DETIN-A 19

DSQOUT-A 23

4.7k

10k

DSQIN-A 22

DSQIN-B 24

ADDR 6

2

TR1-A

C6-A

Tone enable control

Open drains to µController

DiSEqC

22KHz TTL or

DiSEqC

Envelope TTL

10 V

UP-B

P-GND A-GND

4 15

DSQOUT-B 1

DETIN-B

12

BPSW-B 13

4.7k

10k

4.7k

V

OUT-B 11

C5-B D3-B

15 Ω

L2-B

TR1-B

C6-B

LNBOUT-B

D2-B

AM10478v1

Table 6.

Component

DiSEqC 2.x bill of material (valid for A and B channels except for C1, C4,

C7 and R1)

Notes

R1 (RSEL) SMD resistors. Refer to

Table 13

and ISEL pin description in Table 2

C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable

C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.

C5

C4, C7

C6

D1

From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.

220 nF ceramic capacitors

10 nF ceramic capacitors

STPS130A or similar schottky diode

D3

D2

L1

L2

TR1

BAT54, BAT43, 1N5818, or any low power schottky diode with I

F

(AV) > 0.2 A,

V

RRM

> 25 V, V

F

< 0 .5 V . To be placed as close as possible to V

OUT

pin

1N4001-07, S1A-S1M, or any similar general purpose rectifier

10 µH inductor with I sat

> I peak

where I peak

is the boost converter peak current

220 µH inductor

2STR2160 or 2STF2340 or any small power PNP with IC > 250 mA, V

CE

> 30 V, can be used.

Also any small power PMOS with ID > 250 mA, R

DSON used.

< 0.5

Ω, V

DS

> 20 V, can be

Doc ID 022771 Rev 1 17/38

I²C bus interface

6 I²C bus interface

LNBH26

Data transmission from the main microprocessor to the LNBH26 and vice versa takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).

6.2

As shown in

Figure 8

, the data on the SDA line must be stable during the high semi-period

of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Start and stop condition

As shown in

Figure 9

, a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is

HIGH. A STOP condition must be sent before each START condition.

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

6.4 Acknowledge

The master (microprocessor) puts a resistive HIGH level on the SDA line during the

acknowledge clock pulse (see

Figure 10

). The peripheral (LNBH26) which acknowledges

must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed must generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH26 does not generate acknowledge if the V

CC

supply is below the undervoltage lockout threshold (4.7 V typ.).

If detection of the acknowledge of the LNBH26 is not required, the microprocessor can use a simpler transmission: it simply waits one clock without checking the slave acknowledging, and sends the new data. This approach is of course less protected from misworking and decreases noise immunity.

18/38 Doc ID 022771 Rev 1

LNBH26

Figure 8.

Data validity on the I²C bus

I²C bus interface

Figure 9.

Timing diagram of I²C bus

Figure 10.

Acknowledge on the I²C bus

Doc ID 022771 Rev 1 19/38

I²C interface protocol

7 I²C interface protocol

LNBH26

The LNBH26 interface protocol is made up of:

●

●

●

●

●

●

● a start condition (S) a chip address byte with the LSB bit R/W = 0 a register address (internal address of the first register to be accessed) a sequence of data (byte to write in the addressed internal register + acknowledge) the following bytes, if any, to be written in successive internal registers a stop condition (P). The transfer lasts until a stop bit is encountered the LNBH25, as slave, acknowledges every byte transfer.

Figure 11.

Example of writing procedure starting with first data address 0x2

(a)

CHIP ADDRESS

MSB LSB

REGISTER ADDRESS

MSB LSB

S 0 0 0 1 0 0 X 0 0 0 0 0 X X X

MSB

DATA 1

Add=0x2

LSB MSB

DATA 2

Add=0x3

LSB MSB

DATA 3

Add=0x4

LSB MSB

DATA 4

Add=0x5

LSB

P

AM10479v1

ACK = Acknowledge

S = Start

P = Stop

R/W = 1/0, Read/Write bit

X = 0/1, set the values to select the CHIP address (see

Table 16

for pin selection) and to select the REGISTER address (see

Table 7

to

Table 12

).

20/38 a.

The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped by the master by sending a stop condition after any acknowledge bit.

Doc ID 022771 Rev 1

LNBH26 I²C interface protocol

●

●

●

●

●

In read mode the bytes sequence must be as follows:

● a start condition (S) a chip address byte with the LSB bit R/W=0 the register address byte of the internal first register to be accessed a stop condition (P) a new master transmission with the chip address byte and the LSB bit R/W=1

● after the acknowledge the LNBH26 starts to send the addressed register content. As long as the master keeps the acknowledge LOW, the LNBH26 transmits the next address register byte content.

the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit.

Figure 12.

Example of reading procedure starting with first status address 0X0

(b)

MSB

CHIP ADDRESS

LSB

REGISTER ADDRESS

MSB LSB MSB

CHIP ADDRESS

LSB

S 0 0 0 1 0 0 X 0 0 0 0 0 X X X P S 0 0 0 1 0 0 X

MSB

STATUS 1

Add=0x0

LSB MSB

STATUS 2

Add=0x1

LSB

MSB

DATA 1

Add=0x2

LSB MSB

DATA 2

Add=0x3

LSB MSB

DATA 3

Add=0x4

LSB MSB

DATA 4

Add=0x5

LSB

P

AM10480v1

ACK = Acknowledge

S = Start

P = Stop

R/W = 1/0, Read/Write bit

X = 0/1, set the values to select the CHIP address (see

Table 16

for pin selection) and to select the REGISTER address (see

Table 7

to

Table 12

).

b.

The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped by the master by sending a stop condition after any acknowledge bit.

Doc ID 022771 Rev 1 21/38

I²C interface protocol LNBH26

Table 7.

Bit

Bit 0

(LSB)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

(MSB)

The DATA 1..4 registers can be addressed both in write and read mode. In read mode they return the last writing byte status received in the previous write transmission.

The following tables provide the register address values of Data 1..4 and a function description of each bit.

DATA 1 (Read/Write register. Register address = 0X2)

Name CH Value Description

VSEL1-A

VSEL2-A

VSEL3-A

VSEL4-A

VSEL1-B

VSEL2-B

VSEL3-B

VSEL4-B

A

B

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

Channel A

Output voltage selection bits.

(Refer to

Table 14

)

Channel B

Output voltage selection bits.

(Refer to

Table 14

)

N/A = Reserved bit.

All bits reset to “0” at power-on.

22/38 Doc ID 022771 Rev 1

LNBH26 I²C interface protocol

Table 8.

Bit

DATA 2 (Read/Write register. Register address = 0X3)

Name CH Value Description

Bit 0

(LSB)

Bit 1

TEN-A

LPM-A

Bit 2 EXTM-A

Bit 3

Bit 4

Bit 5

N/A

TEN-B

LPM-B

Bit 6 EXTM-B

A

B

1

0

0

1

0

1

1

0

1

0

1

0

0

22 kHz tone enabled. Tone output controlled by the DSQIN pin

22 kHz tone output disabled

Low power mode activated (used only with 22 kHz tone output disabled)

Low power mode deactivated (keep always LPM=0 during 22 kHz tone transmission)

DSQIN input pin is set to receive external 22 kHz TTL signal source

DSQIN input pin is set to receive external DiSEqC envelope TTL signal

Reserved. Keep to “0”

22 kHz tone enabled. Tone output controlled by the DSQIN pin

22 kHz tone output disabled

Low power mode activated (used only with 22 kHz tone output disabled)

Low power mode deactivated (keep always LPM=0 during 22 kHz tone transmission)

DSQIN input pin is set to receive external 22 kHz TTL signal source

DSQIN input pin is set to receive external DiSEqC envelope TTL signal

Bit 7

(MSB)

N/A 0 Reserved. Keep to “0”

N/A = Reserved bit.

All bits reset to 0 at power-on.

Doc ID 022771 Rev 1 23/38

I²C interface protocol

Table 9.

Bit

DATA 3 (Read/Write register. Register address = 0X4)

Name CH Value Description

Bit 0

(LSB)

Bit 1

Bit 2

Bit 3 TIMER-A

Bit 4

Bit 5

Bit 6

ISET-A

ISW-A

PCL-A

ISET-B

ISW-B

PCL-B

Bit 7

(MSB)

TIMER-B

A

B

1

0

0

1

0

1

0

1

0

1

0

1

0

1

1

0

Current limit of LNB output (Vout pin) set to lower current range:

Refer to Section 2.5

in application information section.

Current limit of LNB output (Vout pin) set to default range:

Refer to Section 2.5

in application information section.

DC-DC, inductor switching current limit set to 2.5 A typ.

DC-DC, inductor switching current limit set to 4 A typ.

Pulsed (Dynamic) LNB output current limiting is deactivated

Pulsed (Dynamic) LNB output current limiting is activated

Pulsed (Dynamic) LNB output current T

ON

time set to 180 ms typ.

Pulsed (Dynamic) LNB output current T

ON

time set to 90 ms typ.

Current limit of LNB output (V

OUT

pin) set to lower current range:

Refer to Section 2.5

in the application information section.

Current limit of LNB output (V

OUT

pin) set to default range:

Refer to Section 2.5

in the application information section.

DC-DC, inductor switching current limit set to 2.5 A typ.

DC-DC, inductor switching current limit set to 4 A typ.

Pulsed (Dynamic) LNB output current limiting is deactivated

Pulsed (Dynamic) LNB output current limiting is activated

Pulsed (Dynamic) LNB output current T

ON

time set to 180 ms typ.

Pulsed (Dynamic) LNB output current T

ON

time set to 90 ms typ.

N/A = Reserved bit.

All bits reset to 0 at power-on.

LNBH26

24/38 Doc ID 022771 Rev 1

LNBH26 I²C interface protocol

Table 10.

DATA 4 (Read/Write register. Register address = 0X5)

Bit Name CH Value Description

Bit 0

(LSB)

EN_IMON-

A

Bit 1

Bit 2

Bit 3

Bit 4

EN_IMON-

B

Bit 5

Bit 6

Bit 7

(MSB)

N/A

N/A

OLR

N/A

THERM

COMP

A

A/B

B

A/B

1

0

0

1

0

0

0

1

0

1

0

1

0

IMON diagnostic function is enabled .

(V

OUT

is set to 21 V typ.)

IMON diagnostic function is disabled. Keep always at “0” if IMON is not used.

Reserved. Keep to “0”

Reserved. Keep to “0”

In the case of overload protection activation (OLF=1), all VSEL bits are reset to “0” and LNB relevant output (V

OUT

pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0).

In the case of overload protection activation (OLF=1) the LNB output (V

OUT pin) is automatically enabled as soon as the overload condition is removed

(OLF=0) with the previous VSEL bit setting.

IMON diagnostic function is enabled

IMON diagnostic function is disabled. Keep always at “0” if IMON is not used.

Reserved. Keep to “0”

If thermal protection is activated (OTF=1), all VSEL bits are reset to “0” and

LNB output (V

OUT

pin) is disabled (both section A & B). The VSEL bits must be set again by the master after the overtemperature condition is removed

(OTF=0).

In the case of thermal protection activation (OTF=1) the LNB output (V

OUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=0) with the previous VSEL bit setting.

DC-DC converter compensation set to use HIGH E.S.R. capacitors (V

UP

pin)

DC-DC converter compensation set to use LOW E.S.R. capacitors (V

UP

pin)

Doc ID 022771 Rev 1 25/38

I²C interface protocol LNBH26

The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables.

Table 11.

STATUS 1 (Read register. Register address = 0X0)

Bit Name CH Value Description

Bit 0

(LSB)

Bit 1

OLF-A

OLF-B

A

B

Bit 2 VMON-A A

Bit 3 VMON-B B

Bit 4

Bit 5

Bit 6

Bit 7

(MSB)

PDO-A

PDO-B

OTF

PNG

A

B

A/B

A/B

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V

OUT

pin overload protection has been triggered (I

OUT

> I

MAX

). Refer to

Table 9

for the overload operation settings (ISET, PCL, TIMER bits).

No overload protection has been triggered to V

OUT

pin (I

OUT

< I

MAX

).

V

OUT

pin overload protection has been triggered (I

OUT

> I

MAX

). Refer to

Table 9

for the overload operation settings (ISET, PCL, TIMER bits).

No overload protection has been triggered to V

OUT

pin (I

OUT

< I

MAX

).

Output voltage (V

OUT

pin) lower than VMON specification thresholds. Refer to

Table 17 .

Output voltage (V

OUT

pin) is within the VMON specifications.

Output voltage (V

OUT

pin) lower than VMON specification thresholds. Refer to

Table 17 .

Output voltage (V

OUT

pin) is within the VMON specifications.

Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (V

OUT

pin).

No overcurrent detected on output pull-down stage.

Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (V

OUT

pin).

No overcurrent detected on output pull-down stage.

Junction overtemperature is detected, T

J bit setting in

Table 10 .

> 150 °C (typ.). See also the THERM

Junction overtemperature not detected, T

J

<135 °C (typ.). T

J

is below thermal protection threshold.

Input voltage (V

CC

pin) lower than LPD minimum thresholds. Refer to

Table 13 .

Input voltage (V

CC

pin) higher than LPD thresholds. Refer to

Table 13

.

N/A = Reserved bit.

All bits reset to 0 at power-on.

26/38 Doc ID 022771 Rev 1

LNBH26 I²C interface protocol

Table 12.

STATUS 2 (Read register. Register address = 0X1)

Bit Name CH Value Description

Bit 0

(LSB)

TDET-A

Bit 1 TDET-B

Bit 6

Bit 7

(MSB)

N/A

N/A

A

B

Bit 2 TMON-A A

Bit 3 TMON-B B

Bit 4 IMON-A A

Bit 5 IMON-B B

1

0

1

0

1

0

1

0

1

0

1

0

-

-

22 kHz tone presence is detected on the DETIN pin

No 22 kHz tone is detected on the DETIN pin

22 kHz tone presence is detected on the DETIN pin

No 22 kHz tone is detected on the DETIN pin

22 kHz tone present on the DETIN pin is out of TMON specification thresholds.

That is: the tone frequency or the A

TONE

(tone amplitude) are out of the

thresholds guaranteed in Table 19 .

22 kHz tone present on the DETIN pin is within TMON specification

thresholds. Refer to Table 19 .

22 kHz tone present on the DETIN pin is out of TMON specification thresholds.

That is: the tone frequency or the A

TONE

(tone amplitude) are out of the

thresholds guaranteed in Table 19 .

22 kHz tone present on DETIN pin is within TMON specification thresholds.

Refer to

Table 19

.

Output current (from V

OUT

pin) is lower than IMON specification thresholds.

Refer to

Table 18

.

Output current (from V

OUT

pin) is higher than IMON specifications.

Refer to

Table 18

.

Output current (from V

OUT pin) is lower than IMON specification thresholds.

Refer to

Table 18

.

Output current (from V

OUT

pin) is higher than IMON specifications.

Refer to

Table 18

.

Reserved

Reserved

N/A = Reserved bit.

All bits reset to 0 at power-on.

Doc ID 022771 Rev 1 27/38

Electrical characteristics LNBH26

Refer to

Section 5

, T

J

from 0 to 85 °C, all DATA 1..4 register bits set to 0 except VSEL1 = 1,

RSEL = 11 k

Ω, DSQIN = LOW, V

IN

= 12 V, I

OUT

= 50 mA, unless otherwise stated. Typical values are referred to T

J

= 25 °C. V

OUT

= V

OUT

pin voltage. See software description section for I²C access to the system register (

Section 6

and

Section 7

).

Table 13.

Electrical characteristics of section A/B

Symbol Parameter

Supply voltage

(1)

Test conditions

V

IN

I

IN

Supply current

Both sections A and B enabled,

I

OUT

= 0 mA

22 kHz tone enabled (TEN-A/B = 1,

DSQIN-A/B = High), I

OUT

= 0 mA

Both sections A and B set in standby:

VSEL1=VSEL2=VSEL3=VSEL4=0

V

OUT

V

OUT

V

OUT

I

I

MAX

MAX

Output voltage total accuracy

Line regulation

Load regulation

Output current limiting thresholds

Output current limiting thresholds

Valid at any V

OUT

selected level

V

IN

= 8 to 16 V

I

OUT

from 50 to 750 mA

RSEL = 11 k Ω, ISET = 0

RSEL = 15 k Ω, ISET = 0

RSEL = 20 k

Ω, ISET = 0

RSEL = 11 k Ω, ISET = 1

RSEL = 15 k

Ω, ISET = 1

RSEL = 20 k Ω, ISET = 1

RSEL = 11 k Ω, ISET = 0 I

SC

SS

SS

T13-18

Output short-circuit current

Soft-start time

Soft-start time

Soft transition rise time

V

OUT

from 0 to 13 V

V

OUT

from 0 to 18 V

V

OUT

from 13 V to 18 V

T18-13

T

OFF

Soft transition fall time V

OUT

from 18 V to 13 V

Dynamic overload protection OFF time

PCL = 0, output shorted

Min.

Typ.

Max.

Unit

8

-3.5

750

500

350

12

12

19

2

100

400

280

200

500

4

6

1.5

1.5

900

16

+3.5

%

40 mV

1100

750

550

V mA mA mA mA ms ms ms ms ms

T

ON

Dynamic overload protection ON time

PCL = TIMER = 0, output shorted

PCL = 0, TIMER = 1, output shorted

T

OFF

/

10

T

OFF

/

5

A

TONE

Tone amplitude

DSQIN=High, EXTM=0, TEN=1

I

OUT

from 0 to 750 mA

C

BUS

from 0 to 750 nF

0.55

0.675

0.8

V

PP

28/38 Doc ID 022771 Rev 1

LNBH26 Electrical characteristics

Table 13.

Electrical characteristics of section A/B (continued)

Symbol Parameter Test conditions Min.

Typ.

Max.

Unit

F

TONE

D

TONE tr, tf

Tone frequency

Tone duty cycle

Tone rise or fall time

(2)

Eff

DC/DC

DC-DC converter efficiency

F

SW

DC-DC converter switching frequency

I

DSQIN=High, EXTM=0, TEN=1

OUT

= 500 mA

20

43

5

22

50

8

93

440

24 kHz

57

15

%

µs

% kHz

UVLO

V

LP

Undervoltage lockout thresholds

Low power diagnostic (LPD) thresholds

UVLO threshold rising

UVLO threshold falling

V

LP

threshold rising

V

LP

threshold falling

4.8

4.7

7.2

6.7

V

V

F

V

V

I

IL

IH

IH

DETIN

DSQIN, pin logic low

DSQIN, pin logic high

DSQIN, pin input current

Tone detector frequency capture range

V

IH

= 5 V

0.4 V

PP

sine wave

(3)

2

19

15

22

0.8

25

V

V

µA kHz

V

DETIN

Z

DETIN

V

OL

V

OL_BPS

W

Tone detector input amplitude

Tone detector input impedance

DSQOUT, FLT pins logic LOW

BPSW pin low voltage

Sine wave signal, 22 kHz

DETIN tone present, I

I

OL_BPSW

= 5 mA

OL

= 2 mA

DSQIN = high, EXTM = 0, TEN = 1

0.3

150

0.7

1.5

V

PP k

Ω

0.3

0.5

V

V

I

OZ

DSQOUT, FLT pins leakage current

Output backward current

DETIN tone absent, V

OH

= 6 V 10 µA

I

I

I

OBK

SINK

SINK_TIM

E-OUT

Output low-side sink current

Low-side sink current time-out

All VSELx = 0, V

OBK

= 30 V

V

OUT

forced at V

OUT_nom

+0.1 V

V

OUT

forced at V

OUT_nom

+0.1 V.

PDO I²C bit is set to 1 after this time is elapsed.

-3

70

10

-6 mA mA ms

I

REV

Max. reverse current

V

OUT

forced at V

OUT_nom

+0.1 V, after PDO bit is set to 1 (I

SINK_TIME-

OUT elapsed).

2 mA

T

SHDN

ΔT

SHDN

Thermal shutdown threshold

Thermal shutdown hysteresis

150

15

°C

°C

1.

In applications where (V

CC

- V

OUT

) > 1.3 V, the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design.

2.

Guaranteed by design.

3.

Frequency range in which the DETIN function is guaranteed. The Vpp level is intended on the LNB bus (before the C6 capacitor. See typical application circuit for DiSEqC 2.x) I

OUT

from 0 to 750 mA, C

BUS

from 0 to 750 nF.

Doc ID 022771 Rev 1 29/38

Electrical characteristics LNBH26

Each LNBH26 channel is provided with 15 output voltage levels (7 levels for 13 V range when VSEL4-A/B=0 and 8 levels for 18 V range when VSEL4-A/B=1) which can be selected

through the register Data1.

Table 14

shows the output voltage values corresponding to

VSELx bit combinations both for channel A and B. If all VSELx are set to “0” the device is set in standby mode and the VOUT-A/B is disabled.

0

0

0

0

0

0

0

Table 14.

Output voltage selection table (Data1 register, write mode)

(1)

VSEL4-

A/B

VSEL3-

A/B

VSEL2-

A/B

VSEL1-

A/B

V

OUT min.

V

OUT

-A/B pin voltage

V

OUT max.

0 0 0 0 0

Function

V

OUT

-A/B disabled. LNBH26 set in standby mode

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

12.545

12.867

13.188

13.51

13.832

14.153

14.475

13.000

13.333

13.667

14.000

14.333

14.667

15.000

13.455

13.800

14.145

14.490

14.835

15.180

15.525

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1.

T

J

from 0 to 85 °C, V

I

= 12 V.

0

1

1

1

0

0

0

1

1

0

1

1

0

0

1

0

17.515

17.836

18.158

18.48

18.801

19.123

19.445

19.766

18.150

18.483

18.817

19.150

19.483

19.817

20.150

20.483

18.785

19.130

19.475

19.820

20.165

20.510

20.855

21.200

T

J

from 0 to 85 °C, V

I

= 12 V.

Table 15.

I²C electrical characteristics

Symbol Parameter Test conditions

V

IL

V

IH

V

I

IN

OL

Low level input voltage

High level input voltage

SDA, SCL

SDA, SCL

Input current

Low level output voltage

(1)

SDA, SCL, V

IN

= 0.4 to 4.5 V

SDA (open drain), I

OL

= 6 mA

F

MAX

Maximum clock frequency

1.

Guaranteed by design.

SCL

30/38 Doc ID 022771 Rev 1

Min.

Typ.

Max.

Unit

0.8

2

-10

400

10

0.6

V

V

µA

V kHz

LNBH26 Electrical characteristics

T

J

from 0 to 85 °C, V

I

= 12 V.

Table 16.

Address pin characteristics

Symbol Parameter

V

ADDR-1

V

ADDR-2

Test condition

“0001000(R/W)” address pin voltage range

R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)

“0001001(R/W)” address pin voltage range

R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)

Min.

Typ.

Max.

0

2

0.8

5

Unit

V

V

Refer to

Section 5

, T

J

from 0 to 85 °C, All DATA 1..4 register bits set to “0”, RSEL = 11 k

Ω,

DSQIN = LOW, V

IN

= 12 V, I

OUT

= 50 mA, unless otherwise stated. Typical values are referred to T

J

= 25 °C. V

OUT

= V

OUT

pin voltage. See software description section for I²C access to the system register.

Table 17.

Output voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

V

TH-L

V

TH-L

Diagnostic low threshold at

V

OUT

= 13.0 V

Diagnostic low threshold at

V

OUT

= 18.15 V

VSEL1 = 1,

VSEL2 = VSEL3 = VSEL4 = 0

VSEL4=1,

VSEL1 = VSEL2 = VSEL3 = 0

80

80

90

90

95

95

%

%

Note: If the output voltage is lower than the min. value the VMON I²C bit is set to 1.

If VMON=0 then V

OUT

> 80% of V

OUT

(typ.).

If VMON=1 then V

OUT

< 95% of V

OUT

(typ.).

Refer to

Section 5

, T

J

from 0 to 85 °C, RSEL = 11 k

Ω, DSQIN = LOW, V

IN

= 12 V, unless otherwise stated. Typical values are referred to T

J

= 25 °C. V

OUT

= V

OUT software description section for I²C access to the system register.

pin voltage. See

Table 18.

Output current diagnostic (IMON-A/B bit, STATUS 2 register) characteristics

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

I

TH

Minimum current diagnostic threshold

EN_IMON = 1 (V

OUT

is set to 21 V typ.) 5 12 20 mA

Note: If the output current is lower than the min. threshold limit, the IMON I²C bit is set to 1. If the output current is higher than the max. threshold limit, the IMON I²C bit is set to 0.

Doc ID 022771 Rev 1 31/38

Electrical characteristics LNBH26

Refer to

Section 5

, T

J

from 0 to 85 °C, All DATA 1..4 register bits set to “0” except

VSEL1 = 1, TEN=1, RSEL = 11 k

Ω, DSQIN = HIGH, V

IN

= 12 V, I

OUT

= 50 mA, unless otherwise stated. Typical values are referred to T

J

= 25 °C. V

OUT software description section for I²C access to the system register.

= V

OUT

pin voltage. See

Table 19.

22 kHz tone diagnostic (TMON-A/B bit, STATUS 2 register) characteristics

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

A

TH-L

200 300 400 mV

A

TH-H

F

TH-L

F

TH-H

Amplitude diagnostic low threshold DETIN pin AC coupled

Amplitude diagnostic high threshold

DETIN pin AC coupled

Frequency diagnostic low thresholds

Frequency diagnostic high thresholds

DETIN pin AC coupled

DETIN pin AC coupled

900 1100 1200 mV

13

24

16.5

29.5

20

38 kHz kHz

Note: If the 22 kHz tone parameters are lower or higher than the above limits, the TMON I²C bit is set to “1”.

32/38 Doc ID 022771 Rev 1

LNBH26

9 Package mechanical data

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at:

www.st.com

. ECOPACK is an ST trademark.

Table 20.

QFN24L (4 x 4 mm) mechanical data

Dim.

D

D2

E

E2 e

L

A

A1 b

Min.

0.80

0.00

0.18

3.90

2.55

3.90

2.55

0.45

0.25

(mm.)

Typ.

0.90

0.02

0.25

4.00

2.70

4.00

2.70

0.50

0.35

Max.

1.00

0.05

0.30

4.10

2.80

4.10

2.80

0.55

0.45

Doc ID 022771 Rev 1 33/38

Package mechanical data

Figure 13.

QFN24L (4 x 4 mm) package dimensions

LNBH26

34/38 Doc ID 022771 Rev 1

7596209_D

LNBH26 Package mechanical data

Dim.

N

T

Ao

Bo

A

C

D

Ko

Po

P

Tape & reel QFNxx/DFNxx (4x4) mechanical data

Min.

mm.

Typ.

Min.

Max.

330

13.2

inch.

Typ.

12.8

20.2

99

0.504

0.795

3.898

101

14.4

4.35

4.35

1.1

4

8

0.171

0.171

0.043

0.157

0.315

Max.

12.992

0.519

3.976

0.567

Doc ID 022771 Rev 1 35/38

Package mechanical data

Figure 14.

QFN24L (4 x 4) footprint recommended data (mm.)

LNBH26

36/38 Doc ID 022771 Rev 1

LNBH26

Table 21.

Document revision history

Date Revision

03-Feb-2012 1 Initial release.

Changes

Revision history

Doc ID 022771 Rev 1 37/38

LNBH26

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