STMicroelectronics LNBH25L Datasheet
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LNBH25L
LNB supply and control IC with step-up and I²C interface
Features
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Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @
0.5 A)
Selectable output current limit by external resistor
Compliant with main satellite receiver output voltage specifications
Accurate built-in 22 kHz tone generator suits widely accepted standards
22 kHz tone waveform integrity guaranteed also at no load condition
Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allowing low power losses
Overload and overtemperature internal protection with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
Applications
■
■
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STB satellite receivers
TV satellite receivers
PC card satellite receivers
Description
Intended for analog and digital satellite receivers/Sat-TV and Sat-PC cards, the
LNBH25L is a monolithic voltage regulator and interface IC, assembled in QFN24 (4x4) specifically designed to provide the 13/18 V power supply and the 22 kHz tone signalling to
Table 1.
Device summary
Order code Package
LNBH25LPQR QFN24 (4 x 4)
QFN24 (4 x 4 mm) the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count and low power dissipation together with a simple design and I²C standard interfacing.
Packaging
Tape and reel
February 2012 Doc ID 022634 Rev 2 1/28 www.st.com
28
Contents
Contents
LNBH25L
DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6
PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7
OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/28 Doc ID 022634 Rev 2
LNBH25L Contents
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Doc ID 022634 Rev 2 3/28
Block diagram
Figure 1.
Block diagram
ADDR SCL SDA
I2C Digital core
DSQIN
ISEL
Voltage reference
DAC
Drop control
Tone ctrl
Diagnostics
Protections
Current
Limit selection
GND BYP VCC
Linear
Regulator
AM10460v1
LX
PGND
VUP
VOUT
LNBH25L
4/28 Doc ID 022634 Rev 2
LNBH25L Application information
2.1
2.2
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (V
UP
) that let the integrated LDO post-regulator (generating the
13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
V
UP
- V
OUT
= 1 V typ.). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied V
CC
drops below a fixed threshold (4.7 V typically). The step-up converter soft-start function reduces the inrush current during startup. The SS time is internally fixed at 4ms typ. to switch from 0 to 13 V and 6 ms typ. to switch from 0 to 18 V.
DiSEqC data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards, and can be activated in 3 different ways:
1.
by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM = TEN = 1.
2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1.
3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.
Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the V
OUT
pin, by using the
LNBH25L integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25L tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible
22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the
LNBH25L activates the 22 kHz tone on the V
OUT
output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN
Figure 2
).
Figure 2.
Tone enable and disable timing (using external waveform)
DSQIN
~ 60 µs
Tone
Output
~ 1 µs
AM10426v1
Doc ID 022634 Rev 2 5/28
Application information
2.3
LNBH25L
Data encoding by external DiSEqC™ envelope control through the DSQIN pin
If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and
TEN = 1. In this way, the internal 22 kHz signal is superimposed to the V
OUT
DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH, the internal control circuit activates the 22 kHz tone output.
The 22 kHz tone on the V
OUT
pin is activated with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired (refer to
Figure 3
Figure 3.
Tone enable and disable timing (using envelope signal)
DSQIN
15 µs ~ 60 µs
Tone
Output
~ 6 µs
AM10427v1
2.4 Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation:
Equation 1
I
MAX
( typ .)
=
13915
RSEL
1 .
111 where RSEL is the resistor connected between ISEL and GND expressed in k
Ω
and
I
MAX
(typ.) is the typical current limit threshold expressed in mA. I
MAX
can be set up to
750 mA.
The linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal DATA1 register (see
Section 7.3
and
Table 13
for exact programmable values). Register writing is accessible via the I²C bus.
6/28 Doc ID 022634 Rev 2
LNBH25L
2.6
Application information
Diagnostic and protection functions
The LNBH25L has 3 diagnostic internal functions provided via the I²C bus, by reading 3 bits on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that is no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature and overload protection status (OTF and OLF). One bit is dedicated to the input voltage power not good function (PNG). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is done.
2.7 Surge protection and TVS diodes
The LNBH25L device is directly connected to the antenna cable in a set-top box.
Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually used, as shown in the following schematic, to protect the STB output circuits where the LNBH25L and other devices are electrically connected to the antenna cable.
Figure 4.
Surge protection circuit
2.8
2.9
For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically designed by ST. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details).
Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH25L is automatically reset at power-on. As long as the
V
CC
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all data register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the V
CC
rises above 4.8 V typ. the I²C interface becomes operative and the data registers can be configured by the main microprocessor.
PNG: input voltage minimum detection
When input voltage (V
CC
pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to
Table 12
for threshold details.
Doc ID 022634 Rev 2 7/28
Application information LNBH25L
2.10 OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for a T
ON
time of 90 ms, after which the output is set in shutdown for a T
OFF
time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register is set to “1”. After this time has elapsed, the output is resumed for a time T
ON
. At the end of T
ON
, if the overload is still detected, the protection circuit cycles again through T
OFF and T
ON
. At the end of a full T
ON
in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical
T
ON
+ T
OFF
time is 990 ms and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in a short-circuit condition, still ensuring excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and then switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current clamp limit is reached and returns LOW when the overload condition is cleared and a register reading is done.
After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
OUT
pin) is disabled. To reenable the output stage, the VSEL bits must be set again by the microprocessor, and the
OLF bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation.
2.11 OTF: thermal protection and diagnostic
The LNBH25L is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (V
OUT
pin) is disabled. To reenable the output stage, the VSEL bits must be set again by the microprocessor, while the
OTF bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.
8/28 Doc ID 022634 Rev 2
LNBH25L Pin configuration
Figure 5.
Pin connections (top view)
24 23 22 21
NC
20 19
GND DSQIN VUP VOUT GND
1 NC
2 GND
3 LX
4 PGND
5 NC
6 ADDR
LNBH25L
GND 18
VCC 17
VBYP 16
GND 15
NC 14
NC 13
SCL SDA ISEL NC NC NC
7 8 9 10 11 12
AM10461v1
Table 2.
Pin n°
3
4
6
7
8
9
2,15, 18, 19,
23
Pin description
Symbol Name
LX
P-GND
ADDR
SCL
SDA
ISEL
Pin function
N-MOS drain Integrated N-channel Power MOSFET drain.
Power ground
DC-DC converter power ground. To be connected directly to the
Epad.
Address setting
Serial clock
Two I²C bus addresses available by setting the address pin level voltage. See
.
Clock from I²C bus.
Serial data
Current selection
Bi-directional data from/to the I²C bus.
The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold. Refer to
.
GND Analog ground Analog circuits ground. To be connected directly to the Epad.
16
17
20
21
BYP
V
CC
V
OUT
V
UP
Bypass capacitor
Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.
Supply input 8 to 16 V IC DC-DC power supply.
LNB output port
Step-up voltage
Output of the integrated very low drop linear regulator. See Table 13
for voltage selection and description.
Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor.
Doc ID 022634 Rev 2 9/28
Pin configuration LNBH25L
Table 2.
Pin n°
Pin description (continued)
Symbol Name Pin function
22
Epad
1, 5, 10, 11,
12, 13, 14, 24
DSQIN
Epad
N.C.
DSQIN for
DiSEqC envelope input or
External 22 kHz
TTL input
It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM I²C bit setting as follows:
EXTM=0, TEN=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH25L uses this code to modulate the internally generated 22 kHz carrier.
EXTM=TEN=1: it accepts external 22 kHz logic signals which
activate the 22 kHz tone output (refer to Section 2.3
Pull up high if the tone output is activated only by the TEN I²C bit.
Exposed pad
To be connected with power grounds and to the ground layer through vias to dissipate the heat.
Not internally connected
Not internally connected pins. These pins can be connected to GND to improve thermal performances.
10/28 Doc ID 022634 Rev 2
LNBH25L Maximum ratings
Table 3.
Symbol
V
CC
V
UP
I
OUT
V
OUT
V
I
LX
V
BYP
ISEL
T
STG
T
J
ESD
Absolute maximum ratings
Parameter
DC power supply input voltage pins
DC input voltage
Output current
DC output pin voltage
Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins)
LX input voltage
Internal reference pin voltage
Current selection pin voltage
Storage temperature range
Operating junction temperature range
ESD rating with human body model (HBM) all pins, unless power output pins
ESD rating with human body model (HBM) for power output pins
Value
-0.3 to 20
-0.3 to 40
Internally limited
-0.3 to 40
-0.3 to 7
-0.3 to 30
-0.3 to 4.6
-0.3 to 3.5
-50 to 150
-25 to 125
2
4
Unit
V
V mA
V
V
V
V
V
°C
°C kV
Table 4.
Symbol
R thJC
R thJA
Thermal data
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient with device soldered on 2s2p 4layer PCB provided with thermal vias below exposed pad.
Note:
Value
2
40
Unit
°C/W
°C/W
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal.
Doc ID 022634 Rev 2 11/28
Typical application circuits LNBH25L
Figure 6.
DiSEqC 1.x application circuit
D2 to LNB
21 Vup
Vout 20
D1
C2 C3
C5 D3
3 LX
LNBH25L
L1
Vin
12V
C1 C4
17 Vcc
DiSEqC
22KHz TTL or
DiSEqC
Envelope TTL
22 DSQIN
R1 (RSEL)
I 2 C Bus
{ 8
7
6
9
ADDR
SDA
SCL
ISEL
P-GND A-GND
4 15
Byp
16
C7
AM10462v1
Table 5.
Component
Typical application circuit bill of material
Notes
R1 (RSEL)
SMD resistor. Refer to Table 12
and ISEL pin description in
C1, C2 > 25 V electrolytic capacitor, 100 µF is suitable.
C3
C5
From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.
From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.
C4, C7
D1
D3
D2
L1
220 nF ceramic capacitors.
STPS130A or similar schottky diode.
BAT54, BAT43, 1N5818, or any low power schottky diode with I
F
(AV) > 0.2 A,
V
RRM
> 25 V, V
F
< 0.5 V. To be placed as close as possible to V
OUT
pin.
1N4001-07, S1A-S1M, or any similar general purpose rectifier.
10 µH inductor with I sat
> I peak
where I peak
is the boost converter peak current.
12/28 Doc ID 022634 Rev 2
LNBH25L
6 I²C bus interface
I²C bus interface
Data transmission from the main microprocessor to the LNBH25L and vice versa takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
6.2
As shown in
Figure 7
, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and stop condition
As shown in
Figure 8
, a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
6.4 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
Figure 9
). The peripheral (LNBH25L) that acknowledges must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed must generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH25L does not generate an acknowledge if the V
CC
supply is below the undervoltage lockout threshold (4.7
V typ.).
To avoid detection of the LNBH25L acknowledges, the microprocessor can use a simpler transmission: it simply waits one clock cycle without checking the slave acknowledging, and sends the new data. This approach is of course less protected from misworking and decreases the noise immunity.
Doc ID 022634 Rev 2 13/28
I²C bus interface
Figure 7.
Data validity on the I²C bus
LNBH25L
Figure 8.
Timing diagram of I²C bus
Figure 9.
Acknowledge on the I²C bus
14/28 Doc ID 022634 Rev 2
LNBH25L
7 I²C interface protocol
I²C interface protocol
MSB
The LNBH25L interface protocol is made up of:
●
●
●
●
●
●
● a start condition (S) a chip address byte with the LSB bit R/W = 0 a register address (internal address of the first register to be accessed) a sequence of data (byte to write in the addressed internal register + acknowledge) the following bytes, if any, to be written in successive internal registers a stop condition (P). The transfer lasts until a stop bit is encountered the LNBH25L, as slave, acknowledges every byte transfer.
Figure 10.
Example of writing procedure starting with first data address 0x2
(a)
CHIP ADDRESS
LSB
REGISTER ADDRESS
MSB LSB
S 0 0 0 1 0 0 X 0 0 0 0 0 X X X
MSB
DATA 1
Add=0x2
LSB MSB
DATA 2
Add=0x3
LSB MSB
DATA 3
Add=0x4
LSB MSB
DATA 4
Add=0x5
LSB
P
AM1046 3 v1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see
Table 15
select the REGISTER ADDRESS (see
Table 6
Table 11
a.
The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped from the master by sending a stop condition after any acknowledge bit.
Doc ID 022634 Rev 2 15/28
I²C interface protocol LNBH25L
●
●
●
●
●
In read mode the bytes sequence must be as follows:
● a start condition (S) a chip address byte with the LSB bit R/W=0 the register address byte of the internal first register to be accessed a stop condition (P) a new master transmission with the chip address byte and the LSB bit R/W=1
● after the acknowledge the LNBH25L starts to send the addressed register content. As long as the master keeps the acknowledge LOW, the LNBH25L transmits the next address register byte content.
the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit.
Figure 11.
Example of reading procedure starting with first status address 0X0
(b)
MSB
CHIP ADDRESS
LSB
REGISTER ADDRESS
MSB LSB MSB
CHIP ADDRESS
LSB
S 0 0 0 1 0 0 X 0 0 0 0 0 X X X P S 0 0 0 1 0 0 X
MSB
STATUS 1
Add=0x0
LSB MSB
STATUS 2
Add=0x1
LSB
16/28
MSB
DATA 1
Add=0x2
LSB MSB
DATA 2
Add=0x3
LSB MSB
DATA 3
Add=0x4
LSB MSB
DATA 4
Add=0x5
LSB
P
AM10464v1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see
Table 15
select the REGISTER ADDRESS (see
Table 6
Table 11
b.
The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped from the master by sending a stop condition after any acknowledge bit.
Doc ID 022634 Rev 2
LNBH25L I²C interface protocol
Table 6.
BIT
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(MSB)
VSEL1
VSEL2
VSEL3
VSEL4
N/A
N/A
N/A
N/A
The data 1..4 registers can be addressed both in write and read mode. In read mode they return the last writing byte status received in the previous write transmission.
The following tables provide the register address values of data 1..4 and a function description of each bit.
Data 1 (read/write register. Register address = 0X2)
Name Value Description
0/1
0/1
0/1
0/1
0
0
0
0
Output voltage selection bits. (Refer to Table 13 )
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
Table 7.
BIT
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(MSB)
N/A = Reserved bit.
All bits reset to “0” at power-on.
Data 2 (read/write register. Register address = 0X3)
Name Value Description
TEN
N/A
EXTM
N/A
N/A
N/A
N/A
0
0
0
0
0
1
0
0
1
22 kHz tone enabled. Tone output controlled by the DSQIN pin
22 kHz tone output disabled
Reserved. Keep to “0”
DSQIN input pin is set to receive external 22 kHz TTL signal source
DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
N/A 0 Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
Doc ID 022634 Rev 2 17/28
I²C interface protocol
Table 8.
BIT
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(MSB)
Data 3 (read/write register. Register address = 0X4)
Name Value Description
N/A
N/A
PCL
N/A
N/A
N/A
N/A
N/A
0
0
0
0
0
0
1
0
0
Reserved. Keep to “0”
Reserved. Keep to “0”
Pulsed (Dynamic) LNB output current limiting is deactivated
Pulsed (Dynamic) LNB output current limiting is activated
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
LNBH25L
Table 9.
BIT
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(MSB)
N/A = Reserved bit.
All bits reset to “0” at power-on.
Data 4 (read/write register. Register address = 0X5)
Name Value Description
N/A
N/A
N/A
OLR
N/A
N/A
THERM
N/A
0
0
0
0
0
1
0
1
0
0
Reserved. Keep to “0”
Reserved. Keep to “0”
Reserved. Keep to “0”
In case of overload protection activation (OLF=1), all VSEL 1..4 bits are reset to
“0” and LNB output (V
OUT
pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0).
In case of overload protection activation (OLF=1) the LNB output (V
OUT
pin) is automatically enabled as soon as the overload condition is removed (OLF=0) with the previous VSEL bits setting.
Reserved. Keep to “0”
Reserved. Keep to “0”
If thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and
LNB output (V
OUT
pin) is disabled. The VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=0).
In case of thermal protection activation (OTF=1) the LNB output (V
OUT
pin) is automatically enabled as soon as the overtemperature condition is removed
(OTF=0) with the previous VSEL bits setting.
Reserved. Keep to “0”
18/28
N/A = Reserved bit.
All bits reset to “0” at power-on.
Doc ID 022634 Rev 2
LNBH25L I²C interface protocol
The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables.
Table 10.
STATUS 1 (Read register. Register address = 0X0)
BIT Name Value Description
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(MSB)
OLF
N/A
N/A
N/A
N/A
N/A
OTF
PNG
1
0
-
-
-
-
-
1
0
1
0
V
OUT
pin overload protection has been triggered (I
OUT
> I
MAX the overload operation settings (PCL bit).
for
No overload protection has been triggered to the V
OUT
pin (I
OUT
< I
MAX
).
Reserved
Reserved
Reserved
Reserved
Reserved
Junction overtemperature is detected, T
J
.
> 150 °C. See also the THERM bit
Junction overtemperature not detected, T
J
< 135 °C. T
J
is below thermal protection threshold.
Input voltage (V
CC
pin) lower than LPD minimum thresholds. Refer to
.
Input voltage (V
CC
pin) higher than LPD thresholds. Refer to
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 11.
STATUS 2 (Read register. Register address = 0X1)
BIT Name Value Description
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(MSB)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
N/A = Reserved bit.
All bits reset to “0” at power-on.
Doc ID 022634 Rev 2 19/28
Electrical characteristics LNBH25L
Section 5
, T
J
from 0 to 85 °C, all data 1..4 register bits set to 0 unless VSEL1 = 1,
RSEL = 16.2 k
Ω
, DSQIN = LOW, V
IN
= 12 V, I
OUT
= 50 mA, unless otherwise stated. Typical values are referred to T
J
= 25 °C. V
OUT
= V
OUT
pin voltage. See software description section for I²C access to the system register (
Section 6
Section 7
.
Table 12.
Electrical characteristics
Symbol Parameter
Supply voltage
(1)
Test conditions
V
IN
I
IN
Supply current
I
OUT
=0 mA
22 kHz tone enabled (TEN=1,
DSQIN=High), I
OUT
=0 mA
VSEL1=VSEL2=VSEL3=VSEL4=0
V
OUT
V
OUT
V
OUT
I
I
MAX
SC
SS
SS
T13-18
T18-13
Output voltage total accuracy Valid at any V
OUT
selected level
Line regulation
Load regulation
Output current limiting thresholds
Output short-circuit current
V
IN
=8 to 16 V
I
OUT
from 50 to 500 mA
RSEL = 16.2 k
Ω
RSEL = 22 k Ω
RSEL= 16.2 k
Ω
Soft-start time
Soft-start time
Soft transition rise time
Soft transition fall time
V
OUT
from 0 to 13 V
V
OUT
from 0 to 18 V
V
OUT
from 13V to 18 V
V
OUT
from 18V to 13 V
T
OFF
Dynamic overload protection
OFF time
PCL=0, output shorted
A
T
ON
TONE
Dynamic overload protection
ON time
PCL=0, output shorted
Tone amplitude
DSQIN=High, EXTM=0, TEN=1
I
OUT
from 0 to 500 mA
C
BUS
from 0 to 750 nF
Tone frequency F
TONE
D
TONE t r
, t f
Eff
DC/DC
F
SW
UVLO
Tone duty cycle
Tone rise or fall time
(2)
DSQIN=High, EXTM=0, TEN=1
DC-DC converter efficiency I
OUT
=500mA
DC-DC converter switching frequency
Undervoltage lockout thresholds
UVLO threshold rising
UVLO threshold falling
V
LP
Low power diagnostic (LPD) thresholds
V
LP
threshold rising
V
LP
threshold falling
20/28 Doc ID 022634 Rev 2
Min.
8
-3.5
500
350
Typ.
Max.
Unit
12
6
16 V mA
10
1
75
0.55
0.675
20
43
5
4.8
4.7
7.2
6.7
350
4
6
1.5
1.5
900
T
OFF
/10
22
50
8
93
440
+3.5
40
100
750
550
24
57
15
% mV mA kHz
%
µs
% mA ms ms ms ms ms
0.8
V
PP kHz
V
V
LNBH25L Electrical characteristics
Table 12.
Electrical characteristics (continued)
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
V
IL
V
IH
I
IH
I
OBK
DSQIN, pin logic low
DSQIN, pin logic high
DSQIN, pin input current
Output backward current
V
IH
=5 V
All VSELx=0, V
OBK
=30 V
2
15
-3
0.8
6
V
V
µA mA
I
SINK
I
SINK_TIME-
OUT
Output low-side sink current V
Low-side sink current timeout V
OUT
OUT
forced at V
forced at V
OUT_nom
OUT_nom
+0.1 V
+0.1 V
70
10 mA ms
I
REV
Max. reverse current
V
OUT
forced at V
OUT_nom
+0.1 V, after I
SINK_TIME-OUT is elapsed
2 mA
T
SHDN
Δ T
SHDN
Thermal shutdown threshold
Thermal shutdown hysteresis
150
15
1.
In applications where (V
CC
-V
OUT
) >1.3 V, the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design.
2.
Guaranteed by design.
°C
°C
Table 13.
Output voltage selection table (Data1 register, write mode)
VSEL4 VSEL3 VSEL2 VSEL1
V
OUT min.
V
OUT
pin voltage
V
OUT max.
Function
V
OUT
disabled. LNBH25L set in standby
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
0
12.545
12.867
13.188
13.51
0.000
13.000
13.333
13.667
14.000
13.455
13.800
14.145
14.490
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
17.515
17.836
18.158
18.48
18.150
18.483
18.817
19.150
18.785
19.130
19.475
19.820
Doc ID 022634 Rev 2 21/28
Electrical characteristics LNBH25L
T
J
from 0 to 85 °C, V
I
= 12 V.
Table 14.
I²C electrical characteristics
Symbol Parameter Test conditions
V
IL
V
IH
I
IN
V
OL
Low level input voltage
High level input voltage
SDA, SCL
SDA, SCL
Input current
Low level output voltage
(1)
SDA, SCL, V
IN
= 0.4 to 4.5 V
SDA (open drain), I
OL
= 6 mA
F
MAX
Maximum clock frequency
1.
Guaranteed by design.
SCL
Min.
Typ.
Max.
Unit
0.8
2
-10
400
10
0.6
V
V
µA
V kHz
T
J
from 0 to 85 °C, V
I
= 12 V.
Table 15.
Address pin characteristics
Symbol Parameter
V
ADDR-1
V
ADDR-2
Test condition
“0001000(R/W)” address pin voltage range
R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)
“0001001(R/W)” address pin voltage range
R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)
Min.
Typ.
Max.
0
2
0.8
5
Unit
V
V
22/28 Doc ID 022634 Rev 2
LNBH25L
9 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at:
www.st.com
. ECOPACK is an ST trademark.
Table 16.
QFN24L (4 x 4 mm) mechanical data
Dim.
D
D2
E
E2 e
L
A
A1 b
Min.
0.80
0.00
0.18
3.90
2.55
3.90
2.55
0.45
0.25
(mm)
Typ.
0.90
0.02
0.25
4.00
2.70
4.00
2.70
0.50
0.35
Max.
1.00
0.05
0.30
4.10
2.80
4.10
2.80
0.55
0.45
Doc ID 022634 Rev 2 23/28
Package mechanical data
Figure 12.
QFN24L (4 x 4 mm) package dimensions
LNBH25L
24/28 Doc ID 022634 Rev 2
7596209_D
LNBH25L Package mechanical data
Dim.
N
T
Ao
Bo
A
C
D
Ko
Po
P
Tape & reel QFNxx/DFNxx (4x4) mechanical data
Min.
mm.
Typ.
Min.
Max.
33 0
1 3 .2
inch.
Typ.
12.
8
20.2
99
0.504
0.7
9 5
3 .
898 101
14.4
4.
3 5
4.
3 5
1.1
4
8
0.171
0.171
0.04
3
0.157
0.
3 15
Max.
12.
99 2
0.51
9
3 .
9 76
0.567
Doc ID 022634 Rev 2 25/28
Package mechanical data
Figure 13.
QFN24L (4 x 4) footprint recommended data (mm.)
LNBH25L
26/28 Doc ID 022634 Rev 2
LNBH25L
Table 17.
Document revision history
Date
09-Jan-2012
15-Feb-2012
Revision
1
2
Changes
Initial release.
Modified: D1 and D3
.
Revision history
Doc ID 022634 Rev 2 27/28
LNBH25L
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28/28 Doc ID 022634 Rev 2
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