STMicroelectronics LNBH30 Datasheet
Advertentie
Advertentie
LNBH30
LNB supply and control IC with step-up and I²C interface
Datasheet - production data
Overload and overtemperature internal protection with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
Applications
STB satellite receivers
TV satellite receivers
PC card satellite receivers Features
Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ.
93% @ 0.5 A)
Selectable output current limit by external resistor
Compliant with main satellite receiver output voltage specifications
EXTM pin, auxiliary 44 kHz modulation input extends design flexibility
Low drop post regulator and high efficiency step-up PWM with integrated power NMOS allowing low power losses
Description
Intended for the Japanese market for digital dual satellite receivers/Sat-TV, and Sat-PC cards, the
LNBH30 is a monolithic voltage regulator and interface IC, assembled in QFN16 (4x4 mm) specifically designed to provide the power supply and the 44 kHz tone signaling to the LNB downconverter in the antenna dish or to the multiswitch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.
Table 1: Device summary
Order code Package Packing
LNBH30QTR QFN16 (4x4) Tape and reel
October 2017 DocID023739 Rev 3
This is information on a product in full production.
1/27 www.st.com
Contents
Contents
LNBH30
1 Block diagram .................................................................................. 5
2 Application information .................................................................. 6
Data encoding ................................................................................... 6
Output current limit selection ............................................................. 6
Output voltage selection .................................................................... 6
COMP: boost capacitors and inductor ............................................... 6
Diagnostic and protection functions .................................................. 7
VMON: output voltage diagnostic ...................................................... 7
PDO: overcurrent detection on output pull-down stage ..................... 7
Power-on I²C interface reset and undervoltage lockout .................... 7
PNG: input voltage minimum detection ............................................. 7
OLF: overcurrent and short-circuit protection and diagnostic ............ 7
OTF: thermal protection and diagnostic ............................................ 8
3 Pin configuration ............................................................................. 9
4 Maximum ratings ........................................................................... 11
5 Typical application circuits ........................................................... 12
6 I²C bus interface ............................................................................ 14
Start and stop condition .................................................................. 14
Acknowledge ................................................................................... 14
Transmission without acknowledge ................................................. 14
7 I²C interface protocol .................................................................... 16
Write mode transmission ................................................................. 16
Read mode transmission ................................................................ 16
Data registers .................................................................................. 17
Status registers ............................................................................... 18
8 Electrical characteristics .............................................................. 20
9 Package information ..................................................................... 23
QFN16 (4x4 mm) package information ........................................... 24
10 Revision history ............................................................................ 26
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LNBH30
List of tables
List of tables
DocID023739 Rev 3 3/27
List of figures
List of figures
LNBH30
4/27 DocID023739 Rev 3
LNBH30
1 Block diagram
Figure 1: Block diagram
Block diagram
DocID023739 Rev 3 5/27
Application information
2
2.1
2.2
2.3
2.4
Application information
LNBH30
This IC has a built-in DC-DC step-up converter that, from a single source of typically 12 V, generates the voltages (V
UP
) that allow the linear post-regulator to work at a minimum dissipated power of 0.5 W typ. @ 500 mA load (it is internally kept at V
UP
- V
OUT
= 1 V typ.).
An undervoltage lockout circuit disables the whole circuit when the supplied V
CC
drops below a fixed threshold (4.7 V typ.). The step-up converter is provided with a soft-start function which reduces the in-rush current during startup. The SS time is internally fixed at
5 ms typ. to switch from 0 to 15 V.
Data encoding
In order to improve design flexibility, an analogical modulation input pin is available (EXTM) to generate the 44 kHz tone superimposed to the VOUT DC output voltage. An appropriate
DC blocking capacitor must be used to couple the 44 kHz modulating signal source to the
EXTM pin. The EXTM pin modulates the VOUT voltage through the series decoupling capacitor, so that:
VOUT(AC) = VEXTM(AC) x GEXTM where: VOUT(AC) and VEXTM(AC) are, respectively, the peak-to-peak AC voltage on the VOUT pin and on the EXTM pin, while GEXTM is the voltage gain between the EXTM voltage and VOUT signal.
Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit as per the following equation:
𝐼
𝑀𝐴𝑋.
(𝑡𝑦𝑝. ) =
13915
𝑅𝑆𝐸𝐿 1.111
where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
I
MAX.
(typ.) is the typical current limit threshold expressed in mA. I
MAX
can be set up to
0.55 A.
Output voltage selection
The linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using 3 bits of the internal DATA register see
Section 7.1: "Write mode transmission"
bus.
COMP: boost capacitors and inductor
The DC-DC converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacitors (V
UP
pin). For this purpose, one I²C bit in the DATA register (see COMP) can be set to “1” or “0” as follows:
COMP = 0 for electrolytic capacitors
COMP = 1 for ceramic capacitors
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LNBH30
2.5
2.6
Application information
Diagnostic and protection functions
The LNBH30 has 5 diagnostic internal functions provided by the I²C bus, by reading 5 bits on the status register (in read mode). All the diagnostic bits are, in normal operation, set to
LOW. Two diagnostic bits are dedicated to the overtemperature and overload protection status (OTF and OLF) while the remaining 3 bits are dedicated to the output voltage level
(VMON), to external voltage source presence on the VOUT pin (PDO) and to the input voltage power not good function (PNG). Once the OLF (or OTF or PNG) bit is active (set to
“1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is performed.
VMON: output voltage diagnostic
When the device output voltage is active (VOUT pin), its value is internally monitored and, as long as the output voltage level is below the guaranteed limits, the relevant VMON I²C
2.7
2.8
2.9
PDO: overcurrent detection on output pull-down stage
When an overcurrent occurs on the pull-down output stage due to an external voltage source greater than the LNBH30 nominal V
OUT
, and for a time longer than I
SINK_TIME_OUT
(10 ms typ.), the corresponding PDO I²C bit is set to “1”. This may happen due to an external voltage source presence on the LNB output (VOUT pin).
For current threshold and deglitch time details, see Table 9: "Electrical characteristics" .
Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH30 is automatically reset at power-on. As long as the
V
CC
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the V
CC
rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor.
PNG: input voltage minimum detection
When input voltage (V
CC
pin) is lower than LPD (low power diagnostic) minimum
thresholds, the PNG I²C bit is set to “1”. Refer to Section 8: "Electrical characteristics" for
threshold details.
2.10 OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. The overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T
ON
time (90 ms) and after that, the output is set in shutdown for a T
OFF
time of typically 900 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the status register is set to “1”. After this time has elapsed, the involved output is resumed for a time
T
ON
. At the end of T
ON
, if the overload is still detected, the protection circuit cycles again through T
OFF
and T
ON
. At the end of a full T
ON
in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after register reading is performed. Typical T
ON
+T
OFF
time is 990 ms and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on startup in most conditions.
DocID023739 Rev 3 7/27
Application information
2.11 OTF: thermal protection and diagnostic
LNBH30
The LNBH30 is also protected against overheating: when the junction temperature exceeds
150 °C (typ.), the step-up converter and the liner regulators are shut off, the diagnostic OTF bit in the status register is set to “1”. As soon as the overtemperature condition is removed, normal operation is automatically reenabled while the OTF bit is reset to “0” after a register reading operation.
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LNBH30
3 Pin configuration
Figure 2: Pin connections (top view)
Pin configuration
3
5
6
7
8
9
Pin
2
10
12
13
Symbol
PGND
EXTM
ADDR
SCL
SDA
ISEL
GND
BYP
VCC
VOUT
Table 2: Pin description
Name Pin function
Power ground
External 44 kHz tone input
Address setting
DC-DC converter power ground. To be connected directly to the exposed pad
The “external tone modulation” input acts on the integrated linear regulator loop to superimpose an external 44 kHz signal to the
VOUT pin DC voltage. DC decoupling is needed for AC source
Two I 2 C bus addresses available by setting the address pin level
voltage. See Table 11: "Address pin characteristics"
Serial clock Clock from I²C bus
Serial data
Current selection
Bi-directional data from/to I²C bus
The resistor “RSEL” connected between ISEL and GND defines
the linear regulator current limit threshold. Refer to Section 2.2:
"Output current limit selection"
Analog ground
Bypass capacitor
Analog circuit ground. To be connected directly to the exposed pad
Needed for internal pre-regulator filtering. The BYP pin is intended to connect an external ceramic capacitor only. Any connection of this pin to external current or voltage sources may cause permanent damage to the device
Supply input 10 to 17.5 V IC DC-DC power supply
LNB output port
Output of the integrated very low drop linear regulator. See
Table 8: "Output voltage selection (data register, write mode)"
DocID023739 Rev 3 9/27
Pin configuration
Pin
14
16
1,4,11,15
Epad
Symbol
VUP
LX
NC
Epad
LNBH30
Name Pin function
Step-up voltage
Input of linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor
NMOS drain Integrated N-channel power MOSFET drain
Not internally connected output
Not internally connected pins. These pins may be connected to
GND to improve thermal performance
Exposed pad
To be connected with power ground and to the ground layer through vias to dissipate heat
10/27 DocID023739 Rev 3
LNBH30
4
Maximum ratings
Maximum ratings
Symbol
Table 3: Absolute maximum ratings
Parameter
V
CC
V
UP
I
OUT
DC power supply input voltage pins
DC input voltage
Output current
V
OUT
V
I
DC output pin voltage
Logic input pin voltage (SDA, SCL, DSQIN, ADDR pins)
V
EXTM
EXTM pin voltage
LX LX input voltage
V
BYP
ISEL
T
STG
T
J
Internal reference pin voltage
Current selection pin voltage
Storage temperature range
Operating junction temperature range
ESD
ESD rating with human body model (HBM) for all pins, except power output pins
ESD rating with human body model (HBM) for power output pins
Symbol
Table 4: Thermal data
Parameter
RthJC Thermal resistance junction-case
RthJA
Thermal resistance junction-ambient with device soldered on
2s2p 4-layer PCB provided with thermal vias below exposed pad
Value
-0.3 to 20
-0.3 to 40
Internally limited
-0.3 to 40
-0.3 to 7
-0.3 to 2
-0.3 to 30
-0.3 to 4.6
-0.3 to 3.5
-50 to 150
-25 to 125
2
4
Value
2
40
Unit
V
V mA
V
V
°C
°C
V
V
V
V kV
Unit
°C/W
°C/W
Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability. All voltage values are with respect to network ground terminal.
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Typical application circuits
5 Typical application circuits
Figure 3: Application circuit
LNBH30
12/27
Component
C1
C2
C3
C5
C4, C6
C7
D1
D2
D3
Table 5: Typical application circuit bill of material
Notes
> 25 V electrolytic capacitor, 100 µF or higher is suitable or
> 25 V ceramic capacitor, 10 µF or higher is suitable
With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable or with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is suitable
2.2 µF ceramic capacitor placed as close as possible to VUP pins. Higher values allow lower DC-DC noise
From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise
220 nF ceramic capacitors
100 nF or higher is suitable
STPS130A or similar Schottky diode
1N4001-07, S1A-S1M, or any similar general purpose rectifier
BAT54, BAT43, 1N5818, or any low power Schottky diode with I
F
(AV) > 0.2
A, V
RRM
> 25 V, V
F
< 0.5 V. To be placed as close as possible to VOUT pin
DocID023739 Rev 3
LNBH30
Component
L1
FB1
Typical application circuits
Notes
With COMP=0, use 10 µH inductor with I
SAT
> I
PEAK
where I
PEAK
is the boost converter peak current or with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with I
SAT
> I
PEAK
where
I
PEAK
is the boost converter peak current
Optional. Ferrite bead to be added if lower DC-DC noise is required
DocID023739 Rev 3 13/27
I²C bus interface
6
6.1
6.2
6.3
6.4
6.5
I²C bus interface
LNBH30
Data transmission from the main microprocessor to the LNBH30 and vice versa takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors must be externally connected to positive supply voltage).
Data validity
As shown in Figure 4: "Data validity on the I²C bus" , the data on the SDA line must be
stable during the high semi-period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and stop condition
As shown in Figure 5: "Timing diagram of I²C bus" , a start condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before than each START condition.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 6: "Acknowledge on the I²C bus" ). The peripheral
(LNBH30), which acknowledges, must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral, which has been addressed, must generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the nine th clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH30 does not generate acknowledge if the V
CC
supply is below the undervoltage lockout threshold (4.7 V typ.).
Transmission without acknowledge
If detection of the acknowledge of the LNBH30 is not required, the microprocessor can use a simpler transmission: it simply waits for one clock without checking the slave acknowledging, and sends the new data. This approach is of course less protected from misworking and decreases noise immunity.
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LNBH30
Figure 4: Data validity on the I²C bus
I²C bus interface
Figure 5: Timing diagram of I²C bus
Figure 6: Acknowledge on the I²C bus
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I²C interface protocol
7
7.1
I²C interface protocol
LNBH30
Write mode transmission
The LNBH30 interface protocol is made up of:
a start condition (S)
a chip address byte with the LSB bit R/W = 0
a register address (internal address of the first register to be accessed)
a sequence of data (byte to write to the addressed internal register + acknowledge)
a stop condition (P). The transfer lasts until a stop bit is encountered the LNBH30, as slave, acknowledges every byte transfer
Figure 7: Example of writing procedure starting with first data address 0x1
7.2
ACK = acknowledge
S = start
P = stop
R/W = 1/0, read/write bit
X = 0/1, set the values to select the chip address
Only one data register address 0x1 is available for the writing procedure.
Read mode transmission
In read mode the byte sequence must be as follows:
a start condition (S)
a chip address byte with the LSB bit R/W=0
the register address byte of the internal first register to be accessed
a stop condition (P)
a new master transmission with the chip address byte and the LSB bit R/W=1
after the acknowledge the LNBH30 starts sending the addressed register content. As long as the master keeps the acknowledge LOW, the LNBH30 transmits the next address register byte content
the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit
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LNBH30 I²C interface protocol
Figure 8: Example of reading procedure starting with first status address 0x0
7.3
ACK = acknowledge
S = start
P = stop
R/W = 1/0, read/write bit
X = 0/1, sets the values to select the chip address and to select the register address (0x0 for status register and 0x1 for data register)
The reading procedure can start from any register address (status or data) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped by the master by sending a stop condition after any acknowledge bit.
Data registers
The data register can be addressed both to write and read mode. In read mode it returns the last writing byte status received in the previous write transmission.
The following table provides the data register values and a function description of each bit.
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Table 6: Data (read/write register, register address = 0x1)
Name Value Description
VSEL0
VSEL1
VSEL2
0/1
0/1
0/1
Output voltage selection bits
COMP
N/A
0/1
0
DC-
DC converter internal compensation: set to “0” to use standard ESR capacitors (VUP pin)
Set to “1” to use very low ESR capacitors or ceramic caps
(VUP pin)
Reserved. Keep to “0”
DocID023739 Rev 3 17/27
I²C interface protocol
Bit Name Value
Bit 5
Bit 6
Bit 7(MSB)
N/A
N/A
N/A
0
0
0
N/A=reserved bit
All bits reset to "0" at power-on
7.4
Description
LNBH30
Status registers
The status register can be only addressed to read mode and provides the diagnostic functions described in the following tables.
Bit
Table 7: Status (read register, register address = 0x0)
Name Value Description
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
OLF
OTF
VMON
PNG
PDO
1
0
1
0
1
0
1
0
1
0
Output short-circuit or VOUT pin overload protection has been triggered (I
OUT
> I
MAX
)
No overload protection has been triggered to
VOUT pin (I
OUT
< I
MAX
)
Junction overtemperature is detected, T
J
> 150 °C
Junction overtemperature is not detected, T
J
<
135 °C. T
J
is below thermal protection threshold
Output voltage (VOUT pin) lower than VMON
specification thresholds. Refer to Table 9:
Output voltage (VOUT pin) is within the VMON specifications
Input voltage (VCC pin) lower than LPD minimum
thresholds. Refer to Table 9: "Electrical characteristics"
Input voltage (VCC pin) higher than LPD minimum
thresholds. Refer to Table 9: "Electrical characteristics"
Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (VOUT pin)
No overcurrent detected on output pull-down stage
Bit 5
Bit 6
Bit 7 (MSB)
N/A = reserved bit
N/A
N/A
N/A
All bits reset to 0 at power-on
-
-
-
Reserved
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LNBH30
1
1
1
0
0
0
1
I²C interface protocol
Table 8: Output voltage selection (data register, write mode)
VSEL2 VSEL1 VSEL0 VOUT min.
VOUT pin voltage
VOUT max. Function
0 0 0 0.000
VOUT disabled. The
LNBH30 is set in standby mode
0
1
1
0
1
1
0
1
0
1
1
0
1
0
11.387
11.580
11.900
14.475
14.796
15.119
15.440
11.800
12.000
12.333
15.000
15.333
15.667
16.000
12.213
12.420
12.765
15.525
15.870
16.215
16.560
DocID023739 Rev 3 19/27
Electrical characteristics
8 Electrical characteristics
LNBH30
Refer to Section 5: "Typical application circuits" , T
J
from 0 to 85 °C, data register bits set to
0 except VSEL0 = 1, RSEL = 16.2 kΩ, V
IN
= 12 V, I
OUT
= 50 mA, unless otherwise stated.
Typical values are referred to T
J
= 25 °C. V
OUT
= VOUT pin voltage. See Section 7: "I²C interface protocol" .
Symbol Parameter
Table 9: Electrical characteristics
Test conditions Min. Typ. Max. Unit
V
IN
10 17.5 V
I
IN
V
OUT
V
OUT
V
OUT
I
MAX
I
SC
SS
SS
T11-15
T15-11
T
OFF
T
ON
G
EXTM
V
EXTM
Z
EXTM
Eff
DC/DC
F
SW
UVLO
V
LPD
Supply voltage
Supply current
I
OUT
= 0 mA
VSEL0=VSEL1=VSEL2=0
Output voltage total accuracy
Line regulation
Load regulation
Output current limiting thresholds
Valid at any V
OUT
selected level
V
IN
= 8 to 16 V
I
OUT
from 50 to 500 mA
RSEL = 16.2 kΩ
RSEL = 22 kΩ
Output shortcircuit current
Soft-start time
Soft-start time
Soft transition rise time
Soft transition fall time
Dynamic overload protection off-time
Dynamic overload protection on-time
External modulation gain
External modulation input voltage
External modulation impedance
DC-DC converter efficiency
DC-DC converter switching frequency
I
RSEL = 16.2 kΩ
V
V
V
V
Δ
OUT
OUT
OUT
OUT
OUT
from 0 to 11.8 V
from 0 to 15 V
from 11.8 V to 15 V
from 15 V to 11.8 V
Output shorted
Output shorted
VOUT
/Δ
VEXTM
, @44 kHz
= 500 mA
Undervoltage lockout thresholds
Low power
UVLO threshold rising
UVLO threshold falling
V
LPD
threshold rising
-3.5
500
350
12
6
1
650
400
4
5
1.5
1.5
900
T
OFF
/10
7.5
230
93
440
4.8
4.7
7.2
+3.5
40
100
750
550 mA
% mV mA mA ms ms ms ms ms
400 mVpp
Ω
% kHz
V
V
20/27 DocID023739 Rev 3
LNBH30
Symbol
I
OBK
I
SINK
I
SINK_TIME-OUT
I
REV
T
SHDN
ΔT
SHDN
Parameter diagnostic (LPD) thresholds
Output backward current
Output low-side sink current
Low-side sink current timeout
Test conditions
V
LPD
threshold falling
All VSELx = 0, V
OBK
= 30 V
V
OUT
forced at V
OUT_NOM
+ 0.1 V
V
OUT
forced at V
OUT_NOM
+ 0.1 V,
PDO I²C bit is set to 1 after this time has elapsed
V
OUT
forced at V
OUT_NOM
+ 0.1 V, after PDO bit is set to 1 (I
SINK_TIME-
OUT
elapsed)
Electrical characteristics
Min. Typ. Max. Unit
6.7
-6 mA -3
50 mA
10
2 ms mA
Max. reverse current
Thermal shutdown threshold
Thermal shutdown hysteresis
150
15
°C
°C
Notes:
(1)
External signal maximum voltage for which the EXTM function is guaranteed.
T
J
from 0 to 85 °C, V
I
= 12 V
Symbol
Table 10: I2C electrical characteristics
Parameter Test conditions Min.
V
IL
V
IH
I
IN
V
OL
F
MAX
Low level input voltage
High level input voltage
Input current
Low level output voltage
Maximum clock frequency
T
J
from 0 to 85 °C, V
I
= 12 V
Symbol
V
ADDR-1
V
ADDR-2
SDA, SCL
SDA, SCL
SDA, SCL V
IN
= 0.4 to 4.5 V
SDA (open drain), I
OL
= 6 mA
SCL
2
-10
Parameter
Table 11: Address pin characteristics
Test conditions
“0001000(R/W)” address pin voltage range
“0001001(R/W)” address pin voltage range
R/W bit determines the transmission mode: read
(R/W=1) write (R/W=0)
R/W bit determines the transmission mode: read
(R/W=1) write (R/W=0)
Min.
0
2
Typ.
Typ.
Max. Unit
0.8
V
10
0.6
µA
V
400 kHz
Max. Unit
0.8
5
V
V
DocID023739 Rev 3 21/27
Electrical characteristics LNBH30
Refer to Section 5: "Typical application circuits" , T
J
from 0 to 85 °C, data register bits set to
“0”, RSEL = 16.2 kΩ, DSQIN = low, V
IN
= 12 V, I
OUT
= 50 mA, unless otherwise stated.
Typical values are referred to T
J
= 25 °C. V
OUT
= VOUT pin voltage.
Symbol
Table 12: Output voltage diagnostic (VMON bit, status register) characteristics
Parameter Test conditions Min. Typ. Max. Unit
V
TH-L
V
TH-L
Diagnostic low threshold at V
OUT
= 11.8 V
Diagnostic low threshold at V
OUT
= 15 V
VSEL0 = 1, VSEL1 =
VSEL2 =0
VSEL1=0, VSEL0 =
VSEL2 = 1
80
80
90
90
95
95
%
%
If the output voltage is lower than the min. value the VMON I²C bit is set to 1.
If VMON=0 then V
OUT
> 80% of V
OUT
(typ.)
If VMON=1 then V
OUT
< 95% of V
OUT
(typ.)
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9
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID023739 Rev 3 23/27
Package information
9.1 QFN16 (4x4 mm) package information
Figure 9: QFN16 (4x4 mm) package outline
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Dim.
D2
E
E
E2 e
L
A
A1
A3 b
D
Table 13: QFN16 (4x4 mm) mechanical data mm
Min.
0.80
Typ.
0.90
0.00
0.25
3.90
0.02
0.20
0.30
4.00
2.50
3.90
3.90
2.50
4.00
4.00
0.30
0.65
0.40
Package information
Max.
1.00
0.05
0.35
4.10
2.80
4.10
4.10
2.80
0.50
Figure 10: QFN16 (4x4 mm) recommended footprint
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Revision history
10
LNBH30
Revision history
Date
Table 14: Document revision history
Revision Changes
16-Oct-2012
19-Mar-2015
11-Oct-2017
1
2
3
Initial release.
Update Section 2.1: "Output current limit selection" and Table 9: "Electrical characteristics".
Updated features and description in cover page.
Updated Section 2.1: "Data encoding" .
Updated Table 2: "Pin description"
, Table 3: "Absolute maximum ratings" ,
Table 5: "Typical application circuit bill of material"
and Table 9: "Electrical characteristics" .
Updated Figure 1: "Block diagram" ,
Figure 2: "Pin connections (top view)"
and Figure 3: "Application circuit" .
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics
– All rights reserved
DocID023739 Rev 3 27/27
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