STMicroelectronics LNBH26S Datasheet
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LNBH26S
Datasheet
Dual LNBS supply and control I²C with step-up and IC interface
Maturity status link
LNBH26S
Device summary
Order code
Package
Packing
LNBH26SPQR
QFN24 (4 x 4)
Tape and reel
Features
• Complete interface between LNB and I²C bus
• Built-in DC-DC converter for single 12 V supply operation and high efficiency
(typ. 93% @ 0.5 A)
• Selectable output current limit by external resistor
• Compliant with main satellite receiver output voltage specification (15 programmable levels)
• Accurate built-in 22 kHz tone generator suits widely accepted standards
• 22 kHz tone waveform integrity guaranteed at no-load condition as well
• Low drop post regulator and high efficiency step-up PWM with integrated power
NMOS allowing low power losses
• LPM function (low power mode) to reduce dissipation
• Overload and overtemperature internal protection with I²C diagnostic bits
• LNB short-circuit dynamic protection
• +/- 4 kV ESD tolerant on output power pins
Applications
• STB satellite receivers
• TV satellite receivers
• PC card satellite receivers
Description
Intended for analog and digital dual satellite receivers/Sat-TV, and Sat-PC cards, the
LNBH26S is a monolithic voltage regulator and interface IC, assembled in QFN24 4 x
4 specifically designed to provide the 13/18 V power supply and the 22 kHz tone signaling to the LNB down-converter in the antenna dishes or to the multi-switch box.
In this application field, it offers a complete solution for dual tuner satellite receivers with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.
DS8975 - Rev 5 - June 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
LNBH26S
Block diagram
Block diagram
LX -A
PGND
VUP-A
VOUT-A
DETIN -A
DSQOUT -A
BPSW -A
Tone detector
Figure 1. Block diagram
DSQIN-A ADDR SCL SDA DSQIN-B
I²C digital core
DAC
Drop control
Tone ctrl
Diagnostics
Protections
Current limit selection
Voltage reference
ISEL GND BYP VCC
LX-B
PGND
VUP-B
VOUT- B
Tone detector
DETIN-B
DSQOUT-B
BPSW-B
FLT
GIPG2201151303LM
DS8975 - Rev 5 page 2/35
2
2.1
2.2
LNBH26S
Application information (valid for each section A/B)
Application information (valid for each section A/B)
The LNBH26S includes two completely independent sections. Except for ISEL, V
CC
and I²C inputs, each circuit can be separately controlled and have their independent external components. All the specifications below must be considered equal for both sections (A/B).
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages
(V
UP
) that let the integrated LDO post-regulator (generating the 13 V / 18 V LNB output voltages plus the 22 kHz
DiSEqC™ tone) work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at V
UP
- V
OUT
= 1 V typ.). The LDO power dissipation can be further reduced when 22 kHz tone output is disabled by setting the LPM bit to “1” (see LPM function description). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied V
CC
drops below a fixed threshold
(4.7 V typ.). The step-up converter soft-start function reduces the in-rush current during startup. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V, and 6 ms typ. to switch from 0 to 18 V.
DISEQC™ data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC™ standards, and can be activated in 3 different ways:
1.
by an external 22 kHz source DiSEqC™ data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1.
2.
by an external DiSEqC™ data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1.
3.
through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled HIGH and the EXTM bit set to “0”.
Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC™ data transmission,
the LPM bit must be set to “0” see Section 2.4 LPM (low power mode)
.
Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the V
OUT
pin, by using the LNBH26S integrated tone generator.
The output tone waveforms are internally controlled by the LNBH26S tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”.
As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26S activates the 22 kHz tone on the V
OUT
output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired, refer to
Figure 2. Tone enable and disable timing (using external waveform) .
Figure 2. Tone enable and disable timing (using external waveform)
DSQIN
Tone output
~ 1 µs
~ 60 µs
GIPG2601151219LM
DS8975 - Rev 5 page 3/35
2.3
2.4
2.5
2.6
LNBH26S
Data encoding by external DiSEqC envelope control through the DSQIN pin
Data encoding by external DiSEqC envelope control through the DSQIN pin
If an external DiSEqC™ envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC™ envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. In this way the internal 22 kHz signal is superimposed on the
V
OUT
DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH the internal control circuit activates the 22 kHz tone output.
The 22 kHz tone on the V
OUT
pin is activated with a delay of about 6 µs from DSQIN TTL signal rising edge, and it stops with a delay time in the range of 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired, refer to
Figure 3. Tone enable and disable timing (using envelope signal) .
Figure 3. Tone enable and disable timing (using envelope signal)
DSQIN
Tone output
~ 6 µs
15 µs ~ 60 µs
GIPG2601151226LM
LPM (low power mode)
In order to reduce total power loss, each section of the LNBH26S is provided with the LPM I²C bit that can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time periods. The LPM bit can be set to “1” when the DiSEqC™ data transmission is not requested (no 22 kHz tone output is present); in this condition the drop voltage across the integrated LDO regulator (V
UP
- V
OUT
) is reduced to 0.6 V typ. and, consequently, the power loss inside the relative LNBH26S channel regulator is reduced too. For example, at 500 mA load, LPM=1, allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0” before starting the 22 kHz DiSEqC™ data transmission; in this condition the drop voltage across the LDO is kept to 1 V typ. Keep LPM=0 all times if LPM function is not used.
DISEQC™ 2.0 implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing. Each LNBH26S section DETIN pin must be AC coupled to the DiSEqC™ bus, and extracted PWK data is available on the corresponding DSQOUT pin. To comply with the bi-directional DiSEqC™ 2.0 bus hardware requirements, an output R-L filter is needed (per each voltage output pin). In order to avoid 22 kHz waveform distortion during tone transmission, each LNBH26S section is provided with a BPSW pin to be connected to an external transistor, which allows the bypassing of the corresponding output RL filter in DiSEqC 2.x applications while in transmission mode. Before starting tone transmission by means of the DSQIN pin, provide that the TEN bit is preventively set to “1” and after ending tone transmission, provide that the TEN bit is set to “0”.
Output current limit selection
The linear regulators current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation:
IMAX typ. =
16578
RSEL1.206
with ISET = 0
IMAX typ. =
6452
RSEL1.159
with ISET = 1
(1)
(2)
DS8975 - Rev 5 page 4/35
2.7
2.8
2.9
LNBH26S
Output voltage selection where RSEL is the resistor connected between ISEL and GND expressed in kΩ and I
LIM
(typ.) is the typical current limit threshold expressed in mA. I
LIM
can be set up to 1 A for each channel. However, it is recommended to not exceed, for a long period, a total amount of current of 1 A from both sections (I
OUT_A
+ I
OUT_B
< 1 A) in order to avoid the overtemperature protection triggering and to thoroughly validate the PCB layout thermal management in real application environment conditions.
Output voltage selection
Each linear regulator channel output voltage level can be easily programmed in order to accomplish application
for exact programmable values. Register writing is accessible via the I²C bus.
Diagnostic and protection functions
The LNBH26S has 14 diagnostic internal functions provided via the I²C bus, by reading 14 bits on two STATUS registers (in read mode). All the diagnostic bits are, in normal operation (that is, no failure detected), set to LOW.
One diagnostic bit is dedicated to the overtemperature status (OTF), one bit is dedicated to the input voltage power not good function (PNG), while the remaining 12 bits (6 per channel) are dedicated to the overload protection status (OLF), to the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum load current (IMON), to external voltage source presence on the V
OUT
pin (PDO), and to 22 kHz tone presence on the DETIN pin (TDET). Once the OLF (or the OTF or PNG) bit has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is done.
Surge protections and TVS diodes
Each LNBH26S device section is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices.
Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually used, as shown in the following schematic
Figure 4. Surge protection circuit
to protect each section of
STB output circuits where the LNBH26S and other devices are electrically connected to the antenna cable.
Figure 4. Surge protection circuit
2.10
For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically designed by ST. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details).
FLT: fault FLAG
In order to get an immediate feedback on a diagnostic status, the LNBH26S is equipped with a dedicated fault flag pin (FLT). In the case an overload (OLF bit=1), overheating (OTF bit=1) or power not good (PNG bit=1) condition is detected, the FLT pin (open drain output) is set to low and is kept low until the relevant activating diagnostic bit is cleared. Be aware that diagnostic bits OLF, OTF and PNG, once activated, are kept latched to “1”
DS8975 - Rev 5 page 5/35
LNBH26S
VMON: output voltage diagnostic
2.11
2.12
2.13
2.14
2.15
2.16
2.17
until the origin cause is removed and a new register reading operation is performed by the microprocessor. The
FLT pin must be connected to a positive voltage (5 V max.) by a pull-up resistor.
VMON: output voltage diagnostic
When one device output voltage is activated (V
OUT
pin), its value is internally monitored and, as long as the
TMON: 22 kHz tone diagnostic
The 22 kHz tone can be internally detected and monitored if one (or both) DETIN pin are connected to the LNB output bus (see
Figure 7. DiSEqC 2.x application circuit ) through a decoupling capacitor.
The tone diagnostic function is provided with the corresponding TMON I²C bit. If the 22 kHz tone amplitude and/or the tone frequency is out of the guaranteed limits, see
Table 18. 22 kHz tone diagnostic (TMON-A/B bit, STATUS
2 register) characteristics , the corresponding TMON I²C bit is set to “1”.
TDET: 22 kHz tone detection
When a 22 kHz tone presence is detected on one DETIN pin, the corresponding TDET I²C bit is set to “1”.
IMON: minimum output current diagnostic
In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) each
LNBH26S section is provided with a minimum output current flag by the corresponding IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than 12 mA (typ.). It is recommended to use the IMON function only with the 22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the output current is below the minimum current threshold. To activate the IMON diagnostic function, set to “1” the
EN_IMON I²C bit in the DATA4 register. Be aware that as soon as the IMON function is activated by means of
EN_IMON=1, the V
OUT
is immediately increased to 21 V (typ.) independently on the VSEL bit setting. This operation is applied in order to be sure that the LNBH26S output has the higher voltage present in the LNB bus.
Do not use this function in an application environment where a 21 V voltage level is not supported by other peripherals connected to the LNB bus.
PDO: overcurrent detection on output pull-down stage
When an overcurrent occurs on one section pull-down output stage due to an external voltage source greater than the LNBH26S nominal V
OUT
, and for a time longer than I
SINK_TIME_OUT
(10 ms typ.), the corresponding PDO
I²C bit is set to “1”. This may happen due to an external voltage source presence on the LNB output (V
OUT
pin).
For current threshold and deglitch time details, see
Table 12. A/B section electrical characteristics .
Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH26S is automatically reset at power-on. As long as the V
CC
stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all
DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor.
PNG: input voltage minimum detection
When input voltage (V
CC
pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1” and the FLT pin is set LOW.
DS8975 - Rev 5 page 6/35
LNBH26S
ISW: inductor switching current limit
2.18
2.19
2.20
2.21
ISW: inductor switching current limit
In order to allow low saturation current inductors to be used, the maximum DC-DC inductor switching current limit threshold can be set by one I²C bit per section (ISW). Two values are available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).
COMP: boost capacitors and inductor
The DC-DC converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacitors (V
UP
pin). For this purpose, one I²C bit in the DATA 4 register (see COMP ) can be set to
“1” or “0” as follows:
COMP = 0 for electrolytic capacitors
COMP = 1 for ceramic capacitors
For recommended DC-DC capacitor and inductor values refer to
Section 5 Typical application circuits
and to the
BOM in
Table 4. LNBH26S DiSEqC 1.x bill of material
.
OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. It is possible to set the short-circuit current protection either statically (simple current clamp) or dynamically by the corresponding PCL bit of the I²C DATA3 register.
When the PCL (pulsed current limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T
ON
time (90 ms or 180 ms typ., according to the corresponding TIMER bit programmed in the DATA3 register) and after that, the output is set in shutdown for a
T
OFF
time of typically 900 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1” and the FLT pin is set to low level. After this time has elapsed, the involved output is resumed for a time T
ON
. At the end of T
ON
, if the overload is still detected, the protection circuit cycles again through T
OFF
and
T
ON
. At the end of a full T
ON
in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after register reading is done. Typical T
ON
+T
OFF
time is 990 ms (if TIMER=0) or
1080 ms (if TIMER=1) and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and then, switching to dynamic mode (PCL=0) after a chosen amount of time, depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns LOW when the overload condition is cleared and register reading is done.
After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register.
If OLR=1, all VSEL bits corresponding to the involved section are reset to “0” and the LNB section output (V
OUT pin) is disabled. To re-enable the output stage, the VSEL bits must be set again by the microprocessor and the
OLF bit is reset to “0” after a register reading operation.
If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and the
OLF bit is reset to “0” after a register reading operation.
OTF: thermal protection and diagnostic
The LNBH26S is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and both liner regulators are shut off, the diagnostic OTF bit in the STATUS1 register is set to
“1” and the FLT pin is set to low level. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register.
If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (V
OUT
pins) are disabled. To re-enable output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation.
If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.
DS8975 - Rev 5 page 7/35
3
LNBH26S
Pin configuration
Pin configuration
Figure 5. Pin connections (top view)
24 23 22 21 20 19
DSQIN-B DSQOUT-A DSQIN-A VUP-A VOUT-A DETIN-A
1 DSQOUT-B
2 FLT
BPSW-A
VCC
18
17
3 LX-A
4 PGND
BYP 16
GND 15
BPSW-B 14 5 LX-B
6 ADDR DETIN-B 13
SCL
7
SDA
8
ISEL
9
NC
10
VUP-B VOUT-B
11 12
GIPG2701151333LM
6
7
8
3
4
5
Pin
1
2
9
10
Symbol
DSQOUT-B
FLT
LX-A
P-GND
LX-B
ADDR
SCL
SDA
ISEL
N.C.
Name
DiSEqC output
FLT
NMOS drain
Power ground
NMOS drain
Address setting
Serial clock
Serial data
Current selection for both channel A and B
Table 1. Pin description
Pin function
Open drain output of channel A tone detector to the main microcontroller for
DiSEqC 2.0 data decoding. It is low when tone is detected on the DETIN-B input pin. Set to ground if not used.
Open drain output for IC fault conditions. It is set low in case of overload (OLF bit) or overheating status (OTF bit) or power not good (PNG bit) is detected. To be connected to pull-up resistor (5 V max.).
Channel A, integrated N-channel power MOSFET drain.
DC-DC converter power ground. To be connected directly to the exposed pad.
Channel B, integrated N-channel power MOSFET drain.
Two I 2 C bus addresses available by setting the address pin level voltage. See
Table 15. Address pin characteristics .
Clock from I²C bus.
Bi-directional data from/to I²C bus.
The resistor “RSEL” connected between ISEL and GND defines the linear
regulator current limit threshold. Refer to Section 2.5 DISEQC™ 2.0
. The RSEL resistor defines the same current limit both for channels A and B.
Not internally connected
Not internally connected pin. Set floating if not used.
DS8975 - Rev 5 page 8/35
DS8975 - Rev 5
LNBH26S
Pin configuration
Pin
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Epad
Symbol
V
V
UP-B
OUT-B
DETIN-B
BPSW-B
GND
BYP
V
CC
BPSW-A
DETIN-A
V
V
OUT-A
UP-A
DSQIN-A
DSQOUT-A
DSQIN-B
Epad
Name
Channel B step-up voltage
Channel B
LNB output port
Tone detector input
Switch control
Analog ground
Bypass capacitor
Supply input
Pin function
Input of channel B linear post-regulator. The voltage on this pin is monitored by the internal channel B step-up controller to keep a minimum dropout across the linear pass transistor.
Output of channel B integrated very low drop linear regulator. See Table
13. Output voltage selection (data1 register, write mode)
for voltage selection and description.
Channel B, 22 kHz tone decoder input, must be AC coupled to the DiSEqC 2.0
bus. Set to ground if not used.
To be connected to an external transistor to be used to bypass the channel B output RL filter needed in DiSEqC 2.x applications during the DiSEqC
transmitting mode (see Section 5 Typical application circuits
). Set ground if not used. Open drain pin.
Analog circuit ground. To be connected directly to the exposed pad.
Needed for internal pre-regulator filtering. The BYP pin is intended to connect an external ceramic capacitor only. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.
8 to 16 V IC DC-DC power supply.
Switch control
Tone detector input
Channel A,
LNB output port
Channel A step-up voltage
DSQIN for DiSEqC envelope input or external 22 kHz
TTL input
DiSEqC output
DSQIN for DiSEqC envelope input or external 22 kHz
TTL input
Exposed pad
To be connected to an external transistor to be used to bypass the channel A output RL filter needed in DiSEqC 2.x applications during the DiSEqC transmitting mode (see
Section 5 Typical application circuits ). Set to ground if not
used. Open drain pin.
Channel A, 22 kHz tone decoder input, must be AC coupled to the DiSEqC 2.0
bus. Set to ground if not used.
Output of channel A integrated very low drop linear regulator. See Table
13. Output voltage selection (data1 register, write mode)
for voltage selection and description.
Input of channel A linear post-regulator. The voltage on this pin is monitored by the internal channel A step-up controller to keep a minimum dropout across the linear pass transistor.
It is intended for channel A 22 kHz tone control. It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-A I²C bit setting as follows: If EXTM-A=0, TEN-A=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH26S uses this code to modulate the internally generated 22 kHz carrier. If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which activate the 22 kHz tone output (refer to
Section 2.2 Data encoding by external 22 kHz tone TTL signal ). Pull up high if the tone output is
activated by the TEN-A I²C bit only.
Open drain output of channel A tone detector to the main microcontroller for
DiSEqC 2.0 data decoding. It is low when tone is detected to the DETIN-A input pin. Set ground if not used.
It is intended for channel B 22 kHz tone control.
It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-B I²C bit setting as follows: if EXTM-B=0, TEN-B=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH26S uses this code to modulate the internally generated 22 kHz carrier.
If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which activate the
22 kHz tone output (refer to
Section 2.2 Data encoding by external 22 kHz tone
).
Pull up high if the tone output is activated by the TEN-B I²C bit only.
To be connected with power grounds and to ground layer through vias to dissipate the heat.
page 9/35
4
Note:
LNBH26S
Maximum ratings
Maximum ratings
Symbol
V
BYP
I
SEL
T
STG
T
J
T
JMAX
V
CC
V
UP
I
OUT
V
OUT
V
I
V
O
V
BPSW
V
DETIN
I
O
LX
ESD
Table 2. Absolute maximum ratings
Parameter
DC power supply input voltage pins
DC input voltage
Output current
DC output pin voltage
Logic input pin voltage (SDA, SCL, DSQIN, ADDR pins)
Logic output pin voltage (FLT, DSQOUT)
BPSW pin voltage
Detector input signal amplitude
Logic output pin current (FLT, DSQOUT, BPSW)
LX input voltage
Internal reference pin voltage
Current selection pin voltage
Storage temperature range
Operating junction temperature range
Maximum junction temperature
ESD rating with human body model (HBM) for all pins, except power output pins
ESD rating with human body model (HBM) for power output pins
Value
-0.3 to 20
-0.3 to 40
Internally limited
-0.3 to 40
-0.3 to 7
-0.3 to 7
-0.3 to 40
-0.6 to 2
10
-0.3 to 30
-0.3 to 4.6
-0.3 to 3.5
-50 to 150
-25 to 125
150
2
4
V
V mA
V
V
V
°C
°C
°C
Unit
V
V mA
V
V
V kV
Symbol
RthJC
RthJA
Table 3. Thermal data
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient with device soldered on 2s2p 4-layer PCB provided with thermal vias below exposed pad
Value
2
40
Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
Unit
°C/W
°C/W
DS8975 - Rev 5 page 10/35
5
LNBH26S
Typical application circuits
Typical application circuits
Figure 6. DiSEqC 1.x application circuit
D2- A
L1- A
Vin
12 V
C1
L1- B
D1- A
LNBOUT-A
21 VUP-A
VOUT-A
20
C2- A C3-A
3 LX-A
R1 (RSEL)
9 ISEL
C7
16 Byp
17 Vcc
C4
I 2 C Bus
{
8
7
SDA
SCL
5 LX-B
LNBH26S
DSQIN- A 22
DSQIN- B 24
ADDR 6
FLT 2
C5-A D3-A
DiSEqC
22 KHz TTL
Tone enable control or
DiSEqC
Envelope TTL
D1- B
C2- B C3-B
11 VUP-B
VOUT -B
P- GND A -GND
4
15
12
C5-B D3-B
D2-B
LNBOUT-B
GIPG2801151243LM
Component
R1 (RSEL)
C1
C2
C3
C5
C4, C7
D1
D2
D3
Table 4. LNBH26S DiSEqC 1.x bill of material
Notes
Smd resistor. Refer to
Table 12. A/B section electrical characteristics
and ISEL pin description in
.
> 25 V electrolytic capacitor, 100 µF or higher is suitable or
> 25 V ceramic capacitor, 10 µF or higher is suitable
With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable or with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is suitable
From 470 nF to 2.2 µF ceramic capacitor placed as close as possible to V
UP lower DC-DC noise
pins. Higher values allow
From 100 nF to 220 nF ceramic capacitor placed as close as possible to V
OUT lower DC-DC noise
pins. Higher values allow
220 nF ceramic capacitors. To be placed as close as possible to V
OUT
pin
STPS130A or similar Schottky diode
1N4001-07, S1A-S1M, or any similar general purpose rectifier
BAT54, BAT43, 1N5818, or any low power Schottky diode with I
F
(AV) > 0.2 A, V be placed as close as possible to V
OUT
pin
RRM
> 25 V, V
F
< 0.5 V. To
DS8975 - Rev 5 page 11/35
DS8975 - Rev 5
LNBH26S
Typical application circuits
Component
L1
Notes
With COMP=0, use 10 µH inductor with I
SAT
> I
PEAK
where I
PEAK
is the boost converter peak current or with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with I
SAT
> I
PEAK
where I
PEAK
is the boost converter peak current
Figure 7. DiSEqC 2.x application circuit
D2-A
Vin
12 V
C1
D1- A
L1- A
L1-B
D1-B
21 VUP-A VOUT-A
20
C5 - A D3- A
L2- A
LNBOUT -A
C2 - A C3 -A LNBH26S
BPSW-A
18
4.7 k
4.7 k (optional)
TR1- A
3 LX-A
DETIN-A 19
R1 (RSEL)
9
DSQOUT-A
23
10 k
C6 -A
ISEL
C7
C4
I 2 C Bus { 8
7
C2 -B C3-B
16
17
Byp
Vcc
DSQIN -A
DSQIN-B
ADDR
22
24
6 Open drains to µcontroller
DiSEqC
22KHz TTL
Tone enable control or
DiSEqC
Envelope TTL
SDA
SCL
FLT 2
5 LX- B
DSQOUT-B 1
10 k
C6 -B
DETIN-B
13
4.7 k
BPSW -B
14
11 VUP-B
VOUT-B
P-GND A-GND
4 15
12
C5 - B D3 B
4.7k
(optional)
15 W
L2 -B
TR1 B
LNBOUT -B
D2- B
GIPG2801151323LM
Component
R1 (RSEL)
C1
C2
C3
C5
C4, C7
D1
Table 5. LNBH26S DiSEqC 2.x bill of material
Notes
SMD resistor. Refer to
Table 12. A/B section electrical characteristics
and ISEL pin description in
.
> 25 V electrolytic capacitor, 100 µF or higher is suitable or
> 25 V ceramic capacitor, 10 µF or higher is suitable
With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable or with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is suitable
From 470 nF to 2.2 µF ceramic capacitor placed as close as possible to V
UP
pins. Higher values allow lower DC-DC noise
From 100 nF to 220 nF ceramic capacitor placed as close as possible to V
OUT lower DC-DC noise
pins. Higher values allow
220 nF ceramic capacitors. To be placed as close as possible to V
OUT
pin
STPS130A or similar Schottky diode page 12/35
LNBH26S
Typical application circuits
Component
D2
D3
L1
L2
TR1
Notes
1N4001-07, S1A-S1M, or any similar general purpose rectifier
BAT54, BAT43, 1N5818, or any low power Schottky diode with I
F
(AV) > 0.2 A, V be placed as close as possible to V
OUT
pin
RRM
> 25 V, V
F
< 0.5 V. To
With COMP=0, use 10 µH inductor with I
SAT
> I
PEAK
where I
PEAK
is the boost converter peak current or with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with I
SAT peak current
> I
PEAK
where I
PEAK
is the boost converter
220 µH - 270 µH inductor as per DiSEqC 2.x specification
MMBTA92, 2STR2160 or any low power PNP with I
C
> 250 mA, V
CE
> 30 V, can be used
Also any small power PMOS with I
D
> 250 mA, R
DS(on)
< 0.5 W, V
DS
> 20 V, can be used
DS8975 - Rev 5 page 13/35
6
6.1
6.2
6.3
6.4
6.5
LNBH26S
I²C bus interface
I²C bus interface
Data transmission from the main microprocessor to the LNBH26S and vice versa takes place through the 2-wire
I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
Data validity
As shown in Figure 8. Data validity on the I²C bus
, the data on the SDA line must be stable during the high semiperiod of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and stop condition
As shown in Figure 9. Timing diagram of I²C bus
, a start condition is HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse
(see
Figure 10. Acknowledge on the I²C bus
). The peripheral (LNBH26S) which acknowledges must pull down
(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed must generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the nin th clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH26S does not generate acknowledge if the V
CC
supply is below the undervoltage lockout threshold (4.7 V typ.).
Transmission without acknowledge
If detection of the acknowledge of the LNBH26S is not required, the microprocessor can use a simpler transmission: it simply waits for one clock without checking the slave acknowledging, and sends the new data.
This approach is of course less protected from misworking and decreases noise immunity.
DS8975 - Rev 5 page 14/35
DS8975 - Rev 5
Figure 8. Data validity on the I²C bus
LNBH26S
Transmission without acknowledge
SCL
SDA
DATA LINE STABLE
DATA VALID DATA CHANGE
ALLOWED
Figure 9. Timing diagram of I²C bus
SCL
GIPG0202151036LM
SDA
START
SCL
SDA
START
STOP
GIPG0202151047LM
1
Figure 10. Acknowledge on the I²C bus
7
2
8
MSB
9
ACKNOWLEDGMENT
FROM SLAVE
GIPG0202151054LM page 15/35
LNBH26S
I²C interface protocol
7
I²C interface protocol
7.1
Write mode transmission
•
•
•
•
•
•
The LNBH26S interface protocol is made up of:
• a start condition (S) a chip address byte with the LSB bit R/W = 0 a register address (internal address of the first register to be accessed) a sequence of data (byte to write in the addressed internal register + acknowledge) the following bytes, if any, to be written in successive internal registers a stop condition (P). The transfer lasts until a stop bit is encountered the LNBH26S, as slave, acknowledges every byte transfer
Figure 11. Example of writing procedure starting with first data address 0x2
CHIP ADDRESS
MSB LSB
REGISTER ADDRESS
MSB LSB
S 0 0 0 1 0 0 X 0 0 0 0 0 X X X
Note:
7.2
MSB
DATA 1
Add=0x2
LSB MSB LSB MSB
DATA 3
Add=0x4
LSB MSB
DATA 4
Add=0x5
LSB
P
GIPG0202151231LM
ACK = acknowledge
S = start
P = stop
R/W = 1/0, read/write bit
X = 0/1, set the values to select the chip address (see Table 15. Address pin characteristics
for pin selection)
The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped by the master by sending a stop condition after any acknowledge bit.
Read mode transmission
•
•
•
•
•
In read mode the byte sequence must be as follows:
• a start condition (S) a chip address byte with the LSB bit R/W=0 the register address byte of the internal first register to be accessed a stop condition (P) a new master transmission with the chip address byte and the LSB bit R/W=1 after the acknowledge the LNBH26S starts sending the addressed register content. As long as the master keeps the acknowledge LOW, the LNBH26S transmits the next address register byte content
DS8975 - Rev 5 page 16/35
LNBH26S
Data registers
• the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit
Figure 12. Example of reading procedure starting with first status address 0X0
CHIP ADDRESS
MSB LSB
REGISTER ADDRESS
MSB LSB
S 0 0 0 1 0 0 X 0 0 0 0 0 X X X
CHIP ADDRESS
MSB
P S 0 0 0 1 0 0 X
LSB
MSB LSB
- B - A - B - A
- B
- A
MSB LSB
- B - A - B - A - B
- A
Note:
7.3
Note:
MSB LSB
- B - B - B - B - A - A - A - A
MSB
- B
- B - B
LSB
- A - A - A
MSB
- B
- B
- B - B
- A
LSB
- A
- A
MSB LSB
P
GIPG0202151331LM
ACK = acknowledge
S = start
P = stop
R/W = 1/0, read/write bit
X = 0/1, set the values to select the chip address, see
Table 15. Address pin characteristics
for pin selection) and
see Table 11. STATUS 2 (read register. Register address = 0X1)
.
The reading procedure can start from any register address (status 1, 2 or Data1..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped by the master by sending a stop condition after any acknowledge bit.
Data registers
The data 1..4 registers can be addressed both to write and read mode. In read mode they return the last writing byte status received in the previous write transmission.
The following tables provide the register address values of data 1..4 and a function description of each bit.
The following tables provide the register address values of data 1..4 and a function description of each bit.
DS8975 - Rev 5 page 17/35
DS8975 - Rev 5
LNBH26S
Data registers
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Table 6. DATA 1 (read/write register. Register address = 0X2)
Name
VSEL1-A
VSEL2-A
VSEL3-A
VSEL4-A
VSEL1-B
VSEL2-B
VSEL3-B
VSEL4-B
CH
A
B
Value
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Description
Channel A
Output voltage selection bits
Channel B
Output voltage selection bits
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (MSB)
Name
TEN-A
LPM-A
EXTM-A
N/A
TEN-B
LPM-B
EXTM-B
N/A
Table 7. DATA 2 (read/write register. Register address = 0X3)
CH
A
B
Value
1
0
1
0
1
0
0
1
0
1
0
1
0
0
Description
22 kHz tone enabled. Tone output controlled by the DSQIN pin
22 kHz tone output disabled
Low power mode activated (used only with 22 kHz tone output disabled)
Low power mode deactivated (keep always LPM=0 during
22 kHz tone transmission)
DSQIN input pin is set to receive external 22 kHz TTL signal source
DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Reserved. Keep to “0”
22 kHz tone enabled. Tone output controlled by the DSQIN pin
22 kHz tone output disabled
Low power mode activated (used only with 22 kHz tone output disabled)
Low power mode deactivated (keep always LPM=0 during
22 kHz tone transmission)
DSQIN input pin is set to receive external 22 kHz TTL signal source
DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Reserved. Keep to “0” page 18/35
DS8975 - Rev 5
LNBH26S
Data registers
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (MSB)
Name
ISET-A
ISW-A
PCL-A
Table 8. DATA 3 (read/write register. Register address = 0X4)
TIMER-A
ISET-B
ISW-B
PCL-B
TIMER-B
CH
A
B
Value
1
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
Description
Current limit of LNB output (VOUT pin) set to lower current range
Current limit of LNB output (VOUT pin) set to default range
DC-DC, inductor switching current limit set to 2.5 A typ.
DC-DC, inductor switching current limit set to 4 A typ.
Pulsed (dynamic) LNB output current limiting is deactivated
Pulsed (dynamic) LNB output current limiting is activated
Pulsed (dynamic) LNB output current T
ON
time set to 180 ms typ.
Pulsed (dynamic) LNB output current T
ON ms typ.
time set to 90
Current limit of LNB output (VOUT pin) set to lower current range
Current limit of LNB output (VOUT pin) set to default range
DC-DC, inductor switching current limit set to 2.5 A typ.
DC-DC, inductor switching current limit set to 4 A typ.
Pulsed (dynamic) LNB output current limiting is deactivated
Pulsed (dynamic) LNB output current limiting is activated
Pulsed (dynamic) LNB output current T
ON
time set to 180 ms typ.
Pulsed (dynamic) LNB output current T
ON
time set to 180 ms typ.
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Name
Table 9. DATA 4 (read/write register. Register address = 0X5)
EN_IMON-A
CH
A
Value
1
0
Description
IMON diagnostic function is enabled. (VOUT is set to 21 V typ.)
IMON diagnostic function is disabled. Keep always at “0” if
IMON is not used
N/A
0
0
Reserved. Keep to “0”
OLR
EN_IMON-B
N/A
A/B
B
1
0
1
0
0
In the case of overload protection activation (OLF=1), all
VSEL bits are reset to “0” and LNB relevant output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0)
In the case of overload protection activation (OLF=1) the
LNB output (VOUT pin) is automatically enabled as soon as the overload condition is removed (OLF=0) with the previous VSEL bit setting
IMON diagnostic function is enabled
IMON diagnostic function is disabled. Always keep “0” if
IMON is not used
Reserved. Keep “0” page 19/35
7.4
LNBH26S
Status registers
Bit
Bit 6
Bit 7 (MSB)
Name
THERM
COMP
CH
A/B
Value
1
0
1
0
Description
If thermal protection is active (OTF=1), all VSEL bits are reset to “0” and LNB output (VOUT pin) is disabled (both section A and B). VSEL bits must be set again by the master after the overtemperature condition is removed
(OTF=0)
In the case of thermal protection activation (OTF=1) the
LNB output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=0) with the previous VSEL bit setting
DC-DC converter compensation. Set to use very low
E.S.R. capacitors or ceramic caps on VUP pin
DC-DC converter compensation. Set to use standard electrolytic capacitors on VUP pin
Status registers
The STATUS 1, 2 registers can be addressed to read mode only and provide the diagnostic functions described in the following tables.
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Table 10. STATUS 1 (read register. Register address = 0X0)
Name
OLF-A
OLF-B
VMON-A
VMON-B
PDO-A
PDO-B
CH
A
B
A
B
A
B
Value
1
0
1
0
1
0
1
0
1
0
1
0
Description
VOUT pin overload protection has been triggered (I
OUT
I
LIM
).
>
No overload protection has been triggered to VOUT pin
(I
OUT
< I
LIM
)
VOUT pin overload protection has been triggered (I
OUT
I
LIM
).
>
No overload protection has been triggered to VOUT pin
(I
OUT
< I
LIM
)
Output voltage (VOUT pin) is lower than VMON specification thresholds. Refer to
Table 16. Output voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics
Output voltage (VOUT pin) is within the VMON specifications
Output voltage (VOUT pin) is lower than VMON specification thresholds. Refer to
Table 16. Output voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics
Output voltage (VOUT pin) is within the VMON specifications
Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (VOUT pin)
No overcurrent detected on output pull-down stage
Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (VOUT pin)
No overcurrent detected on output pull-down stage
DS8975 - Rev 5 page 20/35
DS8975 - Rev 5
LNBH26S
Status registers
Bit
Bit 6
Bit 7 (MSB)
Name
OTF
PNG
CH
A/B
Value
1
0
1
0
Description
Junction overtemperature is detected, T
J
> 150 °C (typ.).
See also the THERM bit setting
Junction overtemperature not detected, T
T
J
J
<135 °C (typ.).
is below thermal protection threshold
Input voltage (VCC pin) is lower than LPD minimum
thresholds. Refer to Table 12. A/B section electrical characteristics .
Input voltage (VCC pin) is higher than LPD thresholds.
Refer to
Table 12. A/B section electrical characteristics
.
N/A = reserved bit
All bits reset to 0 at power-on
Bit
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Table 11. STATUS 2 (read register. Register address = 0X1)
Name
TDET-A
TDET-B
TMON-A
TMON-B
IMON-A
IMON-B
CH
A
B
A
B
A
B
Value
1
0
1
0
1
0
1
0
1
0
1
0
Description
22 kHz tone presence is detected on the DETIN pin
No 22 kHz tone is detected on the DETIN pin
22 kHz tone presence is detected on the DETIN pin
No 22 kHz tone is detected on the DETIN pin
22 kHz tone present on the DETIN pin is out of TMON specification thresholds. That is: the tone frequency or the
A
TONE
(tone amplitude) are out of the thresholds
guaranteed in Table 18. 22 kHz tone diagnostic (TMON-
A/B bit, STATUS 2 register) characteristics
22 kHz tone present on the DETIN pin is within TMON specification thresholds. Refer to
Table 18. 22 kHz tone diagnostic (TMON-A/B bit, STATUS 2 register) characteristics
22 kHz tone present on the DETIN pin is out of TMON specification thresholds. The tone frequency or the A
TONE
(tone amplitude) is out of the thresholds guaranteed in
Table 18. 22 kHz tone diagnostic (TMON-A/B bit, STATUS
22 kHz tone present on DETIN pin is within TMON specification thresholds. Refer to
Table 18. 22 kHz tone diagnostic (TMON-A/B bit, STATUS 2 register) characteristics
Output current (from VOUT pin) is lower than IMON
Output current (from VOUT pin) is higher than IMON
specifications. Refer to Table 17. Output current diagnostic
(IMON-A/B bits, STATUS 2 register) characteristics
Output current (from VOUT pin) is lower than IMON
Output current (from VOUT pin) is higher than IMON
specifications. Refer to Table 17. Output current diagnostic
(IMON-A/B bits, STATUS 2 register) characteristics
page 21/35
Bit
Bit 6
Bit 7 (MSB)
Name
N/A
N/A = reserved bit
All bits reset to 0 at power-on
CH Value Description
Reserved
LNBH26S
Status registers
DS8975 - Rev 5 page 22/35
8
LNBH26S
Electrical characteristics
Electrical characteristics
Refer to
Section 5 Typical application circuits , T
J
from 0 to 85 °C, all DATA 1..4 register bits set to 0 except VSEL1
= 1, RSEL = 11 kΩ, DSQIN = low, V
IN
= 12 V, I
OUT
= 50 mA, unless otherwise stated. Typical values are referred to T
J
= 25 °C. V
OUT
= V
OUT
pin voltage. See Section 6 I²C bus interface
and Section 7 I²C interface protocol .
Symbol
V
IN
I
IN
V
OUT
V
OUT
V
OUT
I
LIM
I
LIM
I
SC
SS
SS
T13-18
T18-13
T
OFF
T
ON
A
TONE
F
TONE
D
TONE tr, tf
Table 12. A/B section electrical characteristics
Parameter
Test conditions Min.
8
Supply current
Both sections A and B enabled
I
OUT
= 0 mA
22 kHz tone enabled (TEN-A/B =
1, DSQIN-A/B = high), I
OUT
= 0 mA
Both sections A and B set in standby:
VSEL1=VSEL2=VSEL3=VSEL4=0
Output voltage total accuracy
Line regulation
Load regulation
Valid at any V
OUT
selected level -3.5
Output current limiting thresholds
Output current limiting thresholds
V
IN
= 8 to 16 V
I
OUT
from 50 to 750 mA
RSEL = 11 kΩ, ISET = 0
RSEL = 15 kΩ, ISET = 0
RSEL = 20 kΩ, ISET = 0
RSEL = 11 kΩ, ISET = 1
RSEL = 15 kΩ, ISET = 1
RSEL = 20 kΩ, ISET = 1
750
500
350
Output short-circuit current
Soft-start time
Soft-start time
Soft transition rise time
Soft transition fall time
Dynamic overload protection off-time
RSEL = 11 kΩ, ISET = 0
V
OUT
from 0 to 13 V
V
OUT
from 0 to 18 V
V
OUT
from 13 V to 18 V
V
OUT
from 18 V to 13 V
PCL = 0, output shorted
Dynamic overload protection on-time
Tone amplitude
PCL = TIMER = 0, output shorted
PCL = 0, TIMER = 1, output shorted
DSQIN=high, EXTM=0, TEN=1
I
OUT
from 0 to 750 mA
C
BUS
from 0 to 750 nF
0.55
Tone frequency
Tone duty cycle
DSQIN=high, EXTM=0, TEN=1
20
43
5
Typ.
12
12
19
2
100
400
280
200
500
4
6
1.5
1.5
900
T
OFF
/10
T
OFF
/5
0.675
22
50
8
Max.
16
+3.5
40
1100
750
550
0.8
24
57
15
Unit
V mA
% mV mA mA
V
PP kHz
%
µs mA ms ms ms ms ms
DS8975 - Rev 5 page 23/35
DS8975 - Rev 5
LNBH26S
Electrical characteristics
Symbol
Eff
F
DC/DC
SW
Parameter
DC-DC converter efficiency
DC-DC converter switching frequency
Test conditions
I
OUT
= 500 mA
Min.
Typ.
93
440
Max.
Unit
% kHz
UVLO
V
LP
Undervoltage lockout thresholds
Low power diagnostic
(LPD) thresholds
UVLO threshold rising
UVLO threshold falling
V
LP
threshold rising
V
LP
threshold falling
4.8
4.7
7.2
6.7
V
V
V
IL
V
IH
I
IH
DSQIN, pin logic low
DSQIN, pin logic high
DSQIN, pin input current V
IH
= 5 V
2
15
0.8
V
V
µA
F
V
Z
DETIN
DETIN
DETIN
V
OL
Tone detector frequency capture range
Tone detector input amplitude
Tone detector input impedance
DSQOUT, FLT pin logic
LOW
0.4 V
PP
sine wave
Sine wave signal, 22 kHz
DETIN tone present, I
OL
= 2 mA
19
0.3
22
150
0.3
25
1.5
0.5
kHz
V
PP kΩ
V
V
OL_BPSW
BPSW pin low voltage
I
OL_BPSW
= 5 mA
DSQIN = high, EXTM = 0,
TEN = 1
0.7
V
I
OZ
DSQOUT, FLT pin leakage current
Output backward current
DETIN tone absent, V
OH
= 6 V 10 µA
I
I
I
OBK
SINK
SINK_TIME-OUT
I
REV
Output low-side sink current
Low-side sink current time-out
Max. reverse current
All VSELx = 0, V
OBK
= 30 V
V
OUT
forced at V
OUT_nom
+0.1 V
V
OUT
forced at V
OUT_nom
+0.1 V
PDO I²C bit is set to 1 after this time is elapsed
V
OUT
forced at V
OUT_nom
+ 0.1 V, after PDO bit is set to 1
(I
SINK_TIME-OUT elapsed)
-3
70
10
2
-6 mA mA ms mA
T
DT
SHDN
SHDN
Thermal shutdown threshold
Thermal shutdown hysteresis
150
15
1. In applications where (V
CC
- V
OUT
) > 1.3 V, the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design.
2. Guaranteed by design.
3. Frequency range in which the DETIN function is guaranteed. The V pp
level is intended on the LNB bus (before the C6 capacitor. See typical application circuit for DiSEqC 2.x) I
OUT
from 0 to 750 mA, C
BUS
from 0 to 750 nF.
°C
°C page 24/35
8.1
LNBH26S
Output voltage selection
Output voltage selection
Each LNBH26S channel is provided with 15 output voltage levels (7 levels for 13 V range when VSEL4-A/B=0 and 8 levels for 18 V range when VSEL4-A/B=1) which can be selected through the register Data1.
13. Output voltage selection (data1 register, write mode)
shows the output voltage values corresponding to
VSELx bit combinations both for channel A and B. If all VSELx are set to “0” the device is set in standby mode and VOUT-A/B is disabled.
T
J
from 0 to 85 °C, V
I
= 12 V
Table 13. Output voltage selection (data1 register, write mode)
VSEL4-A/B VSEL3-A/B VSEL2-A/B VSEL1-A/B V
OUT
min. V
OUT
-A/B pin voltage V
OUT
max.
0 0 0 0 0
Function
V
OUT
-A/B disabled.
The LNBH26S sets in standby mode
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
1
0
0
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
12.545
12.867
13.188
13.51
13.832
14.153
14.475
17.515
17.836
18.158
18.48
18.801
19.123
19.445
19.766
13.000
13.333
13.667
14.000
14.333
14.667
15.000
18.150
18.483
18.817
19.150
19.483
19.817
20.150
20.483
13.455
13.800
14.145
14.490
14.835
15.180
15.525
18.785
19.130
19.475
19.820
20.165
20.510
20.855
21.200
T
J
from 0 to 85 °C, V
I
= 12 V
Table 14. I 2 C electrical characteristics
Symbol
V
IL
V
IH
I
IN
V
OL
F
MAX
Parameter
Low level input voltage
High level input voltage
Input current
Maximum clock frequency
1. Guaranteed by design.
Test conditions
SDA, SCL
SDA, SCL
SDA, SCL V
IN
= 0.4 to 4.5 V
SDA (open drain), I
OL
= 6 mA
SCL
T
J
from 0 to 85 °C, V
I
= 12 V
Min.
Typ.
Max.
Unit
0.8
V
2
-10 10
0.6
µA
V
400 kHz
DS8975 - Rev 5 page 25/35
LNBH26S
Output voltage selection
Note:
Note:
Note:
Symbol
V
ADDR-1
V
ADDR-2
Parameter
“0001000(R/W)” address pin voltage range
“0001001(R/W)” address pin voltage range
Table 15. Address pin characteristics
Test conditions
R/W bit determines the transmission mode: read (R/
W=1) write (R/W=0)
R/W bit determines the transmission mode: read (R/
W=1) write (R/W=0)
Min. Typ. Max. Unit
0 0.8
V
2 5 V
Refer to
Section 5 Typical application circuits , T
J
from 0 to 85 °C, all DATA 1..4 register bits set to “0”, RSEL = 11 kΩ, DSQIN = low, V
IN
= 12 V, I
OUT
= 50 mA, unless otherwise stated. Typical values are referred to T
J
= 25 °C.
V
OUT
= V
OUT
pin voltage.
Table 16. Output voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics
Symbol
V
TH-L
V
TH-L
Parameter Test conditions Min. Typ. Max. Unit
Diagnostic low threshold at V
OUT
= 13.0 V VSEL1 = 1, VSEL2 = VSEL3 = VSEL4 = 0 80 90
Diagnostic low threshold at V
OUT
= 18.15 V VSEL4=1, VSEL1 = VSEL2 = VSEL3 = 0 80 90
95
95
%
%
If the output voltage is lower than the min. value the VMON I²C bit is set to 1.
If VMON=0 then V
OUT
> 80% of V
OUT
(typ.).
If VMON=1 then V
OUT
< 95% of V
OUT
(typ.).
Refer to
Section 5 Typical application circuits
, T
J
from 0 to 85 °C, RSEL = 11 kΩ, DSQIN = low, V unless otherwise stated. Typical values are referred to T
J
= 25 °C. V
OUT
= V
OUT
pin voltage.
IN
= 12 V,
Symbol
I
TH
Table 17. Output current diagnostic (IMON-A/B bits, STATUS 2 register) characteristics
Parameter
Minimum current diagnostic threshold
Test conditions
EN_IMON = 1 (V
OUT
is set to 21 V typ.)
Min. Typ. Max. Unit
5 12 20 mA
If the output current is lower than the min. threshold limit, the IMON I²C bit is set to 1. If the output current is higher than the max. threshold limit, the IMON I²C bit is set to 0.
Refer to
Section 5 Typical application circuits , T
J
from 0 to 85 °C, all DATA 1..4 register bits set to “0” except
VSEL1 = 1, TEN=1, RSEL = 11 kΩ, DSQIN = HIGH, V
IN
= 12 V, I
OUT
= 50 mA, unless otherwise stated. Typical values are referred to T
J
= 25 °C. V
OUT
= V
OUT
pin voltage.
Symbol
A
TH-L
A
TH-H
F
TH-L
F
TH-H
Table 18. 22 kHz tone diagnostic (TMON-A/B bit, STATUS 2 register) characteristics
Parameter
Amplitude diagnostic low threshold
Amplitude diagnostic high threshold
Frequency diagnostic low thresholds
Frequency diagnostic high thresholds
Test conditions
DETIN pin AC coupled
DETIN pin AC coupled
DETIN pin AC coupled
DETIN pin AC coupled
Min.
Typ.
Max.
Unit
200 300 400 mV
900 1100 1200 mV
13
24
16.5
29.5
20
38 kHz kHz
If 22 kHz tone parameters are lower or higher than the above limits, the TMON I²C bit is set to “1”.
DS8975 - Rev 5 page 26/35
9
LNBH26S
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS8975 - Rev 5 page 27/35
9.1
LNBH26S
QFN24 (4x4 mm) package information
QFN24 (4x4 mm) package information
Figure 13. QFN24 (4x4 mm) package outline
D
E
Top view
A
6
7
Side view e
12
Nx b
A1
13
E2
1 18
24
D2
Bottom view
19
7596209_D
DS8975 - Rev 5 page 28/35
DS8975 - Rev 5
Dim.
E2 e
L
A
A1 b
D
D2
E
LNBH26S
QFN24 (4x4 mm) package information
Min.
0.80
0.00
0.18
3.90
2.55
3.90
2.55
0.45
0.25
Table 19. QFN24 (4x4 mm) mechanical data
0.25
4.00
2.70
4.00
Typ.
mm
0.90
0.02
2.70
0.50
0.35
Figure 14. QFN24 (4x4 mm) footprint recommended data
4.4
Max.
1.00
0.05
0.30
4.10
2.80
4.10
2.80
0.55
0.45
D2
0.25
E2
4.4
0.5
0.6
page 29/35
LNBH26S
Revision history
Date
27-Mar-2012
01-Oct-2012
12-Feb-2015
10-Apr-2018
14-Jun-2018
2
3
4
5
Table 20. Document revision history
Revision
1
Changes
Initial release.
Added: Section 2.12: "TMON: 22 kHz tone diagnostic",
Section 2.18: "ISW: inductor switching current limit",
Section 2.19: "COMP: boost capacitors and inductor",
Section 2.20: "OLF: overcurrent and short-circuit protection and diagnostic" and Section 2.21: "OTF: thermal protection and diagnostic".
Modified: Section 2.19: "COMP: boost capacitors and inductor".
Changed symbol I
MAX characteristics".
to I
LIM
in Table 13: "A/B section electrical
Added: T
JMAX
value Table 2. Absolute maximum ratings.
Updated
DS8975 - Rev 5 page 30/35
LNBH26S
Contents
Contents
Data encoding by external DiSEqC envelope control through the DSQIN pin. . . . . . . . . . . . . 3
DS8975 - Rev 5 page 31/35
LNBH26S
Contents
DS8975 - Rev 5 page 32/35
LNBH26S
List of tables
List of tables
DS8975 - Rev 5 page 33/35
LNBH26S
List of figures
List of figures
DS8975 - Rev 5 page 34/35
LNBH26S
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DS8975 - Rev 5 page 35/35
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