STMicroelectronics LNBH26LS Datasheet

LNBH26LS

Dual LNBS supply and control IC with step-up and I²C interface

Datasheet - production data

Features



Complete interface between then LNB and

I²C bus



Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ.

93% @ 0.5 A)



Selectable output current limit by external resistor



Compliant with main satellite receiver output voltage specification (8 programmable levels)



Accurate built-in 22 kHz tone generator suits widely accepted standards



22 kHz tone waveform integrity guaranteed also at no load condition



Low drop post regulator and high efficiency step-up PWM with integrated power NMOS allowing low power losses



Overload and overtemperature internal protection with I²C diagnostic bits



LNB short-circuit dynamic protection



+/- 4 kV ESD tolerant on output power pins

Applications



STB satellite receivers



TV satellite receivers



PC card satellite receivers

Description

Intended for analog and digital dual satellite receiver/Sat-TV, Sat-PC cards, the LNBH26LS is a monolithic voltage regulator and IC interface, assembled in QFN24 (4x4 mm) specifically designed to provide the 13/18 V power supply and the 22 kHz tone signaling to the LNB downconverter in the antenna dishes or to the multiswitch box. In this application field, it offers a complete solution for dual tuner satellite receivers with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

Table 1: Device summary

Order code Package Packing

LNBH26LSPQR

QFN24

(4x4 mm)

Tape and reel

April 2015 DocID025504 Rev 2

This is information on a product in full production.

1/35 www.st.com

Contents

Contents

LNBH26LS

1 Block diagram .................................................................................. 6

2 Application information (valid for each section A/B) .................... 7

2.1

DISEQC™ data encoding (DSQIN pin) ............................................. 7

2.2

Data encoding by external 22 kHz tone TTL signal ........................... 7

2.3

Data encoding by external DiSEqC envelope control through the

DSQIN pin ...................................................................................................... 8

2.4

2.5

2.6

2.7

2.8

Output current limit selection ............................................................. 8

Output voltage selection .................................................................... 8

Diagnostic and protection functions .................................................. 8

Surge protection and TVS diodes ..................................................... 9

Power-on I²C interface reset and undervoltage lockout .................... 9

2.9

PNG: input voltage minimum detection ............................................. 9

2.10

COMP: boost capacitors and inductor ............................................... 9

2.11

OLF: overcurrent and short-circuit protection and diagnostic .......... 10

2.12

OTF: thermal protection and diagnostic .......................................... 10

3 Pin configuration ........................................................................... 11

4 Maximum ratings ........................................................................... 14

5 Typical application circuits ........................................................... 15

6 I²C bus interface ............................................................................ 17

6.1

6.2

6.3

6.4

6.5

Data validity..................................................................................... 17

Start and stop condition .................................................................. 17

Byte format ...................................................................................... 17

Acknowledge ................................................................................... 17

Transmission without acknowledge ................................................. 17

7 I²C interface protocol .................................................................... 19

7.1

7.2

7.3

7.4

Write mode transmission ................................................................. 19

Read mode transmission ................................................................ 20

Data registers .................................................................................. 21

Status registers ............................................................................... 23

8 Electrical characteristics .............................................................. 25

8.1

Output voltage selection .................................................................. 27

9 Package information ..................................................................... 29

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LNBH26LS

9.1

9.2

Contents

QFN24L (4x4 mm) package information ......................................... 30

QFN24L (4x4 mm) packing information .......................................... 32

10 Revision history ............................................................................ 34

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List of tables

List of tables

LNBH26LS

Table 1: Device summary ........................................................................................................................... 1

Table 2: Pin description ............................................................................................................................ 12

Table 3: Absolute maximum ratings ......................................................................................................... 14

Table 4: Thermal data ............................................................................................................................... 14

Table 5: LNBH26LS DiSEqC 1.x bill of material ....................................................................................... 16

Table 6: DATA 1 (read/write register. Register address = 0X2) ............................................................... 21

Table 7: DATA 2 (read/write register. Register address = 0X3) ............................................................... 21

Table 8: DATA 3 (read/write register. Register address = 0X4) ............................................................... 22

Table 9: DATA 4 (read/write register. Register address = 0X5) ............................................................... 23

Table 10: STATUS 1 (read register. Register address = 0X0) ................................................................. 23

Table 11: STATUS 2 (read register. Register address = 0X1) ................................................................. 24

Table 12: Electrical characteristics of section A/B .................................................................................... 25

Table 13: Output voltage selection table (data1 register, write mode) ..................................................... 27

Table 14: I²C electrical characteristics ...................................................................................................... 27

Table 15: Address pin characteristics ....................................................................................................... 28

Table 16: QFN24L (4x4 mm) package mechanical data .......................................................................... 31

Table 17: QFN24L (4x4 mm) tape mechanical data ................................................................................. 32

Table 18: QFN24L (4x4 mm) reel mechanical data .................................................................................. 33

Table 19: Document revision history ........................................................................................................ 34

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LNBH26LS

List of figures

List of figures

Figure 1: Block diagram .............................................................................................................................. 6

Figure 2: Tone enable and disable timing (using an external waveform) ................................................... 7

Figure 3: Tone enable and disable timing (using envelope signal) ............................................................ 8

Figure 4: Surge protection circuit ................................................................................................................ 9

Figure 5: Pin connections (top view) ......................................................................................................... 11

Figure 6: LNBH26LS DiSEqC 1.X typical application circuit .................................................................... 15

Figure 7: Data validity on the I²C bus ....................................................................................................... 18

Figure 8: Timing diagram of I²C bus ......................................................................................................... 18

Figure 9: Acknowledge on the I²C bus ...................................................................................................... 18

Figure 10: Example of writing procedure starting with first data address 0x2 .......................................... 19

Figure 11: Example of reading procedure starting with first status address 0X0 ..................................... 20

Figure 12: QFN24L (4x4 mm) package outline ........................................................................................ 30

Figure 13: QFN24L (4x4 mm) recommended footprint ............................................................................. 31

Figure 14: QFN24L (4x4 mm) tape outline ............................................................................................... 32

Figure 15: QFN24L (4x4 mm) reel outline ................................................................................................ 33

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Block diagram

1 Block diagram

Figure 1: Block diagram

LNBH26LS

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LNBH26LS

2

2.1

2.2

Application information (valid for each section

A/B)

Application information (valid for each section A/B)

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (VUP) that let the integrated LDO post-regulator (generating the 13

V/18 V LNB output voltages plus the 22 kHz DiSEqC tone) work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at VUP -

VOUT = 1 V typ.). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V typically).

The step-up converter soft-start function reduces the in-rush current during startup. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. to switch from 0 to

18 V.

DISEQC™ data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC™ standards, and can be activated in 3 different ways:

1) By an external 22 kHz source DiSEqC™ data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1.

2) By an external DiSEqC™ data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1.

3) Through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled high and the EXTM bit set to “0”.

Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility, an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.

The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the LNBH26LS integrated tone generator.

The output tone waveforms are internally controlled by the LNBH26LS tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible

22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM a nd TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the

LNBH26LS activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN

has expired. Refer to Figure 2: "Tone enable and disable timing (using an external waveform)" .

Figure 2: Tone enable and disable timing (using an external waveform)

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Application information (valid for each section

A/B)

2.3

LNBH26LS

Data encoding by external DiSEqC envelope control through the DSQIN pin

If an external DiSEq C™ envelope source is available, the internal 22 kHz generator can be activated during the tone transmission by connecting the DiSEqC™ envelope source to the

DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. In this manner, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept high the internal control circuit activates the 22 kHz tone output.

The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the

22 kHz TTL signal on DSQIN has expired, refer to Figure 3: "Tone enable and disable timing (using envelope signal)" ).

Figure 3: Tone enable and disable timing (using envelope signal)

2.4 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit as per below equation:

Equation 1:

2.5

2.6

8/35 with ISET = 0, where RSEL is the resistor connected between ISEL and GND expressed in kW and

I

LIM

(typ.) is the typical current limit threshold expressed in mA. I

LIM

can be set up to 750 mA for each channel. However, do not exceed, for a long period of time, a total amount of current of 1 A from both sections (IOUT-A + IOUT-B < 1 A) in order to avoid the overtemperature protection triggering and to thoroughly validate the PCB layout thermal management in real application environment conditions.

Output voltage selection

Each linear regulator channel output voltage level can be easily programmed to accomplish application specific requirements, using 4 + 4 bits of an internal DATA1 register, see

Section 7.3: "Data registers"

and Table 13: "Output voltage selection table (data1 register, write mode)" for exact programmable values. Register writing is accessible via the I²C bus.

Diagnostic and protection functions

The LNBH26LS has 4 diagnostic internal functions provided via the I²C bus, by reading 4 bits on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that is, no failure detected), set to low. One diagnostic bit is dedicated to the

DocID025504 Rev 2

LNBH26LS Application information (valid for each section

A/B) overtemperature (OTF), and two bits (one per section) are dedicated to overcurrent (OLF-

A, OLF-B). One bit is dedicated to the input voltage power not good function (PNG). Once the OTF bit (or OLF-A, OLFB or PNG) has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is performed.

2.7 Surge protection and TVS diodes

Each LNBH26LS device section is directly connected to the antenna cable in a set-top box.

Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect each section of

STB output circuits where the LNBH26LS and other devices are electrically connected to the antenna cable.

Figure 4: Surge protection circuit

2.8

GIPD1311131146LM

For this purpose the use of LNBTVSxx surge protection diodes specifically designed by ST is recommended. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details).

Power-on I²C interface reset and undervoltage lockout

The I²C interface built into the LNBH26LS is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all data register bits are initialized to zero, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor.

2.9 PNG: input voltage minimum detection

When the input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum

thresholds, the PNG I²C bit is set to “1”. Refer to the Table 14: "I²C electrical characteristics" for threshold details.

2.10 COMP: boost capacitors and inductor

The DC-DC converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacitors (VUP pin). For this purpose, one I²C bit in the

DATA 4 register (see COMP not found) can be set to “1” or “0” as follows:

COMP = 0 for electrolytic capacitors

COMP = 1 for ceramic capacitors

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Application information (valid for each section

A/B)

LNBH26LS

For recommended DC-DC capacitor and inductor values refer to Section 5: "Typical application circuits" and to the BOM in Table 5: "LNBH26LS DiSEqC 1.x bill of material" .

2.11 OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. The shortcircuit current protection can be set either statically (simple current clamp) or dynamically through the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set to low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T

ON

time 90 ms and after that, the output is set as shutdown for a T

OFF time of typically 900 ms. Simultaneously, the corresponding diagno stic OLF I²C bit of the STATUS1 register is set to “1”. After this time has elapsed, the involved output is resumed for a time T

ON

. At the end of T

ON

, if the overload is still detected, the protection circuit cycles again through T

OFF

and T

ON

. At the end of a full T

ON in which no overload is detected, normal operation is resumed and the

OLF diagnostic bit is reset to low after the register reading. Typical T

ON

+ T

OFF

time is 990 ms and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, ensuring an excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL =1) and, then, switching to the dynamic mode (PCL = 0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is performed.

After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register.

If OLR=1, all VSEL bits, corresponding to the involved section, are reset to “0” and the LNB section output (VOUT pin) is disabled. To re-enable the output stage, the VSEL bits must be set again by the microprocessor and the OLF bit is reset to “0” after a register reading operation.

If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation.

2.12 OTF: thermal protection and diagnostic

The LNBH26LS is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and both linear regulators are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the

THERM I²C bit on the DATA4 register.

If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (VOUT pins) are disabled.

To re-enable the output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset t o “0” after a register reading operation.

If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.

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LNBH26LS

3 Pin configuration

Figure 5: Pin connections (top view)

Pin configuration

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Pin configuration

Pin n°

3

4

5

6

7

8

9

Symbol

LX-A

P-GND

LX-B

ADDR

SCL

SDA

ISEL

LNBH26LS

Table 2: Pin description

Name

NMOS drain

Power ground

NMOS drain

Address setting

Serial clock

Serial data

Current selection for channel A and B

Pin function

Channel A, integrated N-channel power MOSFET drain.

DC-DC converter power ground. To be connected directly to the exposed pad.

Channel B, integrated N-channel power MOSFET drain.

Two I²C bus addresses available by setting the

ADDRESS pin level voltage. See Table 15: "Address pin characteristics" .

Clock from I²C bus.

Bi-directional data from/to I²C bus.

The resistor “RSEL” connected between ISEL and

GND defines the linear regulator current limit

threshold. Refer to Section 2: "Application information (valid for each section A/B)" . The RSEL

resistor defines the same current limit for both channels (A and B).

1, 2, 13,

14, 15,

18, 19,

23

10

11

12

16

17

20

21

GND Analog ground

Analog circuit ground. To be connected directly to the exposed pad.

NC

VUP-B

VOUT-B

BYP

VCC

VOUT-A

VUP-A

Not internally connected

Not internally connected pin. Set floating if not used.

Channel B step-up voltage

Channel B,

LNB output port

Bypass capacitor

Supply input

Channel A,

LNB output port

Channel A step-up voltage

Input of channel B linear post-regulator. The voltage on this pin is monitored by the internal channel B step-up controller to keep a minimum dropout across the linear pass transistor.

Output of channel B integrated very low drop linear

regulator. Refer to Table 13: "Output voltage selection table (data1 register, write mode)" for

voltage selection and description.

Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to an external current or voltage sources may cause permanent damage to the device.

8 to 16 V IC DC-DC power supply.

Output of channel A integrated very low drop linear

regulator. Refer to Table 13: "Output voltage selection table (data1 register, write mode)" for

voltage selection and description.

Input of channel A linear post-regulator. The voltage on this pin is monitored by the internal channel A step-up controller to keep a minimum dropout across the linear pass transistor.

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LNBH26LS

Pin n°

22

24

Epad

Symbol

DSQIN-A

DSQIN-B

Epad

Name

DSQIN for

DiSEqC envelope input or external 22 KHz

TTL input

DSQIN for

DiSEqC envelope input or external 22 KHz

TTL input

Exposed pad

Pin configuration

Pin function

It is intended for channel A 22 kHz tone control.

It can be used as DiSEqC envelope input or external

22 kHz TTL input depending on the EXTM-A I²C bit setting as follows:

If EXTM-A=0, TEN-A=1: it accepts the DiSEqC envelope code from the main microcontroller. The

LNBH26LS uses this code to modulate the internally generated 22 kHz carrier.

If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which activate the 22 kHz tone output, refer

to Section 2.2: "Data encoding by external 22 kHz tone TTL signal" .

Pull up high if the tone output is activated only by the

TEN-A I²C bit.

It is intended for channel B 22 kHz tone control.

It can be used as DiSEqC envelope input or external

22 kHz TTL input depending on the EXTM-B I²C bit setting as follows:

If EXTM-B=0, TEN-B=1: it accepts the DiSEqC envelope code from the main microcontroller. The

LNBH26LS uses this code to modulate the internally generated 22 kHz carrier.

If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which activate the 22 kHz tone output, refer

to Section 2.2: "Data encoding by external 22 kHz tone TTL signal" .

Pull up high if the tone output is activated by TEN-B

I²C bit only.

To be connected with power grounds and to the ground layer through vias to dissipate the heat.

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Maximum ratings

4

LNBH26LS

Maximum ratings

Symbol

Table 3: Absolute maximum ratings

Parameter Value

V

CC

V

UP

I

OUT

V

OUT

V

I

LX

V

BYP

ISEL

T

STG

T

J

ESD

DC power supply input voltage pins

DC input voltage

Output current

DC output pin voltage

Logic input pin voltage (SDA,

SCL, DSQIN, ADDR pins)

LX input voltage

Internal reference pin voltage

Current selection pin voltage

Storage temperature range

Operating junction temperature range

ESD rating with human body model (HBM) all pins, unless power output pins

ESD rating with human body model (HBM) for power output pins

-0.3 to 20

-0.3 to 40

Internally limited

-0.3 to 40

-0.3 to 7

-0.3 to 30

-0.3 to 4.6

-0.3 to 3.5

-50 to 150

-25 to 125

2

4

Symbol

R thJC

R thJA

Table 4: Thermal data

Parameter

Thermal resistance junction-case

Thermal resistance junction-ambient with device soldered on

2s2p 4-layer PCB provided with thermal vias below the exposed pad

Value

2

40

Unit

V

V mA

V

V

V

V

V

°C

°C kV

Unit

°C/W

°C/W

Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal.

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LNBH26LS

5

Typical application circuits

Typical application circuits

Figure 6: LNBH26LS DiSEqC 1.X typical application circuit

D2-A

D1- A

L1-A

Vin

12 V

C1

L1-B

LNBOUT- A

21

V

UP- A

V

OUT- A 20

C2-A C3-A

3

LX-A

R1 (RSEL)

9

16

ISEL

Byp

C7

17

Vcc

C4

I 2 C Bus {

8

7

SDA

SCL

5

LX-B

LNBH26LS

DSQIN -A

22

DSQIN -B

24

ADDR

6

C5-A D3-A

Tone enable control

DiSEqC

22KHz

DiSEqC

Envelope or

TTL

TTL

D1-B

C2-B

C3-B

11

V

UP- B

P-GND

4 15

V

OUT-B

A-GND

12

C5-B D3-B

D2-B

LNBOUT-B

GIPG201517041137LM

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Typical application circuits

Component

R1 (RSEL)

C1

C2

C3

C5

C4, C7

D1

D2

D3

L1

LNBH26LS

Table 5: LNBH26LS DiSEqC 1.x bill of material

Notes

SMD resistor. Refer to Table 12: "Electrical characteristics of section A/B" and

ISEL pin description in Table 2: "Pin description" .

> 25 V electrolytic capacitor, 100 µF or higher is suitable or

> 25 V ceramic capacitor, 10 µF or higher is suitable.

With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable or with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is suitable.

From 470 nF to 2.2 µF ceramic capacitor placed as closer as possible to VUP pins.

Higher values allow lower DC-DC noise.

From 100 nF to 220 nF ceramic capacitor placed as closer as possible to VOUT pins. Higher values allow lower DC-DC noise.

220 nF ceramic capacitors. To be placed as closer as possible to VOUT pin.

STPS130A or similar Schottky diode.

1N4001-07, S1A-S1M, or any similar general purpose rectifier.

BAT54, BAT43, 1N5818, or any low power Schottky diode with I

F

(AV) > 0.2 A,

V

RRM

> 25 V, V

F

< 0.5 V. To be placed as closer as possible to VOUT pin.

With COMP=0, use 10 µH inductor with I

SAT

> I

PEAK

where I

PEAK

is the boost converter peak current, or with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with I

SAT

> I

PEAK

where I

PEAK

is the boost converter peak current.

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LNBH26LS

6

6.1

6.2

6.3

6.4

6.5

I²C bus interface

I²C bus interface

Data transmission from the main microprocessor to the LNBH26LS, and vice versa, takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).

Data validity

As shown in Figure 7: "Data validity on the I²C bus" , the data on the SDA line must be

stable during the high semi-period of the clock. The high and low state of the data line can only change when the clock signal on the SCL line is low.

Start and stop condition

As shown in Figure 8: "Timing diagram of I²C bus" , a start condition is a transition from high

to low of the SDA line while SCL is high. The stop condition is a transition from low to high of the SDA line while SCL is high. A stop condition must be sent before than each start condition.

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is the first to be transferred.

Acknowledge

The master (microprocessor) puts a resistive high level on the SDA line during the

acknowledge clock pulse, see Figure 9: "Acknowledge on the I²C bus" . The peripheral

(LNBH26LS), which acknowledges, must pull down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The peripheral, which has been addressed, must generate acknowledge after the reception of each byte, otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The LNBH26LS doesn’t generate acknowledge if the V

CC

supply is below the undervoltage lockout threshold (4.7 V typ.).

Transmission without acknowledge

If the detection of LNBH26LS acknowledge is not necessary, the microprocessor can use a simpler transmission; it simply waits for one clock without checking the slave acknowledging, and sends the new data. This approach has less protection in case of misworking and decreases noise immunity.

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I²C bus interface

Figure 7: Data validity on the I²C bus

LNBH26LS

Figure 8: Timing diagram of I²C bus

18/35

Figure 9: Acknowledge on the I²C bus

DocID025504 Rev 2

LNBH26LS

7

7.1

I²C interface protocol

I²C interface protocol

Write mode transmission

The LNBH26LS interface protocol is made up of:



A start condition (S)



A chip address byte with the LSB bit R/W = 0



A register address (internal address of the first register to be accessed)



A sequence of data (byte to write to the addressed internal register + acknowledge)





The following bytes, if any, to be written to successive internal x

A stop condition (P), the transfer lasts until a stop bit is encountered



The LNBH26LS, as slave, acknowledges every byte transfer

Figure 10: Example of writing procedure starting with first data address 0x2

ACK = acknowledge

S = start

P = stop

R/W = 1/0, read/write bit

X = 0/1, set the values to select the chip address, see Table 13: "Output voltage selection table (data1 register, write mode)" for pin selection and to select the register address, see

Table 6: "DATA 1 (read/write register. Register address = 0X2)"

and Table 10: "STATUS 1

(read register. Register address = 0X0)" .

The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped by the master by sending a stop condition after any acknowledge bit.

DocID025504 Rev 2 19/35

I²C interface protocol

7.2 Read mode transmission

LNBH26LS

In read mode the byte sequence must be as follows:



A start condition (S)



A chip address byte with the LSB bit R/W=0



The register address byte of the internal first register to be accessed



A stop condition (P)



A new master transmission with the chip address byte and the LSB bit R/W=1



After the acknowledge, the LNBH26LS starts sending the addressed register content.

As long as the master keeps the acknowledge low, the LNBH26LS transmits the next address register byte content



The transmission is terminated when the master sets the acknowledge high with a following stop bit

Figure 11: Example of reading procedure starting with first status address 0X0

20/35

ACK = acknowledge

S = start

P = stop

R/W = 1/0, read/write bit

X = 0/1, set the values to select the chip address, see Table 15: "Address pin characteristics"

for pin selection and to select the register address, see Table 6: "DATA 1

(read/write register. Register address = 0X2)" .

The reading procedure can start from any register address (STATUS 1, 2 or

DATA 1..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped by the master by sending a stop condition after any acknowledge bit.

DocID025504 Rev 2

LNBH26LS

7.3 Data registers

I²C interface protocol

The DATA 1..4 registers can be addressed both to write and read mode. In read mode they return the last writing byte status received in the previous write transmission.

The following tables provide the register address values of DATA 1..4 and a function description of each bit.

Bit

Table 6: DATA 1 (read/write register. Register address = 0X2)

Name CH Value Description

Bit 0 (LSb)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7 (MSb)

VSEL1-A

VSEL2-A

VSEL3-A

VSEL4-A

VSEL1-B

VSEL2-B

VSEL3-B

VSEL4-B

A

B

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

Channel A output voltage selection bits

refer to Table 13: "Output voltage selection table

(data1 register, write mode)"

Channel B output voltage selection bits

refer to Table 13: "Output voltage selection table

(data1 register, write mode)"

N/A = reserved bit.

All bits reset to “0” at power-on.

Bit

Table 7: DATA 2 (read/write register. Register address = 0X3)

Name CH Value Description

Bit 0 (LSb)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

TEN A

N/A

EXTM-A

N/A

TEN-B

N/A

EXTM-B

A

B

1

0

0

1

0

0

1

0

0

1

0

0

22 kHz tone enabled. Tone output controlled by the DSQIN pin

22 kHz tone output disabled

Reserved. Keep to “0”

DSQIN input pin is set to receive external 22 kHz TTL signal source

DSQIN input pin is set to receive external DiSEqC envelope TTL signal

Reserved. Keep to “0”

22 kHz tone enabled. Tone output controlled by the DSQIN pin

22 kHz tone output disabled

Reserved. Keep to “0”

DSQIN input pin is set to receive external 22 kHz TTL signal source

DSQIN input pin is set to receive external DiSEqC envelope TTL signal

Reserved. Keep to “0” Bit 7 (MSb) N/A

N/A = reserved bit.

All bits reset to “0” at power-on.

DocID025504 Rev 2 21/35

I²C interface protocol

Bit

Bit 0 (LSb)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7 (MSb)

LNBH26LS

Table 8: DATA 3 (read/write register. Register address = 0X4)

Name

N/A

N/A

CH Value

0

0

Description

Reserved. Keep to “0”

Reserved. Keep to “0”

PCL-A

N/A

N/A

N/A

PCL-B

N/A

A

B

1

0

0

0

0

1

0

0

Pulsed (dynamic) LNB output current limiting is deactivated

Pulsed (dynamic) LNB output current limiting is active

Reserved. Keep to “0”

Reserved. Keep to “0”

Reserved. Keep to “0”

Pulsed (dynamic) LNB output current limiting is deactivated

Pulsed (dynamic) LNB output current limiting is deactivated

Reserved. Keep to “0”

N/A = reserved bit.

All bits reset to “0” at power-on.

22/35 DocID025504 Rev 2

LNBH26LS

Bit

Bit 0 (LSb)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

I²C interface protocol

Table 9: DATA 4 (read/write register. Register address = 0X5)

Name CH Value Description

N/A

N/A

N/A

OLR

N/A

N/A

Bit 7 (MSB) COMP

A/B

-

-

-

-

-

THERM A/B

-

-

0

0

0

1

0

0

0

1

0

1

0

Reserved. Keep to 0

Reserved. Keep to 0

Reserved. Keep to 0

In case of overload protection activation (OLF=1), all VSEL 1..4 bits are reset to “0” and LNB output

(VOUT pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0)

In case of overload protection activation (OLF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overload condition is removed (OLF=0) with the previous VSEL bit setting

Reserved. Keep to 0

Reserved. Keep to 0

If thermal protection is active (OTF=1), all VSEL

1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=0)

In case of thermal protection activation (OTF=1) the

LNB output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed

(OTF=0) with the previous VSEL bit setting

DC-DC converter compensation: set to use very low E.S.R. capacitors or ceramic caps on VUP pin

DC-DC converter compensation: set to use standard electrolytic capacitors on VUP pin

7.4 Status registers

The STATUS 1, 2 registers can only be addressed to read mode and provide the diagnostic functions described in the following tables.

Bit

Table 10: STATUS 1 (read register. Register address = 0X0)

Name CH Value Description

Bit 0 (LSb) OLF-A

Bit 1 OLF-B

A

B

1

0

1

0

VOUT pin overload protection has been triggered

(I

OUT

> I

LIM

). Refer to Table 8: "DATA 3 (read/write register. Register address = 0X4)" for the

overload operation and PCL settings

No overload protection has been triggered to the

VOUT pin (I

OUT

< I

LIM

)

VOUT pin overload protection has been triggered

(I

OUT

> I

LIM

). Refer to Table 8: "DATA 3 (read/write register. Register address = 0X4)" for the

overload operation and PCL settings

No overload protection has been triggered to

VOUT pin (I

OUT

< I

LIM

)

DocID025504 Rev 2 23/35

I²C interface protocol

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

(MSb)

Name

N/A

N/A

N/A

N/A

OTF

PNG

CH

-

-

-

-

A/B

A/B

Value

-

-

-

-

1

0

1

0

LNBH26LS

Description

Reserved

Reserved

Reserved

Reserved

Junction overtemperature is detected, T

J

> 150 °C

(typ.). See also THERM bit setting in Table 9:

"DATA 4 (read/write register. Register address =

0X5)" .

Junction overtemperature not detected, T

J

< 135

°C (typ.). T

J

is below thermal protection threshold

Input voltage (VCC pin) lower than LPD minimum

thresholds. Refer to Table 12: "Electrical characteristics of section A/B"

Input voltage (VCC pin) higher than LPD

thresholds. Refer to Table 12: "Electrical characteristics of section A/B"

N/A = reserved bit.

All bits reset to “0” at power-on.

Bit

Bit 0

(LSb)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

(MSb)

Table 11: STATUS 2 (read register. Register address = 0X1)

Name CH Value Description

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

-

-

-

-

-

-

-

-

-

N/A = reserved bit.

All bits reset to “0” at power-on.

-

-

-

-

-

-

-

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

24/35 DocID025504 Rev 2

LNBH26LS

8

Electrical characteristics

Electrical characteristics

Refer to Section 5: "Typical application circuits" , T

J

from 0 to 85 °C, all DATA 1..4 register bits set to 0 unless VSEL1 = 1, RSEL = 11 kΩ, DSQIN = low, V

IN

= 12 V, I

OUT

= 50 mA, unless otherwise stated. Typical values are referred to T

J

= 25 °C. V

OUT

= V

OUT

pin voltage.

See software description section for Section 6: "I²C bus interface"

and Section 7: "I²C interface protocol" .

Symbol

V

IN

I

IN

V

OUT

V

OUT

V

OUT

I

LIM

I

SC

SS

SS

T13-18

T18-13

T

OFF

T

ON

A

TONE

Table 12: Electrical characteristics of section A/B

Parameter Test conditions Min. Typ.

Supply voltage

(1)

8 12

Supply current

Both sections A and B enabled,

I

OUT

= 0 mA

22 kHz tone enabled

(TEN-A/B = 1, DSQIN-

A/B = high), I

OUT

= 0 mA

12

19

Output voltage total accuracy

Line regulation

Load regulation

Output current limiting thresholds

Both sections A and B set in standby:

VSEL1=VSEL2=

VSEL3=

VSEL4=0

Valid at any V

OUT selected level

V

IN

= 8 to 16 V

I

OUT

from 50 to 500 mA

RSEL = 15 kΩ

RSEL = 20 kΩ

-3.5

500

350

2

75

Output short-circuit current

Soft-start time

Soft-start time

Soft transition rise time

RSEL = 15 kΩ

V

V

OUT

from 0 to 18 V

V

OUT

OUT

from 0 to 13 V

from 13 to 18 V

350

4

6

1.5

Soft transition fall time

Dynamic overload protection OFF time

Dynamic overload protection ON time

V

OUT

from 18 to 13 V

PCL = 0, output shorted

T

1.5

900

OFF

/10

Tone amplitude

PCL = 0, output shorted

DSQIN = high,

EXTM=0, TEN=1

I

OUT

from 0 to 500 mA

C

BUS

from 0 to 750 nF

0.55 0.675

Max. Unit

16

+3.5

40

100

750

550

0.8

V mA

% mV mA mA ms ms ms ms ms

V

PP

DocID025504 Rev 2 25/35

Electrical characteristics

Symbol

F

TONE

D

TONE tr, tf

Eff

DC/DC

F

SW

UVLO

V

LP

V

IL

V

IH

I

IH

I

OBK

I

SINK

I

SINK_TIME-

OUT

I

REV

T

SHDN

DT

SHDN

Parameter

Tone frequency

Tone duty cycle

Tone rise or fall

time

(2)

DC-DC converter efficiency

DC-DC converter switching frequency

Undervoltage lockout thresholds

I

OUT

= 500 mA

UVLO threshold rising

UVLO threshold falling

Low power diagnostic (LPD) thresholds

V

LP

threshold rising

V

LP

threshold falling

DSQIN, pin logic low

DSQIN, pin logic high

DSQIN, pin input current

Output backward current

Output low-side sink current

Low-side sink current time-out

Max. reverse current

V

IH

= 5 V

All VSELx = 0, V

30 V

V

OUT

forced at

V

OUT_nom

+ 0.1 V

V

OUT

forced at

V

OUT_nom

+ 0.1 V

OBK

V

OUT

forced at

V

OUT_nom

+ 0.1 V, after I

SINK_TIME-OUT is elapsed

=

Thermal shutdown threshold

Thermal shutdown hysteresis

Test conditions

DSQIN = high,

EXTM=0, TEN=1

Min.

20

43

5

2

Typ.

22

50

8

93

440

4.8

4.7

7.2

6.7

15

-3

70

10

2

150

15

LNBH26LS

Max. Unit

24

57

15

0.8

-6 kHz

%

µs

% kHz

V

V

V

V

µA mA mA ms mA

°C

°C

Notes:

(1)

In applications where (V

CC

- V

OUT

) > 1.3 V, the increased power dissipation, inside the integrated LDO, must be taken into account in the application thermal management design.

(2)

Guaranteed by design.

26/35 DocID025504 Rev 2

LNBH26LS

8.1 Output voltage selection

Electrical characteristics

Each LNBH26LS channel is provided with 8 output voltage levels, (4 levels for 13 V range when VSEL4-A/B=0 and 4 levels for 18 V range when VSEL4-A/B=1) which can be selected through the register data1. The following table shows the output voltage values corresponding to VSELx bit combinations both for channel A and B. If al l VSELx are at “0” the device is set in standby mode and the V

OUT

-A/B are disabled.

Table 13: Output voltage selection table (data1 register, write mode)

VSEL

4-A/B

VSEL

3-A/B

VSEL

2-A/B

VSEL

1-A/B

V

OUT min.

V

OUT

-A/B pin voltage

V

OUT max. Function

0 0 0 0 0

V

OUT

-A/B disabled.

The LNBH26LS is set in standby mode

0

0

0

0

1

1

1

1

0

0

0

1

0

0

0

0

0

1

1

0

0

0

1

1

1

0

1

0

0

1

0

1

12.545

12.867

13.188

13.51

17.515

17.836

18.158

18.48

13.000

13.333

13.667

14.000

18.150

18.483

18.817

19.150

13.455

13.800

14.145

14.490

18.785

19.130

19.475

19.820

T

J

from 0 to 85 °C, V

I

= 12 V.

Table 14: I²C electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

IL

V

IH

I

IN

V

OL

F

MAX

Low level input voltage high level input voltage

Input current

Low level output

voltage

(1)

Maximum clock frequency

SDA, SCL

SDA, SCL 2

SDA, SCL, V

IN

= 0.4 to 4.5 V -10

SDA (open drain), I

OL

= 6 mA

SCL

0.8

10

0.6

400

V

V

µA

V kHz

Notes:

(1)

Guaranteed by design.

DocID025504 Rev 2 27/35

Electrical characteristics

T

J from 0 to 85 °C, V

I

= 12 V.

LNBH26LS

Symbol

V

V

ADDR-1

ADDR-2

Parameter

Table 15: Address pin characteristics

Test conditions Min. Typ. Max. Unit

“0001000(R/W)” address pin voltage range

“0001001(R/W)” address pin voltage range

R/W bit determines the transmission mode: read

(R/W=1) write (R/W=0)

R/W bit determines the transmission mode: read

(R/W=1) write (R/W=0)

0

2

0.8

5

V

V

28/35 DocID025504 Rev 2

LNBH26LS

9

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

DocID025504 Rev 2 29/35

Package information

9.1 QFN24L (4x4 mm) package information

Figure 12: QFN24L (4x4 mm) package outline

LNBH26LS

30/35 DocID025504 Rev 2

LNBH26LS

Dim.

A

A1 b

D

D2

E

E2 e

L

Package information

Table 16: QFN24L (4x4 mm) package mechanical data mm

Min.

0.80

Typ.

0.90

Max.

1.00

0.00

0.18

3.90

2.55

3.90

2.55

0.45

0.02

0.25

4.00

2.70

4.00

2.70

0.50

0.25 0.35

Figure 13: QFN24L (4x4 mm) recommended footprint

0.05

0.30

4.10

2.80

4.10

2.80

0.55

0.40

DocID025504 Rev 2 31/35

Package information

9.2 QFN24L (4x4 mm) packing information

Figure 14: QFN24L (4x4 mm) tape outline

LNBH26LS

Table 17: QFN24L (4x4 mm) tape mechanical data

Dim. mm

A0

B0

K0

4.35

4.35

1.1

32/35 DocID025504 Rev 2

LNBH26LS

Figure 15: QFN24L (4x4 mm) reel outline

Package information

Dim.

Reel 13”

Table 18: QFN24L (4x4 mm) reel mechanical data

R1 R2

13 330

R3

60

DocID025504 Rev 2 33/35

Revision history

10 Revision history

Date Revision

Table 19: Document revision history

Changes

04-Dec-2013

20-Apr-2015

1

2

Initial release.

Updated section 2.11.

Updated package information section.

Changed figure 6.

LNBH26LS

34/35 DocID025504 Rev 2

LNBH26LS

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DocID025504 Rev 2 35/35