The STA321 is part of the Sound Terminal™ family that together with the digital power stage provides full digital audio streaming to the speaker, offering cost effectiveness, low energy dissipation and sound enrichment.

The STA321 input section consists of two multiplexed stereo analog inputs, a 16-bit ADC and two independent digital input interfaces. The serial audio data input interface accepts all possible formats, including the popular I

S format. There is also a digital output interface fed by the ADC or by the digitally processed signals.

The device has a full assortment of digital processing features. This includes sample rate converter, pre and post mixing, up to 13 programmable 28-bit biquads (EQ) per channel, bass/treble tone control and DRC. The embedded headphone detector indicates when headphone jack is inserted.

The STA321 provides four independent channels of FFX™ output capabilities. In conjunction with a power device, it provides high-quality, high-efficiency, all digital amplification.

The embedded CMOS bridge supplies up to 0.5 W into an 8Ω load and 70 mW into a 16Ω load for the headphones output.

Figure 1.

STA321 block diagram

V_BIAS

VCM

VHI

VLO

BICLKI1

LRCLKI1

SDATAI1

BICLKI2

LRCLKI2

SDATAI2

INL1

INL2

INR1

INR2

HPDET

Bias

Serial audio interface

PGA

ADC

PGA

HP detection

Serial audio interface

4-channel

SRC

Osc PLL Divider

FFX™ modulator

EAFTN

EATSN

EAPDN

CMOS headphone bridge

EAPWM4

EAPWM3

EAPWM2

EAPWM1

OUT1

OUT2

OUT3

PWM00

C interface

Doc ID 15351 Rev 3 9/157

Pin description

Figure 2.

Pin out

GND3

PWM00

HPDET

GND33

VCC33

SCL

VCC1

OUT1

GND1

GND2

OUT2

VCC2

VCC3

OUT3

STA321

STA321

VDDIO2

VDD_REG2

DGND2

I2CDIS

ACLK

EAPDN

EATSN

EAFTN

EAPWM1

EAPWM2

EAPWM3

EAPWM4

STBY

RSTN

INL1

10/157

Table 2.

Pin Pull

1 -

3 -

6 -

9 -

11 -

12 -

13 -

14 -

Pin list

Name

SCL

OUT1

OUT2

OUT3

PWM00

HPDET

Type Description

In (digital), schmitt tr I

C serial clock, schmitt trigger input

Out (analog)

HP/line-out PWM 1

HP/line-out PWM 2

HP/line-out PWM 3

Not connected

Out (digital)

In (analog)

Auxiliary PWM

Not connected

Headphone detection

Doc ID 15351 Rev 3

STA321 Pin description

24 -

26 -

27 -

29 -

30 -

31 -

32 -

33 -

Table 2.

Pin Pull

17 -

18 -

19 H

21 -

34 H

35 -

36 -

37 -

38 -

39 -

40 H

41 -

42 -

43 -

44 L

48 L

51 -

Pin list (continued)

Name Type Description

BIAS

VLO

VHI

INR1

INR2

VCM

INL2

INL1

CLKOUT

SDA

MUTE

REG_BYPASS

RSTN

STBY

EAPWM4

EAPWM3

EAPWM2

EAPWM1

EAFTN

EATSN

EAPDN

ACLK

I2CDIS

Out (digital)

In/Out (digital)

In (digital)

In (analog)

Buffered clock output

C serial data

Mute (active high)

DC regulator bypass:

0: normal operation, regulator enabled

1: regulator bypassed

ADC microphone bias voltage In/Out (analog)

In (analog)

In/Out (analog)

In (analog)

In (digital)

ADC low reference voltage

ADC high reference voltage

ADC right channel line input1

ADC right channel line input2

ADC common mode voltage

ADC left channel line input2 or microphone input2

ADC left channel line input1 or microphone input1

Reset:

0: reset state

1: normal operation

Standby mode:

0: normal operation

1: power-down

External amplifier PWM 4B Out (digital)

Out (digital)

External amplifier PWM 4A

External amplifier PWM 3B

External amplifier PWM 3A

Out (digital)

External power fault signal:

0: fault

1: normal operational mode

External amplifier control:

0: active

1: 3-state

External amplifier powerdown (active low) Out (digital)

In (digital), schmitt tr Reserved pin, connect to ground

In (digital)

C disable:

0: I

C enabled

1: I

C disabled

In (digital)

Test mode:

0: normal operation

Not connected

Doc ID 15351 Rev 3 11/157

Pin description STA321

52 -

53 -

54 -

55 -

56 -

57 -

58 -

59 -

60 -

Table 2.

Pin Pull

61 -

62 -

63 -

64 -

XTO

XTI

MCLK

SDATAI2

SDATAI1

SDATAO2

SDATAO1

LRCLKI2

LRCLKI1

Pin list (continued)

Name

LRCLKO

BICLKI2

BICLKI1

BICLKO

Type Description

Out (digital), 1.8 V Crystal output

In (digital), 1.8 V Crystal input or master clock input

In (digital), schmitt tr Master clock input 3.3-V compatible, schmitt input

In (digital)

Out (digital)

In/Out (digital)

Input serial audio interface data

Output serial audio interface data

Input serial audio interface L/R-clock

Output serial audio interface L/R-clock

(volume DOWN when I2CDIS=1)

In/Out (digital)

Input serial audio interface bit clock

Output serial audio interface bit clock

(volume UP when I2CDIS=1)

Table 3.

Number

VCC1

GND1

GND2

VCC2

VCC3

GND3

GND33

VCC33

DGND1

VDD_REG1

VDDIO1

AGND

AVDD

DGND2

VDD_REG2

VDDIO2

PVDD

PGND

Power supply pin list

Name Type Description

Supply CMOS bridge channel 1 supply

Ground CMOS bridge channel 1 ground

Ground CMOS bridge channel 2 ground

Supply CMOS bridge channel 2 supply

Supply CMOS bridge channel 3 supply

Ground CMOS bridge channel 3 ground

Ground CMOS bridge level shifter ground

Supply CMOS bridge level shifter supply

Ground Digital ground

Supply DC regulator unit supply

Supply 3.3-V IO supply

Ground ADC analog ground

Supply ADC analog supply

Ground Digital ground

Supply DC regulator unit supply

Supply 3.3-V IO supply

Supply PLL analog supply

Ground PLL analog ground

12/157 Doc ID 15351 Rev 3

STA321 Electrical specifications

3.1

Note:

3.2 Absolute maximum ratings

Table 4.

Absolute maximum ratings

Pin name/Symbol Parameter

VDD_REG1,

VDD_REG2

VDDIO1, VDDIO2

Digital supply voltage

PVDD

AVDD

Digital IO supply voltage

PLL analog supply voltage

ADC analog supply voltage

VCC1, VCC2, VCC3 CMOS bridge supply voltage

VCC33 CMOS bridge level shifter power supply

STG

Storage temperature

Operating junction temperature

All grounds must always be within 0.3 V of each other.

Negative Positive Unit

-0.3

-40

-20

4.0

150

125

°C

Recommended operating conditions

Table 5.

Recommended operating conditions

Symbol Parameter

VDD_REG1

VDD_REG2

PVDD

AVDD

VCC1

, V

VCC3

VCC2

Digital supply voltage

PLL analog supply voltage

ADC analog supply voltage

CMOS bridge supply voltage

VCC33

VDDIO1

, V

VDDIO2

T amb

CMOS bridge level shifter power supply.

Ensure that V

VCC33

<= V

VCCx

always

3.3-V IO supply

High input voltage, 1.8-V pads

High input voltage, 3.3-V pads

Low input voltage, 1.8-V pads

Low input voltage, 3.3-V pads

Ambient temperature

1.55

2.7

1.3

2.0

Min

2.5

1.8

1.55

Typ

3.3

Max

3.6

3.3

Unit

3.3

3.6

0.6

0.8

°C

Doc ID 15351 Rev 3 13/157

Electrical specifications STA321

Unless otherwise specified, the results in

Table 6 below are given for the operating

conditions V

= 3.3 V, R to default conditions.

= 32 Ω , f

MCLK

= 12.288 MHz, Tamb = 25 °C and with the PLL set

Table 6.

Symbol

Electrical specifications

Parameter

General

V hys

STBYIO

DDIO

STBYL0

STBYL1

DDL1

STBYPD

Test conditions Min Typ

High output voltage, 1.8-V pads

High output voltage, 3.3-V pads -

Low output voltage, 1.8-V pads

Low output voltage, 3.3-V pads

Schmitt trigger hysteresis, 3.3-V IO -

= 2 mA

Pull-up resistance -

Pull-down resistance

Standby current, pins VDDIO1,2

Pin STBY = 3.3 V

CLKOUT disabled

Operating current, pins VDDIO1,2 -

Standby current, pins VDD_REG1,2

Deep power-down,

VDD_REG1,2

= 3.3 V

Standby current, pins VDD_REG1,2

Mild power-down,

VDD_REG1,2

= 3.3 V

Operating current, pins VDD_REG1,2 f

MCLK

= 12.288 MHz, Play from SAI to CMOS bridge and EAPWM, f

ADC

= 48 kHz on SAI_out, V

AVDD

= 3.3 V,

VDD_REG1,2

= 3.3 V

Pre-drive supply current in standby, pin VCC33

1.4

VDDIO

- 0.15

0.4

450

4.7

Max Unit

0.15

V mA

µA mA mA

µA

V k Ω k Ω

µA

14/157 Doc ID 15351 Rev 3

STA321 Electrical specifications

Table 6.

Symbol

Electrical specifications (continued)

Parameter Test conditions Min Typ

DDP

DDPD t

R t

Amplifier (CMOS bridge)

η Output power efficiency

Output power in HP mode with

THD = 1%

HPOUT

Output power in HP mode with

THD = 10%

SNR Signal to noise ratio

THD + N

3.3-V supply R

= 32 Ω

Total harmonic distortion plus noise

20 Hz to 20 kHz

RL = 32 Ω

HP mode

0 dBFs In

-6 dBFs In

STBYP

Dynamic range

Current in standby, pins VCCx

Operating current, pins VCCx

Pre-drive supply current in operation, pin VCC33

Driver rise time, pins OUT1-3

Driver fall time, pins OUT1-3

A-weighted

No LC filter, no load,

PWM at 50% duty-cycle

No load,

PWM at 50% duty-cycle

Resistive load, see

Figure 3

Resistive load, see

Figure 3

DSON

OCH

OCL

Headphone output stage N/P MOS on-resistance

Over-current limit for OUT1-3 to

VCCx short circuit

Over-current limit for OUT1-3 to ground short circuit

PLL

STDBYPLL

DDPLL f

CLKIN_Range

Duty

CLKIN t

CLKIN_RF f

F_INT f

VCO_Range

Duty

VCO

LOCK

PLL supply current in standby

PLL supply current in operation

Input clock frequency range

Input clock duty cycle

Input clock rise/fall time

PFD input clock frequency

Clock out range

Clock out duty cycle

Lock time

PLL_FR_CTRL = 1

250

500

1.88

1.72

2.048

0.4

2.048

65.536 -

35 -

0.3

0.05

Max Unit

350

700

% mW dB

% dB

µA mA

µA ns ns m Ω

1.0

µA mA

49.152 MHz

0.2

% ns

12.288 MHz

98.304 MHz

65 %

200 µs

Doc ID 15351 Rev 3 15/157

Electrical specifications STA321

Table 6.

Symbol

Electrical specifications (continued)

Parameter Test conditions

ADC

DDA

STDBYA

SNR

ADC

THD

ADC

Supply current in operating mode

AVDD supply current in standby

Dynamic range

Signal to noise ratio

Total harmonic distortion

Channel cross talk

Group delay

Pass band

Pass band ripple

Stop band attenuation

Frequency response

AVDD

= 3.3V

AVDD

= 3.3V

1 kHz, A-weigthed

AVDD

= 3.3 V

1 kHz, A-weighted

AVDD

= 3.3 V

1 kHz, -1dB

AVDD

= 3.3 V

AVDD

= 3.3 V

Fs mode (f

= 32 kHz) -

Fs_by_2 mode (f

= 16 kHz) -

Fs_by_4 mode (f

= 8 kHz) -

Fs mode (f

= 44.1 kHz)

Fs_by_2 mode

= 22.05 kHz)

Fs_by_4 mode

= 11.025 kHz)

Fs mode (f

= 44.1 kHz)

Fs_by_2 mode

= 22.05 kHz)

Fs_by_4 mode

= 11.025 kHz)

-3 dB

-0.08 dB at 20 Hz -

Linear phase deviation

Pass-band ripple

Headphone detector threshold limits

HP low threshold

E_HP1

E_HP2

HP high threshold

HP low threshold

HP high threshold

Min Typ

0.4

0.7

1.4

0.4535 -

0.08

2.34

2.52

0.7

0.9

19.35

0.08

Max Unit

15 mA

µA dB dB dB dB ms

Fs dB dB

Hz deg dB

16/157 Doc ID 15351 Rev 3

STA321

Figure 3.

Test circuit

Electrical specifications

R = 32 Ω

Figure 4.

Oscillator configuration

To PLL

Enable from register bit MISC[7]

STA321

XTI XTO

Doc ID 15351 Rev 3 17/157

Electrical specifications STA321

The STA321 has an integrated oscillator between pins XTI and XTO.

The architecture is a single-stage oscillator with an inverter working as an amplifier. The oscillator stage is biased by an internal resistor (of about 500 k

Ω

), and requires an external

PI network consisting of a crystal and two capacitors as shown in Figure 4

below. An enable feature is provided in bit 7 of register MISC (address 0xC8) to stop the oscillator and thereby to reduce power consumption.

Not all crystals operate satisfactorily with the type of oscillator used in the STA321. To find out if a crystal is suitable for this device the following transconductance formula must be evaluated and compared to the critical transconductance for the embedded oscillator:

Gm = Rm * ω 2

* (C + 2 * Co)

< Gm

CRITICAL

/ 3 where ω is the crystal operating frequency, C = CA = CB, Co and Rm are shown in

Figure 5

and Gm

CRITICAL is given in

Table 7

Figure 5.

Equivalent circuit of crystal and external components

Table 7.

Symbol

Oscillator specifications

Parameter Min Typ Max Unit

OSC

Oscillator power consumption with crystal connected

(1)

215

Duty

OSC

Duty cycle

Startup time

CRITICAL

Oscillator

46.9

1060 -

47.8% 48.9

15 *

τ x -

If no crystal is connected then the power consumption could be much higher.

τ x is the time constant of the crystal and external components; a typical value is 44 µs.

µA

% s

(2)

µA/V

18/157 Doc ID 15351 Rev 3

STA321 Electrical specifications

The power supply to the digital STA321 core and PLL is provided via embedded linear DC regulators as shown below in

Figure 6 . When pin REG_BYPASS is tied to ground, the DC

regulators are active so that a voltage in the range 2.5 V to 3.6 V applied to pins VDD_REGx or PVDD provides a regulated internal voltage to the core and the PLL. The voltages Vddi and Vddipll range from 1.55 V to 1.95 V depending on operating conditions.

Figure 6.

Embedded DC regulator scheme

VDD_REG1

VDD_REG2

Vddi

Core

REG_BYPASS

PVDD

Vddipll PLL

STA321

If the application allows multiple supplies or the power supply requirements are a fundamental constraint, pin REG_BYPASS can be tied high and a 1.8 V external supply can be applied directly to pins VDD_REGx and PVDD. In this case the operating range for such an external supply is 1.55 V to 1.95 V.

Embedded DC regulators imply also static power consumption that must be take into account when the power-down modes are active. The STA321 provides a deep powerdown mode where also the regulators are active but in a low power consumption mode (see

Section 4.3.2 on page 27 ).

Doc ID 15351 Rev 3 19/157

Power-up and power-down sequences

4 Power-up and power-down sequences

STA321

After providing the power supply to the device, it is necessary to wait until the DC regulator

PWUP time has elapsed before the device can be set up and used for normal operations.

(see Figure 7

Figure 7.

Startup sequence

3v3

2v2

20/157

RSTN (active L)

DC Reg. PWDN

PWDN (active H)

DC Reg. A. OK

C clock

User configuration via I 2 C

Vdd ramp

DC reg. PWUP time

Device in reset mode

VDDIO

VDD_REG

PVDD

STBY

RSTN

PWDN

A. OK

C read

C clock

XTI/MCLK

Table 8.

Signal/pin

Power-up signal description

Type

Supply

In (digital)

Internal

In (I

Internal

In (digital)

Description

Power supply of the digital pads (= VDDIO1,2)

Power supply of the system core (= VDD_REG1,2)

Power supply of the PLL

External standby signal provided by the user

External reset signal provided by the user

Power-down of the DC regulator cell, controlled by the core

DC regulator status, when active the 1.8 V is provided to the core

Configuration commands coming to the I

C interface

C peripheral clock

Clock input source

Doc ID 15351 Rev 3

STA321 Power-up and power-down sequences

Table 9.

Startup timings

Parameter

DC reg. power-up time

Device in reset mode

Description

Start up time of the DC Regulator after connecting the power

Must be greater than

(VDD time + DC reg. power-up time)

Min

Typ

Max Unit

300 µs

µs

Table 10.

Configuration example

Register address

Value

0xC9

0xCA

0xB8

0xB7

0xC6

0xB2

0xC8

0xB2

0xA0

0x00

0x4A

0x38

0x02

0xF3

0x21

0xD3

0x00

Description

Remove PLL bypass

Headphone detection polarity = 0

Configure SAI output: SAI_out1 = SAI_in1, SAI_out2 = SAI_in2

SRC source select: SRC1 = ADC, SRC2 = ADC

ADC clock on

S configuration

Core clock on, SAI/ADC audio set to 32 kHz - 48 kHz range

SAI_out: output enabled

Soft volume removed

Remove bridge 3-state

The software power-down is obtained by configuring the appropriate I

C registers.

In order to obtain flexibility every peripheral has its independent, standby signal and several gating clock cells are available.

Obviously, the I

C peripheral can not be turned off in this mode, otherwise the device can recover from the power-down state only via the reset pin.

In the table below EA is embedded amplifier and CB is CMOS bridge. For complete information this table must be used in conjunction with

Chapter 14: Register description on page 77

Table 11.

Registers for power-down

Description

Put EA in standby

Put CB in standby

Put PLL in standby

Put ADC in standby

Turn core clock off

Turn ADC clock off

Register bit

FFXCFG1

[7]

FFXCFG1

[6]

PLLPFE [5]

ADCCFG0

[3]

MISC

[0]

ADCCFG0

[1]

Address

0x00

0xC6

Doc ID 15351 Rev 3 21/157

Power-up and power-down sequences

Table 11.

Registers for power-down (continued)

Description Register bit

Turn SRC clock off

Turn PROC clock off

Turn FFX clock off

CKOCFG [3]

CKOCFG [2]

CKOCFG [4]

STA321

Address

0xC7 on page 134

0xC7

Note:

This is an example of the register setup for power-down clock. It is assumed that every peripheral is already configured and working correctly.

There are other configuration examples to help you get started please refer to other chapters and also to

Chapter 14: Register description on page 77

in order to get all the necessary and complementary details.

Turn off all the peripherals.

The MCLK (or XTI) must be used as system clock (sys_clk) before setting the PLL to standby.

Table 12.

Example configurations for power-down

Register bit Address Value

EA_STBY

CB_STBY

0x00 on page 81

0xC0

CLK_FFX_ON

0xC7 on page 134

0x0C

ADC_STBY

0xC6 on page 133

0x09

CLK_ADC_ON

0xC6

0x80

CLK_PROC_ON

0xC7

CLK_SRC_ON

0xC7

0x08

0x00

PLL_BYP_UNL

0xC4 on page 132

0x80

PLL_PWDN

0xC4

0xA0

CLK_CORE_ON

0xC8 on page 135

0x00

Description

Set the embedded power amplifier and CMOS bridge to power-down

Turn off the FFX modulator clock

Set the ADC into standby mode

Turn the ADC clock off

Turn the processing clock off

Turn the sample rate converter clock to off

Bypass the PLL clock and use MCLK (or XTI) as source clock when the PLL is not locked (a safety operational mode)

Put the PLL in standby

Turning off the core clock

22/157 Doc ID 15351 Rev 3

STA321

4.3

Power-up and power-down sequences

Hardware power-down mode

The hardware power-down is obtained by asserting pin STBY to high.

There are two power-down options available, namely mild mode and full (or deep) mode, that could be selected using the DC_STBY_EN signal in register STBY_MODES

Figure 8 summarizes the main power-down sequence. “Power on” is the normal operating

status where all the startup procedures have already been executed. The rectangular boxes indicate the steps to be done by the user whilst the rounded boxes indicate the steps done by the device.

Figure 8.

Hardware power-done sequence

Power on

I 2 C programming register

STBY_MODES bits:

CMP_EN_N

DC_STBY_EN

Pin STBY <= 1'

CMP_EN_N = 1 ?

YES

Comp Cell Pwdn

DC_STBY_EN = 1 ?

YES

DC Reg. Stby

Embedded amp.

CMOS bridge

Powerdown

CLK_I2C off

CLK_ADC off

CLK Core off

PLL power down

Power-down mode

Doc ID 15351 Rev 3 23/157

Power-up and power-down sequences

Table 13.

Frequently used signals

Name

Input pin STBY on page 11 STBY

PWDN

DC regulator

A. OK

DC regulator

CMP_EN_N

EA_STBY

CB_STBY

EA/CB volume

PLL_UNLOCK

PLL_PWDN

CLK_PROC_ON

CLK_PROC

CLK_FFX_ON clk_ffx

CLK_ADC_ON clk_adc

CLK_SRC_ON clk_src

CMP_EN_N

DC_STBY_EN

FFX_ULCK_PLL

Internal

Description

Bit 1, register

STBY_MODES on page 139

Bits 7:6, register

FFXCFG1 on page 81

Internal

Bit 7, register

PLLST on page 132

Bit 5, register

PLLPFE on page 132

Bit 2, register

CKOCFG on page 134

Processing clock

Bit 4, register

CKOCFG on page 134

FFX clock

Bit 1, register

ADCCFG0 on page 133

ADC clock

Bit 3, register

CKOCFG on page 134

SRC clock

Bit 1, register

STBY_MODES on page 139

Bit 0, register

STBY_MODES on page 139

Bits 4:3, register

FFXCFG1 on page 81

STA321

24/157 Doc ID 15351 Rev 3

STA321 Power-up and power-down sequences

In this case, the device is put into a mild power-down mode.

All the peripherals are set to standby and their clocks turned off.

The I

C configuration is not required as the default values of the registers are sufficient.

z Initial conditions:

FFX_ULCK_PLL = 10 z

CMP_EN_N = 0

DC_STBY_EN = 0

Going into power-down:

After the assertion of the pin STBY, the following actions are taken by the device:

Embedded amplifier (EA) and CMOS bridge (CB) volume are set to mute (the length of this step changes according to the fade-out ramp configuration).

2. EA and CB are put into power-down.

After the previous operation is completed:

3. All peripherals are turned off (regardless the register settings).

4. The PLL clock is bypassed, the system clock (sys_clk in

Figure 11 on page 29

) is XTI.

5. All clocks are shut down.

z Returning to normal mode:

After the release of the pin STBY, the power-up procedure takes place:

All clocks are turned on.

2. All peripherals are restored to their previous status (based on the last register settings).

3. If the PLL clock was the system clock it will be selected again after the locking time.

4. The EA and the CB execute the fade-in procedure before becoming ready to be used

(the length of this step changes according to the fade-in ramp configuration).

Doc ID 15351 Rev 3 25/157

Power-up and power-down sequences

Figure 9.

Hardware powerdown sequence (mild mode)

STBY (active H)

DC Reg. PWDN

(active High)

DC Reg. A. OK

(active High)

Comp Cell PWDN

(active High)

EA is in Pwdn

EA Volume Operational Volume

CB is in Pwdn

CB Volume Operational Volume

PLL LOCKED

(active High)

PLL_PWDN

(active High)

I2C [CORE_CLK_ON]

CLK_I2C

I2C [CLK_PROC_ON]

CLK_PROC_CLK

I2C [CLK_FFX_ON]

CLK_FFX_CLK

I2C [CLK_ADC_ON]

CLK_ADC_CLK

I2C [CLK_SRC_ON]

CLK_SRC_CLK

MUTE

E.A Fade Out

Bridge Fade Out

PLL Locking Time

E.A Fade In

Bridge Fade In

O.V.

STA321

26/157 Doc ID 15351 Rev 3

STA321 Power-up and power-down sequences

In this case the device is put into a full power-down mode.

This implies lower power consumption than the mild mode, but has a drawback in that it takes longer to execute. z Initial conditions

FFX_ULCK_PLL = 10 z

CMP_EN_N = 1

DC_STBY_EN = 1

Going into power-down:

This mode differs from the previous one by an additional step at the end of the powerdown procedure and at the beginning of the power-up:

Embedded amplifier (EA) and CMOS bridge (CB) volume are set to mute (the length of this step changes according to the fade-out ramp configuration).

2. EA and CB are put into power-down.

After the acknowledge signals (EA is in power-down and CB is in power-down) are received:

3. All peripherals are turned off (regardless the register settings).

4. PLL clock is bypassed, the system clock (sys_clk in

Figure 11 on page 29

) is XTI.

5. All clocks are shut down.

6. DC regulator is put into standby mode. After this point the device is in a very low power consumption mode.

z Returning to normal mode:

After the release of pin STBY, the power-up procedure will take place:

DC regulator is set to operational mode

After the acknowledge signal (DCAOK) from the DC regulator is received:

2. All clocks are turned on.

3. All peripherals are restored to the status based on their relative register settings.

4. If the PLL clock was the system clock it is selected again after the locking time.

5. The EA and the CB execute the fade-in procedure before being ready to be used (the length of this step changes according to the fade-in ramp configuration).

Doc ID 15351 Rev 3 27/157

Power-up and power-down sequences

Figure 10.

Hardware power-down sequence (full mode)

DC- Tdown

DC- Tup

STBY (active H)

DC Reg. PWDN

(active High)

DC Reg. A. OK

(active High)

Comp Cell PWDN

(active High)

EA is in Pwdn

EA Volume Operational Volume

CB is in Pwdn

CB Volume Operational Volume

PLL LOCKED

(active High)

PLL_PWDN

(active High)

I2C [CORE_CLK_ON]

CLK_I2C

I2C [CLK_PROC_ON]

CLK_PROC_CLK

I2C [CLK_FFX_ON]

CLK_FFX_CLK

I2C [CLK_ADC_ON]

CLK_ADC_CLK

I2C [CLK_SRC_ON]

CLK_SRC_CLK

MUTE

E.A Fade Out

Bridge Fade Out

PLL Locking Time

E.A Fade In

Bridge Fade In

O.V.

STA321

28/157 Doc ID 15351 Rev 3

STA321 Clock management

Figure 11.

Clock management scheme

BICLKI1

MCLK

XTI

CKOCFG[6:5]

CLKOUT_SEL

PLLPFE[6]

BICLK2PLL

0 pll_clk_in_i sys_clk

1/2

1/8

1/4

00 1

PLL

PLLB[7]

MISC[0]

CLK_CORE_ON

CKOCFG[4]

CLK_FFX_ON

CKOCFG[3]

CLK_SRC_ON

CKOCFG[2]

CLK_PROC_ON

ADCCFG[1]

CLK_ADC_ON

Clock management

1/2 clk_i2c

1/2

1/2 clk_ffx clk_src clk_proc clk_adc

ADC

1/4 0

CLKOUT

FFX

SAI_in1

SAI_in2 clk_adc_in

PLLB[5] ADC_CLKSEL clk_proc

PLLB[3] P2S1_CLKSEL

PLLB[1] P2S2_CLKSEL

SAI_out1

SAI_out2

Table 14.

Clock control registers

Register Name

PLLB on page 136

ADCCFG0 on page 133

CKOCFG on page 134

0xC9

0xC6

0xC7

Address

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Clock management

Table 15.

Clock characteristics

Symbol Parameter f

MCLK_Range

Duty

MCLK t

MCLK_RF f

XTI_Range

Duty

XTI t

XTI_RF f

BICLK1_Range

Duty

BICLK1

Input clock frequency range

Input clock duty cycle

Input clock rise/fall time

Input clock frequency range

Input clock duty cycle

Input clock rise/fall time

Input clock frequency range

Input clock duty cycle t

BICLK1_RF

Input clock rise/fall time f

CLKOUT_Range

Output clock frequency range

STA321

Min

2.048

40 -

2.048

Typ Max Unit

49.152 MHz

0.2

% ns

49.152 MHz

60 %

0.2

49.152 MHz

0.2

% ns

49.152 MHz

30/157 z z

Figure 11

above shows the STA321 clock management scheme with all the major clocks. As can be seen, the system clock (sys_clk) is selected from one of three sources by using register

PLLB on page 136

: z an external clock BICLKI1

(default) an external clock XTI or MCLK (the unused one must, however, be set to 0) the internal PLL.

If the PLL is used there are some design constraints: z pll_clk_in_i must be in the range: 2.048 MHz to 49.152 MHz z pll_clk_out must be in the range: 65.536 MHz to 98.304 MHz.

The sys_clk is routed to the peripherals through the clock manager section.

This is an example of the PLL register setup. It is assumed that every peripheral is already configured and working correctly.

There are other configuration examples to help you get started please refer to other chapters and also to

Chapter 14: Register description on page 77

in order to get all the necessary and complementary details.

Starting with MCLK as system clock switching to PLL as source

Table 16.

Register setup to provide sys_clk from MCLK to PLL

Register Address Value Description

PLLPFE

PLLB

0xC4

0xC9

0x80

0x00

Safety operational mode: automatic use of MCLK (or XTI) as system clock if the PLL is not locked

Remove the PLL bypass and use its clock as system

Doc ID 15351 Rev 3

STA321

5.2

Clock management

Peripheral clock manager

This block manages the clocks of the core processing peripherals ADC, FFX, PROC

(including memories and SAI interfaces) and SRC.

A clock divider (by 2) is attached before every block except the FFX.

Each block is attached to a global gating cell and to a dedicated one. This allows a flexible power-consumption management because it is possible to turn off either the whole processing chain or just a single block. The only exception is the I

C peripheral clock which is disabled only when the device is in hardware power-down mode. In all the other cases this clock remains active.

The PLL specifications are given in Table 6 on page 14

Figure 12.

PLL block diagram pll_clk_in

PLL_CLK_in

PLL_PWDN

IDF

Input freq. divider

F_INT

Lock detect

Buffer PFD

LPF cpump VCO

LDF

Loop freq. divider

Fractional controller

5.3.1

DITHER

FRAC

PLLCFG0[5:4]

PLLCFG2(7-0)

PLLCFG1[7:0]

PLLCFG2[7:0]

PLL block description

Phase/frequency detector (PFD)

This block compares the phase difference between the corresponding rising edges of the

F_INT and the clock coming from the loop frequency divider.

It generates voltage pulses with widths proportional to the input phase error.

Charge pump and loop filter (LPF/CPUMP)

This block converts the voltage pulses from the phase/frequency detector to current pulses which charge the loop filter and generate the control voltage for the voltage controlled oscillator (VCO).

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Clock management STA321

Voltage controlled oscillator (VCO)

This is the oscillator inside the PLL, which produces a frequency, f

VCO

, on output FVCO proportional to the input control voltage.

Input frequency divider (IDF)

This frequency divider divides the PLL input clock CLKIN by the input division factor (IDF) to generate the PFD input frequency. IDF is programmed in register PLLCFG0[3:0].

Loop frequency divider (LDF)

This frequency divider is present within the PLL for dividing the VCO output by the loop division factor (LDF). LDF is programmed in register bits PLLCFG3[5:0].

Lock circuit

The output of this block, signal LOCKP, is asserted high when the PLL enters the state of coarse lock in which the output frequency is ±10% of the desired frequency. LOCKP is

refreshed every 32 cycles of F_INT. The status bit PLL_UNLOCK is in register PLLST on page 132

32/157

The input clock frequency of the phase/frequency detector (PFD) is f

F_INT

= CLKIN / IDF

The VCO frequency depends on the value of register bit PLLCFG0.PLL_FR_CTRL such that

When PLL_FR_CTRL = 1 f

VCO

= f

F_INT

* (LDF + FRAC / 2

+ 1 / 2

) and when PLL_FR_CTRL = 0 f

VCO

= f

F_INT

* LDF

Notes:

1. When dither is disabled (PLL_DDIS = 1), the factor 1 / 2

is not used in the multiplication.

2. There are some limits to the input and output frequencies as given in Table 17

and

Table 18

when selecting the values for IDF, LDF, and FRAC.

3. The LDF values of 5, 6 and 7 cannot be used when fractional synthesis mode is on, that is, when PLL_FR_CTRL = 1.

4. The fractional control bits (FRAC_INPUT) must be set to the required values before activating the fractional synthesis mode.

Table 17.

Input division factor (IDF)

IDF[3] IDF[2] IDF[1]

…

IDF[0]

…

Input division factor (IDF)

Doc ID 15351 Rev 3

STA321 Clock management

Table 17.

Input division factor (IDF) (continued)

IDF[3] IDF[2] IDF[1] IDF[0]

Input division factor (IDF)

Table 18.

Loop division factor (LDF)

NDIV[5] NDIV[4] NDIV[3] NDIV[2] NDIV[1] NDIV[0] Loop division factor (LDF)

…

1 x x

…

1 x x

…

1 x

(1)

6 (see note 3)

7 (see note 3)

…

The LDF values of 5, 6 and 7 cannot be used when fractional synthesis mode is ON (PLL_FR_CTRL = 1)

Doc ID 15351 Rev 3 33/157

Digital processing stage

6 Digital processing stage

STA321

The STA321 provides 4 channels of audio signal processing. The block diagram is shown in the following figure.

Figure 13.

Processing flow

Sample rate converter

- G0

- G1

- G2

- G3

Pre scaler

Bq0 Bq12

EQ - tone control

13 biquads kZ

-1 kZ

-1

Delay

Vol 0

Vol 1

Vol 2

Vol 3

Volume control Limiter

Left and right channels coming from the two serial audio interfaces and ADC (left and right channels) are fed into the selection multiplexer (controlled by register

SRCINSEL on page 128

), so that each channel can be connected to any desired processing chain. The four channels are then sample rate converted to the fixed internal sampling rate. Pre mix,

EQ/tone processing, programmable delay, post mix, and volume/limiter make up the

STA321 signal processing chain.

Figure 14.

Processing data multiplexer

SRCINSEL[7:6]

SAI_in1

ADC

SAI_in2

SAI_in1

ADC

SAI_in2

SRC1

SRC2

24 ch0_in ch1_in

PROC ch0

PROC ch1

PROC ch2

PROC ch3

Processing ch2_in ch3_in ch0_out ch1_out ch2_out ch3_out

To SAI_out multiplexers

FFX

SRCINSEL[5:4]

2-channel signal

1-channel signal

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STA321 Digital processing stage

Figure 15.

SAI_out data multiplexer

P2SDATA[5:3]

ADC (L/R)

SAI_in1 (L/R)

SAI_in2 (L/R)

SRC1 (L/R)

SRC2 (L/R)

PROC (ch0/ch1)

PROC (ch2/ch3)

000

001

010

011

100

101 else

SAI_out1

ADC (L/R)

SAI_in1 (L/R)

SAI_in2 (L/R)

SRC1 (L/R)

SRC2 (L/R)

PROC (ch0/ch1)

PROC (ch2/ch3)

000

001

010

011

100

101 else

SAI_out2

P2SDATA[2:0]

2-channel signal

1-channel signal

6.2 Sampling rate converter

The sample rate converter (SRC) re samples the input data source in order to send to the processing block an audio stream always with a fixed frequency: sampling frequency, f

= f sys_clk

/ 1024 where f sys_clk

is the system clock frequency.

In all the examples given here, f

= 96 kHz.

Figure 16.

Sample rate converter block diagram

Data input

Interpolation

FIR x2

Interpolation

FIR x2

Data output

Precomp.

FIR

Sync 6 async.

Threshold selector

LRCK_IN

DRLL

Ratio

The selection between x2 FIR interpolation and direct input data is made automatically by the threshold selector block. If the input sampling frequency (measured by the DRLL) is higher than the SRC threshold (that is, more than 81 kHz) the direct connection is selected

(first filter bypassed), otherwise the first x2 filter is added to the data path.

A 3-kHz hysteresis is fixed around the SRC threshold nominal value in order to prevent unstable oscillations.

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Digital processing stage

6.3

STA321 ch0_in ch1_in ch2_in ch3_in

Pre-EQ mix 1 and post-EQ mix

The four-channel data, received from the sample rate converters, is sent to Mix1 block to produce the four mixed-channel data for processing. All this data can be mapped to any internal processing channel through the appropriate configuration of the RAM memory locations.

Table 19.

Channel mapping

Function Channel

Pre mixer

Post mixer

Ch0

Ch1

Ch2

Ch3

Ch0

Ch1

Ch2

Ch3 from 0x00 from 0x04 from 0x08 from 0x0c from 0x118 from 0x11c from 0x120 from 0x124

Memory location (RAM)

The post-EQ mixer acts in a similar way for the output channels from the processing and directed to the FFX. It is placed after the delay block which provides a full 4-channel input mix on every channel.

Figure 17.

Mixers block diagram ch0_in pos: 0x118

G0_0 pre: 0x00 ch1_in pre: 0x01 pos: 0x119

G0_1 ch0_out

+ ch2_in ch3_in pre: 0x02 pos: 0x11A

G0_2 pos: 0x11B

G0_3 pre: 0x03 ch0_in ch1_in ch2_in ch3_in

G2_0 pre: 0x08 pos: 0x120

G2_1 pre: 0x09 pos: 0x121

G2_2 pre: 0x0A pos: 0x122

G2_3 pre: 0x0B pos: 0x123 ch2_out pre: 0x04 pos: 0x11C

G1_0 pre: 0x05 pos: 0x11D

G1_1 pre: 0x06 pos: 0x11E

G1_2

G1_3 pre: 0x07 pos: 0x11Ff

+ ch1_out ch0_in ch1_in ch2_in ch3_in

G3_0 pre: 0x0C pos: 0x124

G3_1 pre: 0x0D pos: 0x125

G3_2 pre: 0x0E pos: 0x126

G3_3 pre: 0x0F pos: 0x127 ch3_out

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STA321 Digital processing stage

6.3.1 Presets

By default, each mixer output is connected to its corresponding input without any attenuation and without any mixing with the other channels: ch0_out = ch0_in, ch1_out = ch1_in, ch2_out = ch2_in, ch3_out = ch3_in.

The pre scale block, which precedes the first biquad, could be used to attenuate the input signal when the filters of the processing chain have a gain that could reach the clamping value.

Each channel has a dedicated 24-bit signed multiplier in the range -1 (0x800000) to almost

+1 (0x7FFFFF).

6.4.1 Presets

By default, all pre-scale factors are set to 0x7FFFFF

6.5 Equalization, tone control and effects

Figure 18.

EQ/tone block diagram

From prescaler

Biquad

Reserved Reserved

Biquad

08 effects_en[0]

Biquad

09 effects_en[1]

Biquad

Reserved

RAM Reserved RAM Reserved RAM High pass

RAM Deemph.

RAM Reserved

RAM Treble RAM Bass treb_sel bass_sel

To delay stage

Biquad

Four channels of input data are fed to the EQ processing block which provides 13

user-programmable biquad filters per channel as shown in Figure 18 above.

A description of the biquad programming is given in Section 6.14 on page 44 .

Some filter coefficients are pre-programmed and stored in the non-volatile memory in order

to supply particular EQ effects (see Figure 19 and Table 20 on page 38 ).

The selection of RAM, ROM bass/treble or ROM effects is made using registers

EFFS_EN_CHn

on page 109

for the effects and BASS_SELn_R

on page 111

and

TREB_SELn_R on page 113

for the bass/treble. Each biquad can be configured independently.

Doc ID 15351 Rev 3 37/157

Digital processing stage

Figure 19.

Biquad coefficient selection

RAM

ROM - Effects

Coefficients

Biquads (00-10)

STA321

RAM

ROM - Effects

ROM - Bass

ROMCHxx_

ROMCHxx & BASS_SELxx

Coefficients

Biquads (11)

RAM

ROM - Effects

ROM - Trebl.

Table 20.

EQ control signals

Signal name Description

ROMCHxx & TREB_SELxx

Coefficients

Biquads (12) effects_en[1] bass_sel[5] treb_sel[5]

1: enable deemphasysa filter

1: enable bass tone control

1: enable treble tone control

Channel

Ch0

Ch1

Ch2

Ch3

Ch0

Ch1

Ch2

Ch3

Ch0

Ch1

Ch2

Ch3

Register addr

0x71

0x73

0x77

0x78

0X79

0X7A

0X7B

0X7C

0X7D

0X7E

0X7F

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STA321 Digital processing stage

6.6 Biquads

The biquads are based on the following equation and is shown diagramatically in

Figure 20

Y[n] = b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2] where Y[n] represents the output and X[n] represents the input. Fractional multipliers are 24-bit signed with coefficient values in the range -1 (0xFFFFFF) to +1 (0x7FFFFF).

Figure 20.

Biquad filter b0/2 2 +

Z -1 b1/2 2 +

2 -a1/2 Z -1

Z -1 b2

-a2 Z -1

6.6.1 Presets

By default all the biquads values in RAM are set to give a bypass function; in actual fact, the signal passes through unchanged. The coefficients for this are: a1 / 2 = 0, a2 / 2 = 0, b0 / 2 = 0.5 (0x400000), b1 / 2 = 0, b2 / 2 = 0.

The standard high-pass filter is provided by the STA321

Figure 21.

High-pass filter frequency response

High Pass Filter

−5

−10

−15

−20

−25

−30

Freq. [Hz]

Doc ID 15351 Rev 3 39/157

Digital processing stage

The standard deemphasis filter is provided by the STA321.

Figure 22.

Deemphasis filter frequency response

STA321

40/157 Doc ID 15351 Rev 3

STA321

6.9

Digital processing stage

Bass and treble control

Preset values for the 11th and 12th biquads of every channel are stored in ROM in order to achieve a bass and treble tone control.

They are channel independent and have 24 curves ranging from -12 to +12 dB gain with

1 dB steps. Their selection (and enable) is via registers BASS_SELx_R and TREB_SELx_R where x is the number of the channel to be equalized.

The EQ curve and filter cut-off frequencies are shown in

Figure 23 and Figure 24 .

With a sampling frequency of 96 kHz (inside the processing block), the cut-off frequencies are 3 kHz for treble curves and 150 Hz for bass curves.

Figure 23.

Frequency responses of treble control at 1-dB gain steps

Figure 24.

Frequency responses of bass control at 1-dB gain steps

Doc ID 15351 Rev 3 41/157

Digital processing stage STA321

This is an example of the tone control register setup. It is assumed that every peripheral is already configured and working correctly.

Table 21

gives the register values to obtain +12 dB of bass on all channels and -10 dB of treble on channels 0 and 1.

Table 21.

Selecting EQ curves

Register - Address Programmed value

BASS_SEL0_R

BASS_SEL1_R

BASS_SEL2_R

BASS_SEL3_R

TREB_SEL0_R

TREB_SEL1_R

0x38

0x22

0xx22

CH0 +12 dB bass

CH1 +12 dB bass

CH2 +12 dB bass

CH3 +12 dB bass

CH0 -10 dB treble

CH1 - 10 dB treble

Description

Every channel, just after the biquads stage, is connected to a dedicated delay block.

The length of the delay is stored in RAM at location 0x128 and can vary from 0 to 35 samples. The corresponding time delay depends on the processing sampling frequency.

6.10.1 Presets

The delay of every channel is set to 0.

6.11 Volume and mute control

The STA321 provides a flexible volume and mute control stage. Using the registers

VOLCH0

VOLCH3 on page 122

it is possible to set the volume for each channel individually from

+36 dB to -105 dB with 0.5-dB steps.

There is a master volume control, register MVOL on page 120 , as well. The master volume

adds an offset to all the individual volume settings.

The mute function offers the possibility to turn off the sound by reducing the volume setting to -127.5 dB. It could be activated in two ways: z register

FFXCFG0 on page 82

provides a dedicated mute control for each channel.

z pin MUTE, driven by an external signal, puts all four channels into mute mode.

VOLCFG on page 120

provides some flexibility to set how the mute and volume change procedures are applied. If bit SVOL_ONx is activated the volume of channel x is changed gradually (soft volume or soft mute); using a ramp it starts from the current value and goes down to the target value or to -127.5 dB for mute. The slope of the ramp is set with with the value TIM_SVOL which represents how many samples are needed to achieve a

0.5-dB step.

STEP

= 2

TIM_SVOL

/ f

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STA321 Digital processing stage

The ramp procedure ends when the target volume or mute level is reached. The time for the volume change is calculated as: t

CHANGE

= (volume

CURRENT

- volume

TARGET

) / 0.5 * t

STEP

If SVOL_ONx is not used, the volume and mute are set instantaneously.

The STA321 also has the possibility to put the FFX into mute in the event of bad input data using register FFXCFG0. If bit BAD_CKS_M is set to 1 the FFX is muted when BICLK and

LRCLK do not meet the specifications. If MIS_BICK_M is set to 1 the FFX is muted when

BICLK is missing. The mute can be applied gradually or abruptly via bit BAD_IN_M.

The saturation stage provides an individual or a global limitation on the output signal amplitude such that if the signal is above the limiting value then it is truncated (clamped).

A 23-bit saturation value made up using registers SATCHxCFG1, SATCHxCFG2 and

SATCHxCFG3 can be set for each channel x.

However, if bit 7 of register

SATCH0CFG1 on page 116

is set to 1, all the channels take the saturation value of channel 0 and ignore the individual settings.

6.13 FFX channel re-mapping

Figure 25.

FFX re-mapping

Processing block

Channle 0

Channel 1

Channel 2

Channel 3

FFX block

FFX ch1 pwm_1a pwm_1b

FFX ch2 pwm_2a pwm_2b

FFX ch3 pwm_3a pwm_3b

FFX ch4 pwm_4a pwm_4b

Channel re-map cb1_map cb_pwm_1 cb_pwm_2 cb2_map cb_pwm_3 cb3_map pwm_00 pwm00_map ea1a_map ea1b_map ea2a_map ea2b_map ea_pwm_1a ea_pwm_1b ea_pwm_2a ea_pwm_2b

CMOS bridge

OUT1

OUT2

OUT3

The channels are re-mapped through registers

PWMMAP1

, PWMMAP2

and PWMMAP3 on page 86

. The default configuration routes the channels directly to their respective CB/EA signals: pwm_1a -> cb_pwm_1 pwm_1b -> cb_pwm_2 pwm_2a -> cb_pwm_3 pwm_2b -> pwm_00 (PWM00) pwm_3a -> ea_pwm_1 (EAPWM1) pwm_3b -> ea_pwm_2 (EAPWM2) pwm_4a -> ea_pwm_3 (EAPWM3) pwm_4b -> ea_pwm_4 (EAPWM4)

Doc ID 15351 Rev 3 43/157

Digital processing stage STA321

Table 22 on page 47

shows the RAM mapping for the programmable functions in the signal processing stage. Changing or reading this data is done through the I

C interface in either

single-word mode or in multi-word mode. Register PROCCTRL on page 107 sets the

desired mode and whether to read or write: z z

1-word mode: this is for write only; the address of the memory location must be specified in registers

START_ADDR2 and

START_ADDR1 on page 108

and the value of the parameter must

be written into registers I2CB0_TOP

I2CB0_MID and I2CB0_BOT on page 102

5-word mode: in this case it is possible to write/read 5 contiguous locations. Only the address of the first one must be specified in registers START_ADD1-2, all the others are generated automatically. The values of the parameters must be placed in (or taken from) registers

The 5-word mode is particular useful during the biquad programming when a set of five coefficients needs to be updated. Not only is it more efficient to change all of them at the same time but it avoids the generation of possible unpleasant acoustical side-effects.

The following sections explain how to implement this programming using the I

C interface.

6.14.1 Writing one coefficient/location to RAM z z z z z

Write RAM address to registers START_ADDR2

and

START_ADDR1

(b0) Write 8 MSBs of coefficient in register

I2CB0_TOP

Write 8 middle bits of coefficient in register

I2CB0_MID

Write 8 LSBs of coefficient in register

I2CB0_BOT

Write 1 to bit W1 in register

PROCCTRL

Figure 26.

Writing RAM location

Write address to

START_ADDR[8:0]

0x61 = address[8]

0x62 = address[7:0]

Write top 8 bits of coefficient

0x51 = top_val

Write middle 8 bits of coefficient

0x52 = mid_val

Write bottom 8 bits of coefficient

0x53 = bot_val

Write 1 to bit W1 in PROC_CTRL

0x60 = 0x01

44/157 Doc ID 15351 Rev 3

STA321 Digital processing stage z z z z z z z z z z z z z z z z z

6.14.2 Writing a set of five coefficients/locations to RAM

Write RAM address of b0 to registers

START_ADDR2

and START_ADDR1

(b0) Write 8 MSBs of coefficient in register

I2CB0_TOP

Write 8 middle bits of coefficient in register

I2CB0_MID

Write 8 LSBs of coefficient in register

I2CB0_BOT

(b1) Write 8 MSBs of coefficient in register

I2CB1_TOP

Write 8 middle bits of coefficient in register

I2CB1_MID

Write 8 LSBs of coefficient in register

I2CB1_BOT

(b2) Write 8 MSBs of coefficient in register

I2CB2_TOP

Write 8 middle bits of coefficient in register

I2CB2_MID

Write 8 LSBs of coefficient in register

I2CB2_BOT

(a1) Write 8 MSBs of coefficient in register

I2CA1_TOP

Write 8 middle bits of coefficient in register

I2CA1_MID

Write 8 LSBs of coefficient in register

I2CA1_BOT

(a2) Write 8 MSBs of coefficient in register

I2CA2_TOP

Write 8 middle bits of coefficient in register

I2CA2_MID

Write 8 LSBs of coefficient in register

I2CA2_BOT

Write 1 to bit WA in register

PROCCTRL .

Figure 27.

Writing five contiguous RAM locations

Write address to

START_ADDR[8:0]

0x61 = address[8]

0x62 = address[7:0]

Write top 8 bits of coefficient

Write middle 8 bits of coefficient

Write bottom 8 bits of coefficient

0x51/0x54/0x57/0x5A/0x5D

= top_val

0x52/0x55/0x58/0x5B/0x5E

= mid_val

0x53/0x56/0x59/0x5C/0x5F

= bot_val

Repeat for all 5 coefficients

Write 1 to bit WA in PROC_CTRL

0x60 = 0x02

Doc ID 15351 Rev 3 45/157

Digital processing stage z z z z z z z z z z z z z z z z z

6.14.3 Reading a set of five coefficients/locations from RAM

Write RAM address of b0 to registers

START_ADDR2

and START_ADDR1

Write 1 to bit RA in register PROCCTRL

(b0) Read 8 MSBs of coefficient in register

I2CB0_TOP

Read 8 middle bits of coefficient in register I2CB0_MID

Read 8 LSBs of coefficient in register

I2CB0_BOT

(b1) Read 8 MSBs of coefficient in register

I2CB1_TOP

Read 8 middle bits of coefficient in register I2CB1_MID

Read 8 LSBs of coefficient in register

I2CB1_BOT

(b2) Read 8 MSBs of coefficient in register

I2CB2_TOP

Read 8 middle bits of coefficient in register I2CB2_MID

Read 8 LSBs of coefficient in register

I2CB2_BOT

(a1) Read 8 MSBs of coefficient in register

I2CA1_TOP

Read 8 middle bits of coefficient in register I2CA1_MID

Read 8 LSBs of coefficient in register

I2CA1_BOT

(a2) Read 8 MSBs of coefficient in register

I2CA2_TOP

Read 8 middle bits of coefficient in register I2CA2_MID

Read 8 LSBs of coefficient in register

I2CA2_BOT

Figure 28.

Reading five contiguous RAM locations

Write address to

START_ADDR[8:0]

0x61 = address[8]

0x62 = address[7:0]

STA321

Write 1 to bit RA in PROC_CTRL

0x60 = 0x08

Read top 8 bits of coefficient top_val =

0x51/0x54/0x57/0x5A/0x5D

Read middle 8 bits of coefficient mid_val =

0x52/0x55/0x58/0x5B/0x5E

Read bottom 8 bits of coefficient bot_val =

0x53/0x56/0x59/0x5C/0x5F

Repeat for All 5 Coefficients

46/157 Doc ID 15351 Rev 3

STA321 Digital processing stage

0x011 ch1

0x012 ch2

0x013 ch3

0x014 #0 b0

0x015 #0 b1

0x016 #0 b2

0x017 #0 a2

0x018 #0 a1

0x019 #1 b0

0x01A #1 b1

0x01B #1 b2

0x01C #1 a2

0x01D #1 a1

0x01E #2 b0

0x01F #2 b1

0x020 #2 b2

0x000 ch0i

0x001 ch1i

0x002 ch2i

0x003 ch3i

0x004 ch0i

0x005 ch1i

0x006 ch2i

0x007 ch3i

0x008 ch0i

0x009 ch1i

0x00A ch2i

0x00B ch3i

0x00C ch0i

0x00D ch1i

0x00E ch2i

0x00F ch3i

0x010 ch0

Table 22.

RAM mapping for processing stage

Addr Descr.

Default Block Addr Descr.

0x000000

0x400000

0x000000

0x400000

0x000000

0x7FFFFF

0x000000

Pre mix: ch0

0x000000

0x7FFFFF

Pre mix: ch1

0x000000

0x7FFFFF

Pre mix: ch2

0x000000

0x7FFFFF

Pre mix: ch3

0x7FFFFF

Pre scaler

0x7FFFFF

0x400000

0x000000

Ch0-biquad

0x032 #6 b0

0x033 #6 b1

0x034 #6 b2

0x035 #6 a2

0x036 #6 a1

0x037 #7 b0

0x038 #7 b1

0x039 #7 b2

0x03A #7 a2

0x03B #7 a1

0x03C #8 b0

0x03D #8 b1

0x03E #8 b2

0x03F #8 a2

0x040 #8 a1

0x041 #9 b0

0x021 #2 a2

0x022 #2 a1

0x023 #3 b0

0x024 #3 b1

0x025 #3 b2

0x026 #3 a2

0x027 #3 a1

0x028 #3 b0

0x029 #4 b1

0x02A #4 b2

0x02B #4 a2

0x02C #4 a1

0x02D #5 b0

0x02E #5 b1

0x02F #5 b2

0x030 #5 a2

0x031 #5 a1

Default Block

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x000000 (Ch0-biquad)

Doc ID 15351 Rev 3 47/157

Digital processing stage STA321

Table 22.

RAM mapping for processing stage (continued)

Addr Descr.

Default Block Addr Descr.

0x042 #9 b1

0x043 #9 b2

0x044 #9 a2

0x045 #9 a1

0x046 #10 b0

0x047 #10 b1

0x048 #10 b2

0x049 #10 a2

0x04A #10 a1

0x04B #11 b0

0x04C #11 b1

0x04D #11 b2

0x04E #11 a2

0x04F #11 a1

0x050 #12 b0

0x051 #12 b1

0x052 #12 b2

0x053 #12 a2

0x054 #12 a1

0x055 #0 b0

0x056 #0 b1

0x057 #0 b2

0x058 #0 a2

0x059 #0 a1

0x05A #1 b0

0x05B #1 b1

0x05C #1 b2

0x05D #1 a2

0x05E #1 a1

0x05F #2 b0

0x060 #2 b1

0x061 #2 b2

0x062 #2 a2

0x063 #2 a1

0x064 #3 b0

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

(Ch0-biquad)

Ch1-biquad

0x065 #3 b1

0x066 #3 b2

0x067 #3 a2

0x068 #3 a1

0x069 #3 b0

0x06A #4 b1

0x06B #4 b2

0x06C #4 a2

0x06D #4 a1

0x06E #5 b0

0x06F #5 b1

0x070 #5 b2

0x071 #5 a2

0x072 #5 a1

0x073 #6 b0

0x074 #6 b1

0x075 #6 b2

0x076 #6 a2

0x077 #6 a1

0x078 #7 b0

0x079 #7 b1

0x07A #7 b2

0x07B #7 a2

0x07C #7 a1

0x07D #8 b0

0x07E #8 b1

0x07F #8 b2

0x080 #8 a2

0x081 #8 a1

0x082 #9 b0

0x083 #9 b1

0x084 #9 b2

0x085 #9 a2

0x086 #9 a1

0x087 #10 b0

Default Block

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

(Ch1-biquad)

48/157 Doc ID 15351 Rev 3

STA321 Digital processing stage

Table 22.

RAM mapping for processing stage (continued)

Addr Descr.

Default Block Addr Descr.

0x088 #10 b1 0x000000

0x089 #10 b2 0x000000

0x08A #10 a2 0x000000

0x08B #10 a1 0x000000

0x08C #11 b0 0x400000

0x08D #11 b1 0x000000

0x08E #11 b2 0x000000

0x08F #11 a2 0x000000

0x090 #11 a1 0x000000

0x091 #12 b0 0x400000

0x092 #12 b1 0x000000

0x093 #12 b2 0x000000

0x094 #12 a2 0x000000

0x095 #12 a1 0x000000

0x096 #0 b0 0x400000

0x097 #0 b1

0x098 #0 b2

0x099 #0 a2

0x09A #0 a1

0x09B #1 b0

0x09C #1 b1

0x09D #1 b2

0x09E #1 a2

0x09F #1 a1

0x0A0 #2 b0

0x0A1 #2 b1

0x0A2 #2 b2

0x0A3 #2 a2

0x0A4 #2 a1

0x0A5 #3 b0

0x0A6 #3 b1

0x0A7 #3 b2

0x0A8 #3 a2

0x0A9 #3 a1

0x0AA #3 b0

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

(Ch1-biquad)

Ch2-biquad

0x0AB #4 b1

0x0AC #4 b2

0x0AD #4 a2

0x0AE #4 a1

0x0AF #5 b0

0x0B0 #5 b1

0x0B1 #5 b2

0x0B2 #5 a2

0x0B3 #5 a1

0x0B4 #6 b0

0x0B5 #6 b1

0x0B6 #6 b2

0x0B7 #6 a2

0x0B8 #6 a1

0x0B9 #7 b0

0x0BA #7 b1

0x0BB #7 b2

0x0BC #7 a2

0x0BD #7 a1

0x0BE #8 b0

0x0BF #8 b1

0x0C0 #8 b2

0x0C1 #8 a2

0x0C2 #8 a1

0x0C3 #9 b0

0x0C4 #9 b1

0x0C5 #9 b2

0x0C6 #9 a2

0x0C7 #9 a1

0x0C8 #10 b0

0x0C9 #10 b1

0x0CA #10 b2

0x0CB #10 a2

0x0CC #10 a1

0x0CD #11 b0

Default Block

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

(Ch2-biquad)

Doc ID 15351 Rev 3 49/157

Digital processing stage STA321

Table 22.

RAM mapping for processing stage (continued)

Addr Descr.

Default Block Addr Descr.

0x0CE #11 b1 0x000000

0x0CF #11 b2 0x000000

0x0D0 #11 a2 0x000000

0x0D1 #11 a1 0x000000

0x0D2 #12 b0 0x400000

0x0D3 #12 b1 0x000000

0x0D4 #12 b2 0x000000

0x0D5 #12 a2 0x000000

0x0D6 #12 a1 0x000000

0x0D7 #0 b0

0x0D8 #0 b1

0x0D9 #0 b2

0x400000

0x000000

0x0DA #0 a2

0x0DB #0 a1

0x0DC #1 b0

0x000000

0x400000

0x0DD #1 b1

0x0DE #1 b2

0x0DF #1 a2

0x0E0 #1 a1

0x0E1 #2 b0

0x0E2 #2 b1

0x0E3 #2 b2

0x0E4 #2 a2

0x0E5 #2 a1

0x0E6 #3 b0

0x0E7 #3 b1

0x0E8 #3 b2

0x0E9 #3 a2

0x0EA #3 a1

0x0EB #3 b0

0x0EC #4 b1

0x0ED #4 b2

0x0EE #4 a2

0x0EF #4 a1

0x0F0 #5 b0

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

(Ch2-biquad)

Ch3-biquad

0x0F1 #5 b1

0x0F2 #5 b2

0x0F3 #5 a2

0x0F4 #5 a1

0x0F5 #6 b0

0x0F6 #6 b1

0x0F7 #6 b2

0x0F8 #6 a2

0x0F9 #6 a1

0x0FA #7 b0

0x0FB #7 b1

0x0FC #7 b2

0x0FD #7 a2

0x0FE #7 a1

0x0FF #8 b0

0x100 #8 b1

0x101 #8 b2

0x102 #8 a2

0x103 #8 a1

0x104 #9 b0

0x105 #9 b1

0x106 #9 b2

0x107 #9 a2

0x108 #9 a1

0x109 #10 b0

0x10A #10 b1

0x10B #10 b2

0x10C #10 a2

0x10D #10 a1

0x10E #11 b0

0x10F #11 b1

0x110 #11 b2

0x111 #11 a2

0x112 #11 a1

0x113 #12 b0

Default Block

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

0x000000

0x400000

(Ch3-biquad)

50/157 Doc ID 15351 Rev 3

STA321 Digital processing stage

Table 22.

RAM mapping for processing stage (continued)

Addr Descr.

Default Block Addr Descr.

0x114 #12 b1 0x000000

0x115 #12 b2 0x000000

0x116 #12 a2 0x000000

0x117 #12 a1

0x118 ch0i

0x119 ch1i

0x11A ch2i

0x000000

0x7FFFFF

0x000000

(Ch3-biquad)

Post mix: ch0

0x11B ch3i

0x11C ch0i

0x11D ch1i

0x11E ch2i

0x11F ch3i

0x000000

0x7FFFFF

Post mix: ch1

0x000000

0x120 ch0i

0x121 ch1i

0x122 ch2i

0x123 ch3i

0x124 ch0i

0x125 ch1i

0x126 ch2i

0x127 ch3i

0x128 delay

Default Block

0x000000

0x7FFFFF

Post mix: ch2

0x000000

Post mix: ch3

0x7FFFFF

0x000000 Delay

Doc ID 15351 Rev 3 51/157

FFX

7 FFX

STA321

Figure 29.

FFX processing schematic d in

96 kHz

24 bits

16x oversampling stage

1536 kHz

24 bits dw up

Intersector up dw up

3 rd , 4 th , 5 th -order noise shaper dw pwm a

PWM generator pwm b

384/768 kHz

8/7 bits

384/768 kHz

1 bits

The FFX modulator is a digital low-distortion low-noise PCM-to-PWM converter, based on a pseudo-natural sampling technique, which converts the 4 by 24-bit digital inputs into differential pulse-width modulated outputs at a frequency of either 384 or 768 kHz (selected

by register FFXCFG2 , bit PWM_FREQ) and with a time resolution of 98.304 MHz. This

gives a dynamic range that is approaching 100 dB.

The signal is compared with two different carrier signals (rising and falling sawtooth waveforms at the PWM frequency), to get a double edge modulation and to have the possibility to drive a differential (full bridge) power stage.

The order of the noise shaper can be modified by the user, via register bit

FFXCFG2

.NS_ORD, depending on the acceptable amount of noise out of the audio band, that is, noise above 20 kHz. The higher the noise shaper order, the better is the SNR but the higher is the out of band noise.

The PWM generator block converts the amplitude quantization into time quantization to generate a PWM signal.

It is possible to use each of the two intersections with up-carrier and down-carrier to force a rising or a falling edge on each of the two PWM outputs (A and B). This flexibility is achieved through programming registers PWMOnCFG1-2 (where n is the number, 1 to 4, of the output) beginning

on page 91 .

PWM output A can be modulated in one of, or a hybrid of, two basic ways via bits PM_nA: z with the wave starting from level 0 at the beginning of the period, and rising to level 1 when the audio signal intersects the down-carrier z with the wave starting from level 1 at the beginning of the period, and falling to level 0 when the audio signal intersects the up-carrier;

52/157 Doc ID 15351 Rev 3

STA321 FFX

PWM output B can be similarly modulated via bits PM_nB: z with the wave starting from level 1 at the beginning of the period, and falling to level 0 when the audio signal intersects the down-carrier; z with the wave starting from level 0 at the beginning of the period, and rising to level 1 when the audio signal intersects the up-carrier;

The hybrid mode is the toggling between the two methods of modulation for each PWM period.

Figure 30.

PWM modes for outputs A and B up dn up dn

PWM mode for output A

00: dn -> rising

01: up -> falling

10: hybrid 1

11: hybrid 2

PWM mode for output B

00: dn -> falling

01: up -> rising

10: hybrid 1

11: hybrid 2

The various single output modulation schemes can be combined together on the two outputs to get the desired differential modulation schemes.

Doc ID 15351 Rev 3 53/157

FFX STA321

In particular, for the traditional schemes (binary, phase shift), and the new one (new phase shift modulation) the mode bits must be set according to

Table 23 below.

Table 23.

Modulation type with register programming

Register bit

PWMOnCFG1.PM_nA

Register bit

PWMOnCFG2.PM_nB

Resulting modulation

00 binary phase shift new phase shift

Figure 31.

Modulation waveforms corresponding to Table 23

PWM mode

A: 01

B: 01

A: 10

B: 10

A: 00

B: 01

Binary

A - B

Phase shift

New phase

shift

A-B

54/157 Doc ID 15351 Rev 3

STA321

7.3

FFX

PWM shift feature

In new phase shift modulation it is possible to shift one output with respect to the other one.

This can reduce the noise generated by the simultaneous switching of two or more outputs.

The shift is performed through by programming bits PS_nA and PS_nB in registers

PWMOnCFG1-2 (where n is the number, 1 to 4, of the output) beginning on page 91

Figure 32.

New phase shift modulation with shift feature dn up up’

without shift

AB

A

B with shift

A

B

AB

Doc ID 15351 Rev 3 55/157

FFX STA321

The ternary mode feature is also available. It is activated by bits TERNARY_n in registers

PWMOnCFG0 beginning

on page 91 (where n is the number, 1 to 4, of the output).

This feature overrides the PWM mode bits settings PM_nA and PM_nB.

Figure 33.

Ternary modulation

PWM mode

A: 10

TERNARY_n

B: 10

= 0 A: 00

B: 01

A: 10

TERNARY_n

B: 10

= 1 A: 00

B: 01

Phase shift

New phase shift

Ternary

7.5 Minimum pulse limitation

z z

The FFX modulator has a minimum pulse limitation feature which has a double purpose: to limit the maximum/minimum duty cycle when the audio signal is near to full scale; to have the commutations on the same channel outputs A and B separated by a minimum pulse distance.

The first feature is always enabled.

The second feature is enabled with register bit PWMOnCFG0.MP_ZERO_n, where n is the output 1 to 4. It is possible to prevent the commutations on outputs A and B to happen exactly at the same time using bit AZPLS_n. The minimum pulse size is determined by the number of system clock (98.304 MHz) periods programmed in bits MIN_PLS_n[3:0].

56/157 Doc ID 15351 Rev 3

STA321 FFX

The FFX modulator can be used for driving a headphone load with the common terminal available, together with left and right terminals.

In this case it is possible to drive the common terminal with a 50% fixed duty cycle square wave coming from output B of the modulator, by setting bit HALFB_n to 1, and the left and right terminals from the output A of two different channels. For the three outputs used in this way bits PM_nA and PM_nB can be 00 or 01.

Figure 34.

Modulation for headphones

Left

Common

Right

Output 0A

Output 0B

Output 1A

Left

Common

Right

Doc ID 15351 Rev 3 57/157

FFX STA321

In order to avoid pop noise the bypass capacitor, situated between the filtered amplifier output and the load in single-ended applications, needs to be pre-charged to half of the power supply voltage. This is usually done by connecting a resistive partition to the output and then disconnecting it at the end of the charging phase (see the analog pop free description in section 9).

In the STA321 the FFX digital pop-free feature allows the digital pre-charging of the bypass capacitor using the amplifier instead of a resistive partition. This active pre-charge is also faster than the resistive partition method. The digital pop-free function can be independently set on both power stages, that is, the CMOS bridge stage using bit CB_PFDIG and the embedded amplifier stage using bit EA_PFDIG in register

FFXCFG2 on page 83

Registers CB_PFRAMP1-6 beginning

on page 97

and EA_PFRAMP1-6 beginning on page

99 control the charging function. The register usage is given in the following description.

The capacitor is charged from zero to half the supply voltage with the PWM signal. By applying a suitable ramp to the input of the modulator the PWM signal begins from near 0% duty cycle to 50% duty cycle.

The method is based on a slow ramp signal (from ground to V

/ 2), implemented using both pulse density modulation (PDM) and pulse width modulation (PWM). At the beginning of the ramp PDM is used starting from an initial value set by bits CBRMPINI and EARMPINI, and then switching to PWM when reaching a threshold value set by bits CBRMPTH and

EARMPTH.

The total ramp time can be modified via bits EATIM_RMP and CBTIM_RMP.

Figure 35.

Digital pop-free ramp implementation

0000 …000

Ramp value RAMP_THOLD

RAMP_INIT

1000 …000

Output 0 PDM PWM

The PDM is realized with a noise shaper circuit, where the sampling time (Td) of the noise shaper is equal to the minimum pulse size set by bits CBRMP_MP and EARMP_MP.

58/157 Doc ID 15351 Rev 3

STA321 FFX

Pin PWM00 is an additional output with a maximum driving capability of 2 mA to control an external bridge or external operational amplifier.

By default, PWM00 is tied to logical 0. When register bit CKOCFG[0] is set to 1 then any

FFX PWM channel output can be mapped to it.

When the CMOS bridge is in standby the output PWM00 is, by default, turned off. However, it is possible to have the FFX signal PWM3A as the PWM00 output by using bit 3 of register

FFXCFG0 on page 82

, and this whatever the status of power-down or the 3-state signals of both bridges, even if they are different from the normal operating mode where the output is 0 when in power-down or 3-state mode.

Doc ID 15351 Rev 3 59/157

CMOS power stage

8 CMOS power stage

STA321

The CMOS half-bridge circuit of Figure 36 is a single channel analog output power stage.

There are three such output stages in the STA321, one for each of the outputs OUT1-3.

The switching mode is regulated by the logic circuit which ensures that the MOSFETs are switched in such a way as to avoid (or minimize) conditions where both the PMOS and the

NMOS are conducting at the same time.

The input is a 1.8-V to 3.3-V level shifter followed by some combinational logic.

Figure 36.

CMOS half bridge block diagram

VDD VCC33 VCCx

FaultN

FFX-ch N

Powerdown

Tristate

PopFree

Level shifter

Enable logic

GND33

Driver P

Fault

Logic

Driver N

Vcc33

Pop-free

Power

OutN

GND GND33 GNDx

Table 24.

CMOS bridge signal descriptions

Pin Name Direction

FFX-ch

Powerdown

Tristate

PopFree

Fault

Out

VCC33/GND33

VDD/GND

VCCx/GNDx

Out

Supply

Description

Digital audio signal coming from FFX block

Powerdown signal coming from the FFX block

3-state signal from the FFX block

Pop-free signal from the FFX block

Short-circuit fault output feedback signal to digital core (active low)

Channel half-bridge analog output

Pre-driver analog supply

Digital core supply generated by internal regulator

Half-bridge power supply

60/157 Doc ID 15351 Rev 3

STA321 CMOS power stage

The CMOS bridge power rating can be calculated using the following formulas:

P (<1%) = (R

/ 2) * (M * VCC / 2 / (R

+ 2 * R

))

for BTL

P (<1%) = (R

/ 2) * (M * VCC / 2 / (R

+ R

))

for single ended

P (10%) = 1.28 * P(<1%) where R

is composed of the MOST R

DSON

and the board and connector parasitic resistances (including power supplies and coils) and M is the modulation index obtained from

M = 1 - 2 * (MIN_PLS_n + 1) / f clk_ffx

S where MIN_PLS_n is the value in register PWMOnCFG0 for channel n, f clk_ffx frequency of the FFX clock and

S register bit

FFXCFG2

.PWM_FREQ).

is the

is the PWM clock period ( 384 kHz or 768 kHz selected by

For the CMOS bridge, MIN_PLS_n can be set to 0; this gives M = 0.9922.

Table 25.

Power output (at 1% THD) in headphone mode

Load, R

in Ω Power, P in mW (for 3.3-V supply)

The analog pop_free function is available in the CMOS bridge circuit by setting the

appropriate bridge start-up as per Table 26 . The CMOS bridge enable and pop-free signals

are generated from the three signals Powerdown, Tristate and PopFree provided by the digital core and controlled/configured through register bits

FFXCFG1 .CB_STBY,

FFXCFG1

.CB_TRISTn and PFEFAULT .PFEn for the three outputs, n = 1 to 3.

Figure 37.

Analog pop-free schematic

VCCx

OutN

GNDx

PFE & not(Tristate) & Powerdown

Doc ID 15351 Rev 3 61/157

CMOS power stage STA321

Table 26.

Logic circuit at bridge input

Powerdown Tristate PopFree

Pop-free resistors

Disconnected

Connected

Disconnected

Bridge status

3-state

At the appropriate time the two pop-free resistors allow the bypass capacitor to be charged to V

CCx

/ 2. The STA321 generates automatically the bridge start-up and switch-off

sequence to provide the correct charging. The time TT in Figure 38 below is set using

registers CBTTF0-1 and CBTTP0-1. TT must be chosen for the specific application depending on the decoupling capacitor, load and power supply.

After powerdown is applied again the decoupling capacitor discharges slowly due to capacitor leakage.

The analog pop-free implementation cannot be used with the digital pfStart implementation

Both analog and digital pop-free features must be disabled if binary headphone modulation is used.

Figure 38.

Analog pop-free start-up and switch-off sequence

Powerdown

PFE

Tristate

Vcc / 2

V(capacitor)

TT TT

The CMOS bridge circuit includes over-current protection. The FAULT signal indicates to the output the status of the over-current condition due to a short circuit. The over-current thresholds detected by the CMOS bridge are fixed at 1.8 A.

62/157 Doc ID 15351 Rev 3

STA321

9 Fault detection and recovery

Fault detection and recovery

When Fault is reported on pin EAFTN and bit EA_TSFT_ON of register

FFXCFG2 on page 83

is active, then pin EATSN is reset to 0 and the embedded bridge outputs are put in the high-impedance state. When the fault signal disappears (that is, goes to 1) the

embedded bridge is kept in 3-state for a time defined in register EATTF0-1 on page 86

, after which time the outputs recover.

When Fault is reported to the digital core and CB_TSFT_ON of register FFXCFG2 on page 83

is active then the tristate is activated thus putting the STA321 OUTn outputs in the high-impedance state. When the fault signal disappears, the CMOS bridge is kept in 3-state status for a time defined in register CBTTF0-1

on page 88 , after which time the outputs

recover.

Doc ID 15351 Rev 3 63/157

ADC

10 ADC

STA321

10.1 Description

The STA321 analog input is provided through a low-power, low-voltage complete low-cost analog-to-digital converter front end designed for stereo audio applications. It includes programmable gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit, a third order MASH2-1 delta-sigma modulator, a digital decimating filter and a 1st-order

DC-removal filter.

The ADC works with either a microphone input or a line input, selected using bit

ADC_INSEL in register ADCCFG0 on page 133

A programmable gain amplifier (PGA) is available in microphone-in mode giving the possibility to amplify the signal from 0 to 42 dB in steps of 6 dB using register bit

ADCCFG0

.ADC_PGA.

The ADC specifications are given in Table 6 on page 14

Figure 39.

ADC front-end block diagram

PGA

INL 1

INL 2

ADC left

16 bits

ADCCFG1[7:6] ADCINSEL[4]

INR 2

INR 1

PGA

ADC right

16 bits

64/157 Doc ID 15351 Rev 3

STA321

Figure 40.

Typical connections for power supplies and inputs

ADC

This is an example of the register setup for the ADC inputs. It is assumed that every peripheral is already configured and working correctly.

There are other configuration examples to help you get started please refer to other chapters and also to

Chapter 14: Register description on page 77

in order to get all the necessary and complementary details.

Table 27

shows the register settings for selecting INL2 and INR2 as input source for SRC and SAI_out1 and using the PGA with a 12-dB gain.

Table 27.

Example register settings for ADC

Register Value

ADCCFG1

ADCCFG0

P2SDATA

0x40

0x52

0x40

Description

Selecting INL2 and INR2 as sources

PGA Gain = +12 dB, PGA enabled, ADC clock on

ADC Data routed also to the SAI_out

Doc ID 15351 Rev 3 65/157

Serial audio interface

11 Serial audio interface

STA321

The data on pins SDATAI, SDATAO, LRCLKI and LRCLKO are always synchronous with the bit clock. The data on these pins changes with the BICLK active (or clocking) edge.

The BICLK strobe edge latches the data SDATAI, SDATAO, LRCLKI, LRCLKO; thus this data should be stable near the BICLK strobe edges. The slave device uses the strobe edges to latch the serial data internally.

The active and strobe edges can be selected to be the rising edge or the falling edge by appropriately programming register bits

SAI_IN1_CFG0 [7],

SAI_OUT_CFG0

[7] and

SAI_IN2_CFG0 [7].

The serial-to-parallel interface and the parallel-to-serial interface can have different

sampling rates. Figure 41 shows a typical setup.

Figure 41.

SAI typical sampling rates

SAI_in

Fs = 8 - 192 kHz

Sample rate converter

Fs = CLK / 1024

96 kHz

Processing

Fs = CLK / 1024

SAI_out

96 kHz

Fs = CLK / 1024

Fs = CLK / 2048

96 kHz or

48 kHz

CLK 98 MHz

PLL

66/157

In this mode BICLKI/BICLKO and LRCLKI/LRCLKO are configured as outputs and are generated by the core.

Figure 42.

Timing diagram for master mode

Biclki/

Biclko

BICLKO t

LRCLKI

LRCLKO t

DDA

SDATAO

SDATAI t

DST t

DHT

Doc ID 15351 Rev 3

STA321 Serial audio interface

Table 28.

Timing parameters for master mode

Symbol Parameter t

DL t

DDA t

DST t

DHT

LRCLKI/LRCLKO propagation delay from BICLK active edge

SDATAI propagation delay from BICLKI/O active edge

SDATAO setup time to BICLKI/O strobing edge

SDATAO hold time from BICLKI/O strobing edge

Min

10 -

Typ Max Unit

15 ns ns ns ns

In this mode BICLKI/O and LRCLKI/O are configured as inputs and supplied by the external peripheral.

Figure 43.

Timing diagram for slave mode t

BCH t

BCL

BICLKI

BICLKO t

BCy

LRCLKI

LRCLKO t

DS t

LRH t

LRSU

SDATAO t

SDATAI t

Table 29.

Timing parameters for slave mode

Symbol Parameter t

BCy t

BCH t

BCL t

LRSU t

LRH t

DS t

DH t

BICLK cycle time

BICLK pulse width high

BICLK pulse width low

LRCLKI/LRCLKO setup time to BICLK strobing edge

LRCLKI/LRCLKO hold time to BICLK strobing edge

SDATAO setup time to BICLK strobing edge

SDATAO hold time to BICLK strobing edge

SDATAI propagation delay from BICLK active edge

Min

Typ Max Unit

10 ns ns ns ns ns ns ns ns

Doc ID 15351 Rev 3 67/157

Serial audio interface STA321

Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market.

Data length can be customized for 8, 16, 24 or 32 bits.

Figure 44.

Right justified serial format

LRCLKI

LRCLKO

BICLKI

BICLKO

SDATAO

SDATAI

Figure 45.

Left justified serial format

LRCLKI

LRCLKO

BICLKI

BICLKO

SDATAO

SDATAI

68/157 Doc ID 15351 Rev 3

STA321

11.3.3 DSP

Figure 46.

DSP serial format

LRCLKI

LRCLKO

BICLKI

BICLKO

SDATAO

SDATAI

Left

11.3.4 I

Figure 47.

S serial format

LRCLKI

LRCLKO

BICLKI

BICLKO

SDATAO

SDATAI

3 n

-1 n

Right

Serial audio interface

1 2 3 n

-1 n z z

MSB first

16-bit data.

Figure 48.

PCM (non-delayed) serial format

Any width

LRCLKI

LRCLK

LRCLKO

BICLKI

BICLKO

SDATAO

SDATAI

SDATAO/

SDATAI

1 2 3 n

-1 n

Doc ID 15351 Rev 3 69/157

Serial audio interface z z

MSB first

16-bit data.

Figure 49.

PCM (delayed) serial format

LRCLKI

LRclki/

LRCLKO

BICLKI

BICLKO

BIclki/

BIclko

SDATAO/

SDATAI

1 2 3 n

-1 n

STA321

70/157 Doc ID 15351 Rev 3

STA321 Serial audio interface

STA321 has an invalid input detection feature that can detect an invalid serial interface bit clock or frame clock and then mute the processing channels to avoid any speaker or headphone damage and, moreover, to avoid loud audible transients which may be discomforting to the listener. The control is active only for the SAI input. The configuration programmed in bits 0, 1 and 2 of register

FFXCFG0 on page 82

is applicable to both SAI1 and SAI2 whilst the checks are independent for each interface. The mute on the processing channel is asserted depending on the input interface mapping.

Figure 50

shows the invalid detection schematic. Here, two different checks are available.

The first one is enabled by register bit FFXCFG0 .BAD_CKS_M and evaluates the ratio of

BICLK and LRCLK. The resulting number must be the same as that written in bits

S2Pn_BOS (for example, 32 * f

or 64 * f

) in registers

SAI_IN1_CFG1 on page 123

and

SAI_IN2_CFG1 , otherwise the channels are muted.

The second check is enabled by register bit FFXCFG0 .MIS_BICK_M and is related to the

presence of BICLK. Basically, a 8-bit watchdog counter decrements, starting from 0xFF, with each edge of clk_proc. The counter is reset to 0xFF at each BICLK edge; so, if the watchdog counter ever reaches 0x00, a missing bit clock error is signalled and the mute command is issued.

Figure 50.

Invalid input detection schematic

BICLKI1

LRCLKI1

LRCLKI2

BICLKI2 clk_proc

Is alive?

MIS_BICK_M

Ratio calculator

BAD_CKS_M

S2P1_BOS

S2P2_BOS

BAD_CKS_M

MUTE0

MUTE1

MUTE0

MUTE1

MUTE2

MUTE3

MUTE2

Is alive?

MIS_BICK_M clk_proc

MUTE3

01 mute ch0

SRC1_INSEL

01 mute ch1

01 mute ch2

SRC2_INSEL

01 mute ch3

Doc ID 15351 Rev 3 71/157

Headphone detection STA321

The headphone detector circuit, shown in

Figure 51

, is made with two schmitt-trigger comparators (with different thresholds) which sense the value of the HPDECT input voltage

and modifies the HP_DET1 or the HP_DET2 level as given in Table 30 and Table 31

below.

The comparators are enabled or disabled with bits E_HP1 and E_HP2 in register HPDET2 on page 138

Table 30.

Headphone 1 detector

E_HP1

(register HPDET2)

HP-jack status HP_DET voltage HP_DET1

Status register bit

HPDST.HP_DET_FILT

Unplugged

Plugged

Low

High

1 -

Table 31.

Headphone 2 detector

E_HP2

(register HPDET2)

HP-jack status HP_DET voltage HP_DET2

Status register bit

HPDST.HP_DET_FILT

Unplugged

Plugged

Low

High

The comparator output status is provided via bits 1 and 0 of register HPDET2 on page 138

One of the comparator outputs is then selected with register bit

HPDET1 .HPD_SEL, and

that signal is passed through a digital debouncing filter and supplied to the FFX modulator.

The PWM outputs are then modified depending on the settings of register bits

HPDST .HP_DET_FILT and

HPDET1 .HPD_ACT_MODE.

72/157 Doc ID 15351 Rev 3

STA321 Headphone detection

Two applications circuits are given here, one for the binary single-ended application and one for the binary headphone application.

Figure 51.

Headphone detection circuit for single-ended configuration

VCC33

100 k

TUD_EN

VCC33

HP_DET1

HP_DET

5 k

HP_DET2

I 2 C

Filter

HP_DET_FILT

CMOS bridge

FFX modulator

EAPWM out

1 k

Figure 52.

Headphone detection circuit for binary HP configuration

VCC33

100 k

TUD_EN

VCC33

HP_DET1

HP_DET

5 k

HP_DET2

I 2 C

Filter hp_det_filt

CMOS bridge

FFX modulator

EAPWM out

1 k

Doc ID 15351 Rev 3 73/157

Headphone detection STA321

Note:

This is an example of the register setup for headphones detection. It is assumed that every peripheral is already configured and working correctly.

There are other configuration examples to help you get started please refer to other chapters and also to

Chapter 14: Register description on page 77

in order to get all the necessary and complementary details.

Table 32 and Table 33 below give a possible setup for the headphones detection

configurations shown in Figure 51 and Figure 52

, respectively.

Table 32.

Headphone detection configuration sequence for binary SE

Register Value Description

MISC on page 135

PLLB on page 136

0x21

0x00

User FFX and CMOS bridge configuration

HPDET2 on page 138

0x80

Enable core clock

Use PLL clock

HPDET1 on page 137

0x57

Disable the HP_DET pull-up

Use HP1 for hpdet filter; polarity = high; action = mute; mod = binary SE; average time 170 ms.

HPDET2 on page 138

FFXCFG1 on page 81

0x00 Remove the tristate from the bridges

Table 33.

Headphone detection configuration sequence for binary headphone

Register Value Description

MISC on page 135

PLLB on page 136

0x21

0x00

User FFX and CMOS bridge configuration

HPDET2 on page 138

0x80

Enable core clock

Use PLL clock

HPDET1 on page 137

0x5F

Disable the HP_DET pull-up

Use HP1 for hpdet filter; polarity = high; action = mute; mod = binary HP; average time 170 ms.

HPDET2 on page 138

FFXCFG1 on page 81

0x00 Remove the tristate from the bridges

The pullup on HPDET pad must always be disabled before using the HPDET function.

Comparator 1 and comparator 2 cannot be enabled simultaneously.

74/157 Doc ID 15351 Rev 3

STA321

13 I

C interface

C interface

13.1.1 Data transition and change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.

START is identified by a high to low transition of the SDA bus while the clock signal, SCL, is stable in the high state. A START condition must precede any command for data transfer.

STOP is identified by a low to high transition on the SDA bus while the clock signal, SCL, is stable in the high state. A STOP condition terminates communication between STA321 and the bus master.

During the data input the STA321 samples the SDA signal on the rising edge of clock SCL.

For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

To start communication between the master and the STA321, the master initiates with a start condition. Following this, the master sends 8 bits (MSB first) on the SDA line which corresponds to the device select address and read or write mode.

The 7 MSBs are the device address identifiers, corresponding to the I

C bus definition. In the STA321 the I

C interface has the device address 0x30.

After a START condition the STA321 identifies the device address and if a match is found, acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.

Following the START condition the master sends a device select code with the RW bit set to 0. After the STA321 acknowledge, the master sends the byte of internal address. On receiving the internal byte address the STA321 responds with acknowledge.

Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the

STA321. The master then terminates the transfer by generating a STOP condition.

Doc ID 15351 Rev 3 75/157

C interface STA321

Multi-byte write

The multi-byte write mode starts from any internal address. The master generates a STOP condition to terminate the transfer.

Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA321 acknowledges and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Current address multi-byte read

The multi-byte read mode start from any internal address. Data bytes are read from sequential addresses within the STA321. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer.

Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA321 acknowledges and then the master writes the internal address byte. After receiving, the internal byte address the STA321 again responds with an acknowledge. The master then initiates another START condition and sends the device select code with the

RW bit set to 1. The STA321 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Random address multi-byte read

The multi-byte read modes start from any internal address. Data bytes are read from sequential addresses within the STA321. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer.

Figure 53.

C write operations

Figure 54.

C read operations

76/157 Doc ID 15351 Rev 3

STA321 Register description

Table 34.

Register summary

EA_STBY

CB_STBY FFXCFG1

FFXCFG0

0x00

0x01 MUTE3 MUTE2

FFXCFG2 0x02

RESET

_NOISH

PWM_FREQ

PWMMAP1

PWMMAP2

PWMMAP3

0x03

0x04

0x05

EATTF0

EATTF1

0x06

0x07

EATTP0 0x08

EATTP1 0x09

CBTTF0 0x0A

CBTTF1 0x0B

CBTTP0 0x0C

CBTTP1 0x0D

FFXST 0x0E

POWST 0x0F

POWST1 0x10

PWMO1CFG0 0x11

PWMO1CFG1 0x12

PWMO1CFG2 0x13

PWMO2CFG0 0x14

PWMO2CFG1 0x15

PWMO2CFG2 0x16

PWMO3CFG0 0x17

PWMO3CFG1

PWMO3CFG2

0x18

0x19

PWMO4CFG0 0x1A

PWMO4CFG1 0x1B

PWMO4CFG2

CB_PFRAMP1

0x1C

0x20

CB_PFRAMP2

CB_PFRAMP3

CB_PFRAMP4

CB_PFRAMP5

0x21

0x22

0x23

0x24

CB_PFRAMP6

EA_PFRAMP1

EA_PFRAMP2

0x25

0x26

0x27

CB3_MAP[0]

EA1B_MAP[1:0]

EA_MPWM

Reserved

AZPLS_1

PM_1A[1:0]

PM_1B[1:0]

AZPLS_2

PM_2A[1:0]

PM_2B[1:0]

AZPLS_3

PM_3A[1:0]

PM_3B[1:0]

AZPLS_4

CB1_MAP[2:0]

CB_MPWM

CB_PD

PM_4A[1:0]

PM_4B[1:0]

EA_TRIST

PWM00_MAP[2:0]

Reserved

TERNARY_1

TERNARY_2

TERNARY_3

TERNARY_4

MUTE1

CBTIM_RMP[3:0]

MUTE0

NS_ORD[1:0]

EA2A_MAP[2:0]

EARMP_ST[1:0]

HALFB_1

HALFB_2

HALFB_3

HALFB_4

CBRMP_MP[5:0]

EARMP_MP[5:0]

FFX_ULCK_PLL

EA_TSFT_ON CB_TSFT_ON

EATTF[7:0]

EATTP[15:8]

EATTP[7:0]

CBTTF[15:8]

CBTTF[7:0]

CBTTP[15:8]

CBTTP[7:0]

CB_FT[2:0]

MP_ZERO_1

MP_ZERO_2

MP_ZERO_3

MP_ZERO_4

PWM00_3A

CB2_MAP[2:0]

CBRMP_ST[1:0]

EA_TW

CBRMPINI[15:8]

CBRMPINI[7:0]

CBRMPTH[15:8]

CBRMPTH[7:0]

EARMPINI[15:8]

CB_TRIST2

BAD_IN_M

EA1A_MAP[2:0]

EA_PD

PS_1A[5:0]

PS_1B[5:0]

PS_2A[5:0]

PS_2B[5:0]

PS_3A[5:0]

PS_3B[5:0]

PS_4A[5:0]

PS_4B[5:0]

CB_TRIST1

CB_TRIST0

BAD_CKS_M MIS_BICK_M

EA_PFDIG

CB3_MAP[2:1]

EA2B_MAP[2:0]

CB_PFDIG

EA1B_MAP[2]

EABINSS_AC CBBINSS_AC

CB_TS[2:0]

MIN_PLS_1[3:0]

MIN_PLS_2[3:0]

MIN_PLS_3[3:0]

MIN_PLS_4[3:0]

Reserved

EA_FT

Reserved

EA_TS

Doc ID 15351 Rev 3 77/157

Register description STA321

0x73

0x74

0x75

0x76

0x6F

0x70

0x71

0x72

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x57

0x58

0x59

0x5A

0x53

0x54

0x55

0x56

0x28

0x29

0x2A

0x2B

0x30

0x31

0x51

0x52

Table 34.

Register summary (continued)

I2CA1_MID

I2CA1_BOT

I2CA2_TOP

I2CA2_MID

I2CA2_BOT

PROCCTRL

START_ADD2

START_ADD

ROM_REMAP

BYP_EN_CH0

EFFS_EN_CH0

BYP_EN_CH1

EFFS_EN_CH1

BYP_EN_CH2

EFFS_EN_CH2

BYP_EN_CH3

EA_PFRAMP3

EA_PFRAMP4

EA_PFRAMP5

EA_PFRAMP6

SRC1STATE

SRC2STATE

I2CB0_TOP

I2CB0_MID

I2CB0_BOT

I2CB1_TOP

I2CB1_MID

I2CB1_BOT

I2CB2_TOP

I2CB2_MID

I2CB2_BOT

I2CA1_TOP

EFFS_EN_CH3

BASS_SEL0_R

BASS_SEL1_R

BASS_SEL2_R

BASS_SEL3_R

TREB_SEL0_R

TREB_SEL1_R

TREB_SEL2_R

SRC1_BYP[1:0]

Reserved ENAB_PRE3

Reserved

EATIM_RMP[3:0]

SRC_1_LOCK

Reserved

ENAB_PRE2

Reserved

ENAB_PRE1

Reserved

BASS_EN0

BASS_EN1

BASS_EN2

BASS_EN3

TREB_EN0

TREB_EN1

TREB_EN2

EARMPINI[7:0]

EARMPTH[15:8]

EARMPTH[7:0]

I2CB0[23:16]

I2CB0[15:8]

I2CB0[7:0]

I2CB1[23:16]

I2CB1[15:8]

I2CB1[7:0]

I2CB2[23:16]

I2CB2[15:8]

I2CB2[7:0]

I2CA1[23:16]

I2CA1[15:8]

I2CA1[7:0]

I2CA2[23:16]

I2CA2[15:8]

I2CA2[7:0]

I2CSTART_A7_A0

ENAB_PRE0

Reserved

SRC1_FISFO[4:0]

Reserved

BASS_SEL0

BASS_SEL1

BASS_SEL2

BASS_SEL3

TREB_SEL0

TREB_SEL1

TREB_SEL2

I2CSTART_A8

ENAB_POST ENAB_PRMIX ENAB_DELAY

EROM09

EROM19

EROM29

EROM39

EROM08

Reserved

EROM28

Reserved

78/157 Doc ID 15351 Rev 3

STA321 Register description

Table 34.

Register summary (continued)

TREB_SEL3

1 0

TREB_SEL3_R

SATCH0CFG1

SATCH0CFG2

SATCH0CFG3

SATCH1CFG1

SATCH1CFG2

SATCH1CFG3

SATCH2CFG1

SATCH2CFG2

SATCH2CFG3

SATCH3CFG1

SATCH3CFG2

SATCH3CFG3

VOLCFG

MVOL

VOLCH0

VOLCH1

VOLCH2

VOLCH3

SAI_IN1_CFG0

0xA3

0xA4

0xA5

0xB0 S2P1_B_STR S2P1_LR_L

S2P1_DLEN SAI_IN1_CFG1 0xB1

SAI_OUT_CFG0 0xB2 P2S_B_STR P2S_LR_L

SAI_OUT_CFG1 0xB3

SAI_IN2_CFG0 0xB4

P2S_DLEN

S2P2_B_STR S2P2_LR_L

S2P2_DLEN SAI_IN2_CFG1

AUIFSHARE

0xB5

0xB6

SRCINSEL

P2SDATA

0xB7

0xB8

SRC1_INSEL

Reserved P2S_HFS

PLLCFG0 0xC0 PLL_DPROG

PLL_FR

_CTRL

PLLCFG1

PLLCFG2

PLLCFG3

PLLPFE

PLLST

ADCCFG0

0x97

0x98

0x99

0x9A

0x9B

0xA0

0xA1

0xA2

0x93

0x94

0x95

0x96

0x7F

0x90

0x91

0x92

SAT_EQ

Reserved

SVOL_ON3 SVOL_ON2

TREB_EN3

SVOL_ON1

Reserved

SVOL_ON0

S2P1_MSB

S2P1_BOS

SDATAO_ACT P2S_MSB

P2S_BOS

Reserved S2P2_MSB

S2P2_BOS

Reserved

SRC2_INSEL

P2S1_DSEL

PLL_DDIS

0xC1

0xC2

0xC3 PLL_STRB

PLL

_STRBBYP

0xC4

PLL_BYP

_UNL

BICLK2PLL PLL_PWDN

0xC5 PLL_UNLOCK PLL_PWD_ST PLL_BYP_ST

0xC6 ADC_PGA

PLL

_NOPDDIV

ADC_INSEL

SAT_CH0[22:16]

SAT_CH0[15:8]

SAT_CH0[7:0]

SAT_CH1[22:16]

SAT_CH1[15:8]

SAT_CH1[7:0]

SAT_CH2[22:16]

SAT_CH2[15:8]

SAT_CH2[7:0]

SAT_CH3[22:16]

SAT_CH3[15:8]

SAT_CH3[7:0]

MVOL

CVOL0

CVOL1

CVOL2

CVOL3

S2P1_DFM

S2P1_MAP_L

P2S_DFM

P2S_MAP_L

S2P2_DFM

S2P2_MAP_L

MUTE_SRCU

PLL_FRAC[15:8]

PLL_FRAC[7:0]

PLL_NDIV

ADC_STBY

TIM_SVOL

S2P1_MAP_R

P2S_MAP_R

S2P2_MMD

S2P2_MAP_R

SHARE_BILR

Reserved

P2S2_DSEL

PLL_IDF

Reserved

ADC_BYPCAL CLK_ADC_ON

S2P1_MMD

P2S_MMD

Reserved

CKOCFG 0xC7 CLKOUT_DIS CLKOUT_SEL CLK_FFX_ON CLK_SRC_ON

CLK_PROC

_ON

EAPWM_DIS PWM00ACT

MISC 0xC8 OSC_DIS S2P_FS_RNG ADC_FS_RNG P2P_IN_ADC

CLKCORE

_ON

Doc ID 15351 Rev 3 79/157

Register description STA321

BISTRUN0

BISTRUN1

BISTST0

BISTST1

BISTST2

BISTST3

ROMSIGN0

ROMSIGN1

ROMSIGN2

DEBUG0

PADST0

PADST1

Table 34.

Register summary (continued)

PLLB

HPDET1

HPDET2

HPDST

STBY_MODES

ADCCFG1

PFEFAULT

0xC9

0xCA

0xCB

0xCC

PLL_BYP Reserved

HPD_SEL

E_HP2

HPD_DET

_FILT

HPD_POL

E_HP1

0xCD PAD_PULLDIS

0xCE ADC_ANA_SEL

0xCF Reserved

ADC_CLKSEL

Reserved

HPD_ACT_MODE

TUD_EN

Reserved

P2S1

_CLKSEL

HPD_HPMOD

Reserved

2 1

P2S2

_CLKSEL

HPD_TIM_F

E_HPDET1

CMP_EN_N

Reserved

E_HPDET2

DC_STBY

_EN_N

0xD0 SF1_BRUN SF2_BRUN

0xD1

0xD2

0xD3

0xD4

OS_BRUN

SF1_BEND

SS1_BFAIL

PR_BBAD

0xD5

CF_ROM

_BEND

0xD6

0xD7

0xD8

0xD9 DBGCKO_ON

0xF0 PAD_RSTN

0xF1 PAD_MUTE

DB_BRUN

SF1_BBAD

SS2_BEND

PR_BFAIL

Reserved

PAD_BICLKI

SS1_BRUN

SF1_BFAIL

SS2_BBAD

OS_BEND

PFE1

SS2_BRUN

SF2_BEND

SS2_BFAIL

OS_BBAD

PFE2

CF_BRUN

Reserved

PFE3

PR_BRUN

Reserved

SF2_BBAD

CF_BEND

OS_BFAIL

SF2_BFAIL

CF_BBAD

DB_BEND

PAD_SCL

PAD_LRCLKI

CF_ROMS[7:0]

CF_ROMS[15:8]

CF_ROMS[23:16]

DBGCKO_VAL

PAD_SDA

PAD_SDATAI

PAD_I2CDIS Reserved

PAD_BICLKO PAD_LRCLKO

RESET_EA

_FT

CF_ROM

_BRUN

SS1_BEND

CF_BFAIL

DB_BBAD

RESET_CB

_FT

Reserved

SS1_BBAD

PR_BEND

DB_BFAIL

PAD_STBY

Reserved

80/157 Doc ID 15351 Rev 3

STA321 Register description

FXCFG1

EA_STBY

CB_STBY

EA_TRIST

FFX_ULCK_PLL

3 2

CB_TRIST2

CB_TRIST1

Address:

Type:

Reset:

Description:

0x00

0xD0

[7] EA_STBY

0: the external bridge is active

1: the external bridge is in standby mode

[6] CB_STBY

0: the bridge is active

1: the bridge is in standby mode

[5] EA_TRIST

0: normal behaviour

1: the external bridge is put in 3-state mode

[4:3] FFX_ULCK_PLL: behavior of the FFX modulator in the event of the PLL losing lock:

00: do nothing

01: FFX hard mute (equivalent to using pin MUTE)

10: FFX standby

11: FFX hard mute and noise-shaper reset

[2] CB_TRIST2

0: the bridge is active

1: force CMOS bridge OUT3 to 3-state

[1] CB_TRIST1

0: the bridge is active

1: force CMOS bridge OUT2 to 3-state

[0] CB_TRIST0

0: normal behaviour

1: force CMOS bridge OUT1 to 3-state

CB_TRIST0

Doc ID 15351 Rev 3 81/157

Register description STA321

FFXCFG0

MUTE3

Address:

Type:

Reset:

Description:

MUTE2

0x01

0x07

MUTE1

MUTE0

PWM00_3A

BAD_IN_M

BAD_CKS_M

MIS_BICK_M

[7] MUTE3

0: normal behaviour

1: force the mute in the channel 3

[6] MUTE2

0: normal behaviour

1: force the mute in the channel 2

[5] MUTE1

0: normal behaviour

1: force the mute in the channel 1

[4] MUTE0

0: normal behaviour

1: force the mute in the channel 0

[3] PWM00_3A

0: output PWM00 is driven by FFX (default)

1: output PWM00 comes from FFX output PWM3A and is not sensitive to bridge power-down or

3-state states

[2] BAD_IN_M

Depending on the bit 0 and bit 1 settings

0: mute with a ramp

1: mute instantaneously

[1] BAD_CKS_M

0: FFX not muted

1: FFX muted if biclk and lrclk do not meet the specification

[0] MIS_BICK_M

0: FFX not muted

1: FFX will be muted if biclk is missing

82/157 Doc ID 15351 Rev 3

STA321 Register description

FFXCFG2

RESET_NOISH

PWM_FREQ

Address:

Type:

Reset:

Description:

0x02

0x2D

NS_ORD[1:0]

4 3

EA_TSFT_ON

CB_TSFT_ON

[7] RESET_NOISH

1: a reset is forced to the noise-shaper block

[6] PWM_FREQ

0: 4 f

(4*96 kHz = 384 kHz)

1: 8 fS (8*96 kHz = 768 kHz)

[5:4] NS_ORD[1:0]

Noise shape order

00: 3rd. order

01: 4th. order

10: 5th. order

[3] EA_TSFT_ON

1: if there is a fault on the external bridge, it will be put in 3-state

[2] CB_TSFT_ON

1: if there is a fault on the CMOS bridge, it will be put in 3-state

[1] EA_PFDIG

1: enable the pop-free ramp of EA

[0] CB_PFDIG

1: enable the pop-free ramp of CB

Note:

EA_PFDIG

CB_PFDIG

Particular care must be taken when bits NS_ORD and PWM_FREQ are changed. To avoid any audible artifacts, these bits must be modified only with the following procedure:

Mute STA321 processing.

2. Change PWM_FREQ and/or NS_ORD and set RESET_NOISH = 1.

3. Configure RESET_NOISH = 0.

4. Unmute STA321 processing.

Doc ID 15351 Rev 3 83/157

Register description

PWMMAP1 Processing to PWM out mapping

Address:

Type:

Reset:

Description:

CB1_MAP[2:0]

0x03

0x08

5 4 3

CB2_MAP[2:0]

[7:5] CB1_MAP[2:0]

CB_PWM_1 channel mapping:

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

[4:2] CB2_MAP[2:0]

CB_PWM_2 channel mapping

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

[1:0] CB3_MAP[2:1]

CB_PWM_3 channel mapping (for bit 0 see register

PWMMAP2

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

CB3_MAP[2:1]

STA321

84/157 Doc ID 15351 Rev 3

STA321 Register description

PWMMAP2

CB3_MAP[0]

Address:

Type:

Reset:

Description:

0x04

0xB9

PWM00_MAP[2:0]

4 3 2

EA1A_MAP[2:0]

[7] CB3_MAP[0]

CB_PWM_3 channel mapping (for bits 1 and 2 see register

PWMMAP1 )

[6:4] PWM00_MAP[2:0]

PWM00 channel mapping:

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

[3:1] EA1A_MAP[2:0]

EA_PWM_1A channel mapping:

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

[0] EA1B_MAP[2]

EA_PWM_1B channel mapping (for bits 1and 0 see register PWMMAP3

)

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

EA1B_MAP[2]

Doc ID 15351 Rev 3 85/157

Register description STA321

PWMMAP3

EA1B_MAP[1:0]

6 5 4

EA2A_MAP[2:0]

3 2

Address:

Type:

Reset:

Description:

0x05

0x77

[7:6] EA1B_MAP[1:0]

EA_PWM_1B channel mapping (for bit 2 see register PWMMAP2 )

[5:3] EA2A_MAP[2:0]

EA_PWM_2A channel mapping:

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

[2:0] EA2B_MAP[2:0]

EA_PWM_2B channel mapping:

000: Ch0-A

010: Ch1-A

100: Ch2-A

110: Ch3-A

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

001: Ch0-B

011: Ch1-B

101: Ch2-B

111: Ch3-B

EA2B_MAP[2:0]

EATTF0 External bridge tristate time from fault

7 6 5 4

EATTF[15:8]

3 2 1 0

Address:

Type:

Reset:

Description:

0x06

0x00

The tristate time is the time between fault deasserted and 3-state removed for the external bridge. It is calculated as EATTF[15:0] * 41.66 µs

[7:0] EATTF[15:8]

MSBs of the EA tristate time factor

86/157 Doc ID 15351 Rev 3

STA321 Register description

EATTF1 External bridge tristate time from fault

7 6 5

Address:

Type:

Reset:

Description:

0x07

0x03

See also register

EATTF0

[7:0] EATTF[7:0]

LSBs of EA tristate time factor

EATTF[7:0]

3 2 1

EATTP0 External bridge tristate time from powerdown

Address:

Type:

Reset:

Description:

6 5 4 3 2 1

EATTP[15:8]

0x08

0x00

This tristate time is the time between bridge powerdown removed and 3-state removed for the external bridge. It is calculated as EATTP[15:0] * 41.66 µs

[7:0] EATTP[15:8]

MSBs of EA 3-state time after power-up factor

EATTP1 External bridge tristate time from powerdown

7 6 5 4 3

EATTP[7:0]

Address:

Type:

Reset:

Description:

0x09

0x03

See also register

EATTP0

[7:0] EATTP[7:0]

LSBs of EA 3-state time after power-up factor

2 1 0

Doc ID 15351 Rev 3 87/157

Register description STA321

CBTTF0 CMOS bridge tristate time from fault

7 6 5 4 3 2 1 0

Address:

Type:

Reset:

Description:

CBTTF[15:8]

0x0A

0x00

The tristate time is the time between fault deasserted and 3-state removed for the

CMOS bridge. It is calculated as CBTTF[15:0] * 41.66 µs

[7:0] CBTTF[15:8]

MSBs of CB 3-state time factor

CBTTF1 CMOS bridge tristate time from fault

7 6 5

Address:

Type:

Reset:

Description:

0x0B

0x02

See also register

CBTTF0

[7:0] CBTTF[7:0]

LSBs of CB 3-state time factor

CBTTF[7:0]

3 2 1

CBTTP0 CMOS bridge tristate time from powerdown

Address:

Type:

Reset:

Description:

6 5 4

CBTTP[15:8]

3 2 1

0x0C

0x00

This tristate time is the time between bridge powerdown removed and 3-state removed for the CMOS bridge. It is calculated as CBTTP[15:0] * 41.66 µs

[7:0] CBTTP[15:8]

MSBs of CB 3-state time after power-up factor

88/157 Doc ID 15351 Rev 3

STA321 Register description

CBTTP1 CMOS bridge tristate time from powerdown

7 6 5 4 3

CBTTP[7:0]

Address:

Type:

Reset:

Description:

0x0D

0x02

See also register

CBTTP0

[7:0] CBTTP[7:0]

LSBs of CB 3-state time after power-up factor

2 1 0

FFXST

EA_MPWM

CB_MPWM

Address:

Type:

Reset:

Description:

0x0E

0xC0

EARMP_ST[1:0]

[7] EA_MPWM

1: EA is in mute

[6] CB_MPWM

1: CB is in mute

[5:4] EARMP_ST[1:0] : pop free ramp status

00: parked

11: ready

10: going to park

01: going to ready

[3:2] CBRMP_ST[1:0]: pop free ramp status

00: parked

11: ready

10: going to park

01: going to ready

[1] EABINSS_AC

1: ramp active (going to park or ready)

[0] CBBINSS_AC

1: ramp active (going to park or ready)

CBRMP_ST[1:0]

2 1

EABINSS_AC

CBBINSS_AC

Doc ID 15351 Rev 3 89/157

Register description

POWST

7 6

Reserved

0x0F

0x05

Address:

Type:

Reset:

Description:

[7:4] Reserved

[3] EA_TW

1: EA thermal warning

[2] EA_PD

1: EA power-down

[1] EA_FT

1: EA is in fault

[0] EA_TS

1: EA is in 3-state

Status register for external amplifier

4 3

EA_TW

EA_PD

EA_FT

STA321

EA_TS

Reserved

Address:

Type:

Reset:

Description:

CB_PD

0x10

0x47

5 4

CB_FT[2:0]

[7] Reserved

[6] CB_PD

1: CMOS bridge is in power-down

[5:3] CB_FT[2:0] xx1: CMOS bridge channel 1 is in fault x1x: CMOS bridge channel 2 is in fault

1xx: CMOS bridge channel 3 is in fault

[2:0] CB_TS[2:0] xx1: CMOS bridge channel 1 is in 3-state x1x: CMOS bridge channel 2 is in 3-state

1xx: CMOS bridge channel 3 is in 3-state

3 2 1

CB_TS[2:0]

90/157 Doc ID 15351 Rev 3

STA321 Register description

PWMO1CFG0

AZPLS_1

Address:

Type:

Reset:

Description:

TERNARY_1

0x11

0x20

HALFB_1

MP_ZERO_1

[7] AZPLS_1

1: avoid zero pulse

[6] TERNARY_1

1: ternary modulation

[5] HALFB_1

1: 1B is modulated as null signal

[4] MP_ZERO_1

1: apply the minimum pulse settings also for values near 0

[3:0] MIN_PLS_1[3:0] minimum pulse length = clock period * (MIN_PLS_1 + 1)

MIN_PLS_1[3:0]

PWMO1CFG1

PM_1A[1:0]

Address:

Type:

Reset:

Description:

6 5

0x12

0x00

Configuration for PWM-A

4 3

PS_1A[5:0]

[7:6] PM_1A[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_1A[5:0]: PWM shift

The PWM waveform could be shifted by (PS_1A * clock period / 64)

1 0

Doc ID 15351 Rev 3 91/157

Register description

PWMO1CFG2

7 6 5 4 3 2

PM_1B[1:0]

Address:

Type:

Reset:

Description:

0x13

0x48

Configuration for PWM-B

PS_1B[5:0]

[7:6] PM_1B[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: ibrid mode: alternation of modes 00 and 01

11: ibrid mode: alternation of modes 01 and 00

[5:0] PS_1B[5:0]: PWM shift

The PWM waveform could be shifted by (PS_1B * clock period / 64)

PWMO2CFG0

AZPLS_2

Address:

Type:

Reset:

Description:

TERNARY_2

0x14

0x20

HALFB_2

MP_ZERO_2

[7] AZPLS_2

1: avoid zero pulse

[6] TERNARY_2

1: ternary modulation

[5] HALFB_2

1: 2B is modulated as null signal

[4] MP_ZERO_2

1: apply the minimum pulse settings also for values near 0

[3:0] MIN_PLS_2[3:0]

Minimum pulse length = clock period * (MIN_PLS_2 + 1)

MIN_PLS_2[3:0]

STA321

92/157 Doc ID 15351 Rev 3

STA321 Register description

PWMO2CFG1

7 6 5 4 3 2

PM_2A[1:0]

Address:

Type:

Reset:

Description:

0x15

0x10

PS_2A[5:0]

[7:6] PM_2A[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_2A[5:0]: PWM shift

The PWM waveform could be shifted by (PS_2A * clock period / 64)

PWMO2CFG2

PM_2B[1:0]

Address:

Type:

Reset:

Description:

0x16

0x58

5 4 3

PS_2B[5:0]

[7:6] PM_2B[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_2B[5:0]: PWM shift

The PWM waveform could be shifted by (PS_2B * clock period / 64)

Doc ID 15351 Rev 3 93/157

Register description

PWMO3CFG0

AZPLS_3

Address:

Type:

Reset:

Description:

TERNARY_3

0x17

0x00

HALFB_3

MP_ZERO_3

[7] AZPLS_3

1: avoid zero pulse

[6] TERNARY_3

1: ternary modulation

[5] HALFB_3

1: 3B is modulated as null signal

[4] MP_ZERO_3

1: apply the minimum pulse settings also for values near 0

[3:0] MIN_PLS_3[3:0]

Minimum pulse length = clock period * (MIN_PLS_3 + 1)

MIN_PLS_3[3:0]

PWMO3CFG1

PM_3A[1:0]

Address:

Type:

Reset:

Description:

0x18

0x20

5 4 3

PS_3A[5:0]

[7:6] PM_3A[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_3A[5:0]: PWM shift

The PWM waveform could be shifted by (PS_3A * clock period / 64)

STA321

94/157 Doc ID 15351 Rev 3

STA321 Register description

PWMO3CFG2

7 6 5 4 3 2

PM_3B[1:0]

Address:

Type:

Reset:

Description:

0x19

0x68

PS_3B[5:0]

[7:6] PM_3B[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_3B[5:0]: PWM shift

The PWM waveform could be shifted by (PS_3B * clock period / 64)

PWMO4CFG0

AZPLS_4

Address:

Type:

Reset:

Description:

TERNARY_4

0x1A

0x00

HALFB_4

MP_ZERO_4

[7] AZPLS_4

1: avoid zero pulse

[6] TERNARY_4

1: ternary modulation

[5] HALFB_4

1: 4B is modulated as null signal

[4] MP_ZERO_4

1: apply the minimum pulse settings also for values near 0

[3:0] MIN_PLS_4[3:0]

Minimum pulse length = clock period * (MIN_PLS_4 + 1)

MIN_PLS_4[3:0]

Doc ID 15351 Rev 3 95/157

Register description

PWMO4CFG1

7 6 5 4 3 2

PM_4A[1:0]

Address:

Type:

Reset:

Description:

0x1B

0x30

PS_4A[5:0]

[7:6] PM_4A[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_4A[5:0]: PWM shift

The PWM waveform could be shifted by (PS_4A * clock period / 64)

PWMO4CFG2

PM_4B[1:0]

Address:

Type:

Reset:

Description:

0x1C

0x78

5 4 3

PS_4B[5:0]

[7:6] PM_4B[1:0]: PWM mode

00: generate a rising edge using a down carrier

01: generate a falling edge using an up carrier

10: hybrid mode: alternation of modes 00 and 01

11: hybrid mode: alternation of modes 01 and 00

[5:0] PS_4B[5:0]: PWM shift

The PWM waveform could be shifted by (PS_4B * clock period / 64)

STA321

96/157 Doc ID 15351 Rev 3

STA321

CB_PFRAMP1

7 6 5

CBRMP_MP[5:0]

Address:

Type:

Reset:

Description:

0x20

0x14

[7:2] CBRMP_MP[5:0]

Minimum pulse width of the PDM signal

[1:0] Reserved

CB_PFRAMP2

7 6 5

Address:

Type:

Reset:

Description:

[7:0] CBRMPINI[15:8]

MSBs of CB ramp init

CBRMPINI[15:8]

0x21

0x80

Initial value of the ramp signal

CB_PFRAMP3

7 6 5 4

CBRMPINI[7:0]

Address:

Type:

Reset:

Description:

0x22

0x3C

[7:0] CBRMPINI[7:0]

LSBs of CB ramp init

Register description

Reserved

2 1 0

Doc ID 15351 Rev 3 97/157

Register description STA321

CB_PFRAMP4

Address:

Type:

Reset:

Description:

CBTIM_RMP[3:0]

0x23

0x10

[7:4] CBTIM_RMP[3:0]

EA timing duration of the ramp (= slope)

[3:0] Reserved

3 2

Reserved

1 0

CB_PFRAMP5

Address:

Type:

Reset:

Description:

6 5 4

CBRMPTH[15:8]

3 2 1 0

0x24

0x14

During the ramp, if the signal is below the threshold, the signal is modulated with

PDM, otherwise with PWM

[7:0] CBRMPTH[15:8]

MSBs of CB ramp threshold

CB_PFRAMP6

7 6 5 4

CBRMPTH[7:0]

3 2 1 0

Address:

Type:

Reset:

Description:

0x25

0x00

During the ramp, if the signal is below the threshold, the signal is modulated with

PDM, otherwise with PWM

[7:0] CBRMPTH[7:0]

LSBs of CB ramp threshold

98/157 Doc ID 15351 Rev 3

STA321

EA_PFRAMP1

7 6 5

EARMP_MP[5:0]

Address:

Type:

Reset:

Description:

0x26

0x1C

[7:2] EARMP_MP[5:0]

Minimum pulse width of the PDM signal

[1:0] Reserved

EA_PFRAMP2

7 6 5

Address:

Type:

Reset:

Description:

[7:0] EARMPINI[15:8]

MSBs of EA ramp init

EARMPINI[15:8]

0x27

0x80

Initial value of the ramp signal

EA_PFRAMP3

7 6 5 4

EARMPINI[7:0]

Address:

Type:

Reset:

Description:

0x28

0x60

[7:0] EARMPINI[7:0]

LSBs of EA ramp init

Register description

Reserved

2 1 0

Doc ID 15351 Rev 3 99/157

Register description STA321

EA_PFRAMP4

Address:

Type:

Reset:

Description:

EATIM_RMP[3:0]

0x29

0x10

[7:4] EATIM_RMP[3:0]

EA timing duration of the ramp (= slope)

[3:0] Reserved

3 2

Reserved

1 0

EA_PFRAMP5

Address:

Type:

Reset:

Description:

6 5 4

EARMPTH[15:8]

3 2 1 0

0x2A

0x80

During the ramp, if the signal is below the threshold, the signal is modulated with

PDM, otherwise with PWM

[7:0] EARMPTH[15:8]

MSBs of EA ramp threshold

EA_PFRAMP6

7 6 5 4

EARMPTH[7:0]

3 2 1 0

Address:

Type:

Reset:

Description:

0x2B

0x60

During the ramp, if the signal is below the threshold, the signal is modulated with

PDM, otherwise with PWM

[7:0] EARMPTH[7:0]

LSBs of EA ramp threshold

100/157 Doc ID 15351 Rev 3

STA321

SRC1STATE

SRC1_BYP[1:0]

6 5

SRC_1_LOCK

4 3 2

SRC1_FISFO[4:0]

Address:

Type:

Reset:

Description:

0x30

0x8F

Values of f

based on the 96 kHz as output frequency

[7:6] SRC1_BYP[1:0]

00: input signal has f

< 78 kHz

10: input signal has f

> 81 kHz

[5] SRC_1_LOCK

0: SRC target frequency not reached

1: SRC1 target frequency reached

[4:0] SRC1_FISFO[4:0]

MSB Fs_input / Fs_output

SRC2STATE

Address:

Type:

Reset:

SRC1_BYP[1:0]

0x31

0x8F

Description:

SRC_1_LOCK

[7:6] SRC2_BYP[1:0]

00: Input Signal has f

< 78 kHz

10: Input Signal has f

> 81 kHz

[5] SRC_2_LOCK

0: SRC target frequency not reached

1: SRC1 target frequency reached

[4:0] SRC2_FISFO[4:0]

MSB Fs_input / Fs_output

3 2

SRC1_FISFO[4:0]

Register description

Doc ID 15351 Rev 3 101/157

Register description

I2CB0_TOP

7 6 5 4

I2CB0[23:16]

Address:

Type:

Reset:

Description:

0x51

0x00

[7:0] I2CB0[23:16]

MSBs of coefficient b0

I2CB0_MID

7 6 5

Address:

Type:

Reset:

Description:

0x52

0x00

[7:0] I2CB0[15:8]

Middle bits of coefficient b0

I2CB0_BOT

7 6 5 4

I2CB0[7:0]

Address:

Type:

Reset:

Description:

0x53

0x00

[7:0] I2CB0[7:0]

LSBs of coefficient b0

I2CB0[15:8]

2 1

STA321

2 1 0

102/157 Doc ID 15351 Rev 3

STA321

I2CB1_TOP

7 6 5 4

I2CB1[23:16]

Address:

Type:

Reset:

Description:

0x54

0x00

[7:0] I2CB1[23:16]

MSBs of coefficient b1

I2CB1_MID

7 6 5

Address:

Type:

Reset:

Description:

0x55

0x00

[7:0] I2CB1[15:8]

Middle bits of coefficient b1

I2CB1_BOT

7 6 5 4

I2CB1[7:0]

Address:

Type:

Reset:

Description:

0x56

0x00

[7:0] I2CB1[7:0]

LSBs of coefficient b1

I2CB1[15:8]

Register description

1 0

2 1 0

Doc ID 15351 Rev 3 103/157

Register description

I2CB2_TOP

7 6 5 4

I2CB2[23:16]

Address:

Type:

Reset:

Description:

0x57

0x00

[7:0] I2CB2[23:16]

MSBs of coefficient b2

I2CB2_MID

7 6 5

Address:

Type:

Reset:

Description:

0x58

0x00

[7:0] I2CB2[15:8]

Middle bits of coefficient b2

I2CB2_BOT

7 6 5 4

I2CB2[7:0]

Address:

Type:

Reset:

Description:

0x59

0x00

[7:0] I2CB2[7:0]

LSBs of coefficient b2

I2CB2[15:8]

2 1

STA321

2 1 0

104/157 Doc ID 15351 Rev 3

STA321

I2CA1_TOP

7 6 5 4

I2CA1[23:16]

Address:

Type:

Reset:

Description:

0x5A

0x00

[7:0] I2CA1[23:16]

MSBs of coefficient a1

I2CA1_MID

7 6 5

Address:

Type:

Reset:

Description:

0x5B

0x00

[7:0] I2CA1[15:8]

Middle bits of coefficient a1

I2CA1_BOT

7 6 5 4

I2CA1[7:0]

Address:

Type:

Reset:

Description:

0x5C

0x00

[7:0] I2CA1[7:0]

LSBs of coefficient a1

I2CA1[15:8]

Register description

1 0

2 1 0

Doc ID 15351 Rev 3 105/157

Register description

I2CA2_TOP

7 6 5 4

I2CA2[23:16]

Address:

Type:

Reset:

Description:

0x5D

0x00

[7:0] I2CA2[23:16]

MSBs of coefficient a2

I2CA2_MID

7 6 5

Address:

Type:

Reset:

Description:

0x5E

0x00

[7:0] I2CA2[15:8]

Middle bits of coefficient a2

I2CA2_BOT

7 6 5 4

I2CA2[7:0]

Address:

Type:

Reset:

Description:

0x5F

0x00

[7:0] I2CA2[7:0]

LSBs of coefficient a2

I2CA2[15:8]

2 1

STA321

2 1 0

106/157 Doc ID 15351 Rev 3

STA321 Register description

PROCCTRL

7 6

Reserved

0x60

0x00

5 4

Address:

Type:

Reset:

Description:

[7:4] Reserved

[3] RA

1: read all the biquad coefficients

[2] Reserved

[1] WA

1: write/update all the biquad coefficients

[0] W1

1: write/update the b0 coefficient

Reserved

START_ADDR2

7 6 5 4

Reserved

3 2 1

Address:

Type:

Reset:

Description:

0x61

0x00

[7:1] Reserved

[0] I2CSTART_A8

Base address of the biquadratic to be updated (= address of coefficient b0)

I2CSTART_A8

Doc ID 15351 Rev 3 107/157

Register description STA321

START_ADDR1

7 6 5 4

I2CSTART_A7_A0

3 2 1

Address:

Type:

Reset:

Description:

0x62

0x00

[7:0] I2CSTART_A7_A0

Base address of the biquadratic to be updated (= address of the b0 coefficient)

ROM_REMAP

Reserved

ENAB_PRE3

Address:

Type:

Reset:

Description:

0x6F

0x00

ENAB_PRE2

ENAB_PRE1

ENAB_PRE0

[7] Reserved

[6] ENAB_PRE3

0: pre scale value of channel 3 taken from RAM

1: pre scale value of channel 3 taken from ROM

[5] ENAB_PRE2

0: pre scale value of channel 2 taken from RAM

1: pre scale value of channel 2 taken from ROM

[4] ENAB_PRE1

0: pre scale value of channel 1 taken from RAM

1: pre scale value of channel 1 taken from ROM

[3] ENAB_PRE0

0: pre scale value of channel 0 taken from RAM

1: pre scale value of channel 0 taken from ROM

[2] ENAB_POST

0: post mix values taken from RAM

1: post mix values taken from ROM

[1] ENAB_PRMIX

0: pre mix values taken from RAM

1: pre mix values taken from ROM

[0] ENAB_DELAY

0: Delay values taken from RAM

1: Delay values taken from ROM

ENAB_POST

1 0

ENAB_PRMIX ENAB_DELAY

108/157 Doc ID 15351 Rev 3

STA321

BYP_EN_CH0

7 6 5 4

Reserved

Address:

Type:

Reset:

Description:

0x70

0x00

[7:0] Reserved

EFFS_EN_CH0

7 6 5 4

Reserved

Address:

Type:

Reset:

Description:

0x71

0x00

[7:2] Reserved

[1] EROM09

1: enable de-emphasis EQ on channel 0

[0] EROM08

1: enable high-pass filter on channel 0

BYP_EN_CH1

7 6 5 4 3

Reserved

Address:

Type:

Reset:

Description:

0x72

0x00

[7:0] Reserved

3 2

Register description

1 0

2 1

EROM09

EROM08

2 1 0

Doc ID 15351 Rev 3 109/157

Register description

EFFS_EN_CH1

7 6 5 4

Reserved

Address:

Type:

Reset:

Description:

0x73

0x00

[7:2] Reserved

[1] EROM19

1: enable de-emphasis EQ on channel 1

[0] Reserved

BYP_EN_CH2

7 6 5 4

Reserved

Address:

Type:

Reset:

Description:

0x74

0x00

[7:0] Reserved

EFFS_EN_CH2

7 6 5 4

Reserved

Address:

Type:

Reset:

Description:

0x75

0x00

[7:2] Reserved

[1] EROM29

1: enable de-emphasis EQ on channel 2

[0] EROM28

1: enable high-pass filter on channel 2

110/157 Doc ID 15351 Rev 3

2 1

EROM19

Reserved

2 1

STA321

2 1

EROM29

EROM28

STA321 Register description

BYP_EN_CH3

7 6 5 4 3 2 1 0

Reserved

Address:

Type:

Reset:

Description:

0x76

0x00

[7:0] Reserved

EFFS_EN_CH3

7 6 5 4

Reserved

Address:

Type:

Reset:

Description:

0x77

0x00

[7:2] Reserved

[1] EROM39

1: enable de-emphasis EQ on channel 3

[0] Reserved

3 2 1

EROM39

Reserved

BASS_SEL0_R

Reserved

Address:

Type:

Reset:

Description:

0x78

0x00

BASS_EN0

4 3 2

BASS_SEL0

[7:6] Reserved

[5] BASS_EN0

0: Bass EQ of channel 0 is not active

1: Bass EQ of channel 0 is active

[4:0] BASS_SEL0

Select the gain of the bass filter from -12 dB (00000) to +12 dB using

Table 35

below

Doc ID 15351 Rev 3 111/157

Register description STA321

BASS_SEL1_R

Reserved

Address:

Type:

Reset:

Description:

0x79

0x00

BASS_EN1

4 3 2

BASS_SEL1

[7:6] Reserved

[5] BASS_EN1

0: Bass EQ of channel 1 is not active

1: Bass EQ of channel 1 is active

[4:0] BASS_SEL1

Select the gain of the bass filter from -12 dB (00000) to +12 dB using

Table 35

below

BASS_SEL2_R

Reserved

Address:

Type:

Reset:

Description:

0x7A

0x00

BASS_EN2

4 3 2

BASS_SEL2

[7:6] Reserved

[5] BASS_EN2

0: Bass EQ of channel 2 is not active

1: Bass EQ of channel 2 is active

[4:0] BASS_SEL2

Select the gain of the bass filter from -12 dB (00000) to +12 dB using

Table 35

below

112/157 Doc ID 15351 Rev 3

STA321 Register description

BASS_SEL3_R

Reserved

Address:

Type:

Reset:

Description:

0x7B

0x00

BASS_EN3

4 3 2

BASS_SEL3

[7:6] Reserved

[5] BASS_EN3

0: Bass EQ of channel 3 is not active

1: Bass EQ of channel 3 is active

[4:0] BASS_SEL3

Select the gain of the bass filter from -12 dB (00000) to +12 dB using

Table 35

below

TREB_SEL0_R

Reserved

Address:

Type:

Reset:

Description:

0x7C

0x00

TREB_EN0

4 3 2

TREB_SEL0

[7:6] Reserved

[5] TREB_EN0

0: Treble EQ of channel 0 is not active

1: Treble EQ of channel 0 is active

[4:0] TREB_SEL0

Select the gain of the treble filter from -12 dB (00000) to +12 dB using Table 35

below

Doc ID 15351 Rev 3 113/157

Register description STA321

TREB_SEL1_R

Reserved

Address:

Type:

Reset:

Description:

0x7D

0x00

TREB_EN1

4 3 2

TREB_SEL1

[7:6] Reserved

[5] TREB_EN1

0: Treble EQ of channel 1 is not active

1: Treble EQ of channel 1 is active

[4:0] TREB_SEL1

Select the gain of the treble filter from -12 dB (00000) to +12 dB using Table 35

below

TREB_SEL2_R

Reserved

Address:

Type:

Reset:

Description:

0x7E

0x00

TREB_EN2

4 3 2

TREB_SEL2

[7:6] Reserved

[5] TREB_EN2

0: Treble EQ of channel 2 is not active

1: Treble EQ of channel 2 is active

[4:0] TREB_SEL2

Select the gain of the treble filter from -12 dB (00000) to +12 dB using Table 35

below

114/157 Doc ID 15351 Rev 3

STA321 Register description

TREB_SEL3_R

Reserved

Address:

Type:

Reset:

Description:

0x7F

0x00

TREB_EN3

4 3 2

TREB_SEL3

[7:6] Reserved

[5] TREB_EN3

0: Treble EQ of channel 3 is not active

1: Treble EQ of channel 3 is active

[4:0] TREB_SEL3

Select the gain of the treble filter from -12 dB (00000) to +12 dB using Table 35

below

Table 35.

Bass/treble filter gains used in register addresses 0x78 - 0x7F

BASS_SELx

TREBLE_SELx

Gain

BASS_SELx

TREBLE_SELx

Gain

11000

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

+08

+07

+06

+05

+12

+11

+10

+09

+04

+03

+02

+01

+00

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

-04

-05

-06

-07

-01

-02

-03

-08

-09

-10

-11

-12

Doc ID 15351 Rev 3 115/157

Register description

SATCH0CFG1

SAT_EQ

Address:

Type:

Reset:

Description:

0x90

0xFF

5 4 3

SAT_CH0[22:16]

[7] SAT_EQ

0: saturation value of every channel is independent

1: all the channels take the saturation value of channel 0

[6:0] SAT_CH0[22:16]

MSBs of the absolute saturation value for channel 0.

If the signal is above SAT_CH0[22:0] then it is truncated

SATCH0CFG2

7 6 5 4

SAT_CH0[15:8]

Address:

Type:

Reset:

Description:

0x91

0xFF

[7:0] SAT_CH0[15:8]

Middle bits of the saturation value for channel 0

If the signal is above SAT_CH0[22:0] then it is truncated

SATCH0CFG3

7 6 5 4

SAT_CH0[7:0]

Address:

Type:

Reset:

Description:

0x92

0xFF

[7:0] SAT_CH0[7:0]

LSBs of the saturation value for channel 0

If the signal is above SAT_CH0[22:0] then it is truncated

116/157 Doc ID 15351 Rev 3

STA321

1 0

STA321 Register description

SATCH1CFG1

Reserved

Address:

Type:

Reset:

Description:

0x93

0x00

5 4 3

SAT_CH1[22:16]

2 1 0

[7] Reserved

[6:0] SAT_CH1[22:16]

MSBs of the absolute saturation value for channel 1.

If the signal is above SAT_CH1[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

SATCH1CFG2

7 6 5 4

SAT_CH1[15:8]

3 2 1 0

Address:

Type:

Reset:

Description:

0x94

0x00

[7:0] SAT_CH1[15:8]

Middle bits of the saturation value for channel 1

If the signal is above SAT_CH1[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

SATCH1CFG3

7 6 5 4

SAT_CH1[7:0]

3 2 1 0

Address:

Type:

Reset:

Description:

0x95

0x00

[7:0] SAT_CH1[7:0]

LSBs of the saturation value for channel 1

If the signal is above SAT_CH1[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

Doc ID 15351 Rev 3 117/157

Register description STA321

SATCH2CFG1

Reserved

Address:

Type:

Reset:

Description:

0x96

0x00

5 4 3

SAT_CH2[22:16]

2 1 0

[7] Reserved

[6:0] SAT_CH2[22:16]

MSBs of the absolute saturation value for channel 2.

If the signal is above SAT_CH2[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

SATCH2CFG2

7 6 5 4

SAT_CH2[15:8]

3 2 1 0

Address:

Type:

Reset:

Description:

0x97

0x00

[7:0] SAT_CH2[15:8]

Middle bits of the saturation value for channel 2

If the signal is above SAT_CH2[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

SATCH2CFG3

7 6 5 4

SAT_CH2[7:0]

3 2 1 0

Address:

Type:

Reset:

Description:

0x98

0x00

[7:0] SAT_CH2[7:0]

LSBs of the saturation value for channel 2

If the signal is above SAT_CH2[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

118/157 Doc ID 15351 Rev 3

STA321 Register description

SATCH3CFG1

Reserved

Address:

Type:

Reset:

Description:

0x99

0x00

5 4 3

SAT_CH3[22:16]

2 1 0

[7] Reserved

[6:0] SAT_CH3[22:16]

MSBs of the absolute saturation value for channel 3.

If the signal is above SAT_CH3[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

SATCH3CFG2

7 6 5 4

SAT_CH3[15:8]

3 2 1 0

Address:

Type:

Reset:

Description:

0x9A

0x00

[7:0] SAT_CH3[15:8]

Middle bits of the saturation value for channel 3

If the signal is above SAT_CH3[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

SATCH3CFG3

7 6 5 4

SAT_CH3[7:0]

3 2 1 0

Address:

Type:

Reset:

Description:

0x9B

0x00

[7:0] SAT_CH3[7:0]

LSBs of the saturation value for channel 3

If the signal is above SAT_CH3[22:0] then it is truncated, see also register bit

SATCH0CFG1

[7]

Doc ID 15351 Rev 3 119/157

Register description

VOLCFG

SVOL_ON3

SVOL_ON2

Address:

Type:

Reset:

Description:

SVOL_ON1

SVOL_ON0

0xA0

0xF5

The register sets up the soft volume control

TIM_SVOL

[7] SVOL_ON3

0: volume on channel 3 is updated immediately

1: volume on channel 3 is updated gradually with a ramp

[6] SVOL_ON2

0: volume on channel 2 is updated immediately

1: volume on channel 2 is updated gradually with a ramp

[5] SVOL_ON1

0: volume on channel 1 is updated immediately

1: volume on channel 1 is updated gradually with a ramp

[4] SVOL_ON0

0: volume on channel 0 is updated immediately

1: volume on channel 0 is updated gradually with a ramp

[3:0] TIM_SVOL

Set the volume ramp; each volume step (0.5 dB) takes (2

TIM_SVOL

/ f

) s

MVOL Master volume control

7 6 5 4 3 2 1

MVOL

Address:

Type:

Reset:

Description:

0xA1

0x00

[7:0] MVOL

Master volume from 0 dB to -127.5 dB in 0.5 dB steps (volume = MVOL * 0.5 dB)

STA321

120/157 Doc ID 15351 Rev 3

STA321

VOLCH0 Channel 0 volume control

7 6 5 4 3

CVOL0

Address:

Type:

Reset:

Description:

0xA2

0x48

[7:0] CVOL0

Channel 0 volume 36 dB to -91.5 dB in 0.5 dB steps

VOLCH1 Channel 1 volume control

7 6 5 4 3

CVOL1

Address:

Type:

Reset:

Description:

0xA3

0x48

[7:0] CVOL1

Channel 1 volume 36 dB to -91.5 dB in 0.5 dB steps

VOLCH2 Channel 2 volume control

7 6 5 4 3

CVOL2

Address:

Type:

Reset:

Description:

0xA4

0x48

[7:0] CVOL2

Channel 2 volume 36 dB to -91.5 dB in 0.5 dB steps

Register description

Doc ID 15351 Rev 3 121/157

Register description

VOLCH3 Channel 3 volume control

7 6 5 4 3

CVOL3

Address:

Type:

Reset:

Description:

0xA5

0x48

[7:0] CVOL3

Channel 3 volume 36 dB to -91.5 dB in 0.5 dB steps

SAI_IN1_CFG0

S2P1_B_STR

S2P1_LR_L

Address:

Type:

Reset:

Description:

0xB0

0xD2

Reserved

S2P1_MSB

[7] S2P1_B_STR

BICLK strobe

0: active_edge = rising, strb_edge = falling

1: active_edge = falling, strb_edge = rising

[6] S2P1_LR_L

LRCLK strobe

0: left = 0, right = 1

1: left = 1, right = 0

[5] Reserved

[4] S2P1_MSB

MSB first

[3:1] S2P1_DFM[2:0]

Data format

000: left justified

001: I

010: right justified

100: PCM no-delay

101: PCM delay

111: DSP

[0] S2P1_MMD

Master mode

3 2

S2P1_DFM

122/157 Doc ID 15351 Rev 3

STA321

1 0

S2P1_MMD

STA321

SAI_IN1_CFG1

S2P1_DLEN

Address:

Type:

Reset:

Description:

0xB1

0x91

S2P1_BOS

[7:6] S2P1_DLEN

Data length

00: 8 bits

01: 16 bits

10: 24 bits

11: 32 bits

[5:4] S2P1_BOS

BICLK_OS

00: BICLK = 32 * f

01: BICLK = 64 * f

10: BICLK = 128 * f

11: BICLK = 256 * f

[3:2] S2P1_MAP_L

Map left

00: slot 0

01: slot 1

10: slot 2

11: slot 3

[1:0] S2P1_MAP_R

Map right

00: slot 0

01: slot 1

10: slot 2

11: slot 3

4 3

S2P1_MAP_L

Register description

S2P1_MAP_R

Doc ID 15351 Rev 3 123/157

Register description

SAI_OUT_CFG0

P2S_B_STR

P2S_LR_L

SDATAO_ACT

P2S_MSB

Address:

Type:

Reset:

Description:

0xB2

0xD3

[7] P2S_B_STR

BICLK strobe

0: active_edge = rising, strb_edge = falling

1: active_edge = falling, strb_edge = rising

[6] P2S_LR_L

LRCLK strobe

0: left = 0, right = 1

1: left = 1, right = 0

[5] SDATA0_ACT

0: normal behavior

1: SDATAO is disabled

[4] P2S_MSB

MSB first

[3:1] P2S_DFM[2:0]

Data format

000: left justified

001: I

010: right justified

100: PCM no-delay

101: PCM delay

111: DSP

[0] P2S_MMD

Master mode

3 2

P2S_DFM

STA321

1 0

P2S_MMD

124/157 Doc ID 15351 Rev 3

STA321

SAI_OUT_CFG1

P2S_DLEN

Address:

Type:

Reset:

Description:

0xB3

0x91

P2S_BOS

[7:6] P2S_DLEN

Data length

00: 08 bits

01: 16 bits

10: 24 bits

11: 32 bits

[5:4] P2S_BOS

BICLK_OS

00: BICLK = 32 * f

01: BICLK = 64 * f

10: BICLK = 128 * f

11: BICLK = 256 * f

[3:2] P2S_MAP_L

Map left

00: slot 0

01: slot 1

10: slot 2

11: slot 3

[1:0] P2S_MAP_R

Map right

00: slot 0

01: slot 1

10: slot 2

11: slot 3

4 3

P2S_MAP_L

Register description

P2S_MAP_R

Doc ID 15351 Rev 3 125/157

Register description

SAI_IN2_CFG0

S2P2_B_STR

S2P2_LR_L

Address:

Type:

Reset:

Description:

0xB4

0xD2

Reserved

S2P2_MSB

[7] S2P2_B_STR

BICLK strobe

0: active_edge = rising, strb_edge = falling

1: active_edge = falling, strb_edge = rising

[6] S2P2_LR_L

LRCLK strobe

0: left = 0, right = 1

1: left = 1, right = 0

[5] Reserved

[4] S2P2_MSB

MSB first

[3:1] S2P2_DFM[2:0]

Data format

000: left justified

001: I

010: right justified

100: PCM no-delay

101: PCM delay

111: DSP

[0] S2P2_MMD

Master mode

STA321

S2P2_DFM

1 0

S2P2_MMD

126/157 Doc ID 15351 Rev 3

STA321

SAI_IN2_CFG1

S2P2_DLEN

Address:

Type:

Reset:

Description:

0xB5

0x91

S2P2_BOS

[7:6] S2P2_DLEN

Data length

00: 8 bits

01: 16 bits

10: 24 bits

11: 32 bits

[5:4] S2P2_BOS

BICLK_OS

00: BICLK = 32 * f

01: BICLK = 64 * f

10: BICLK = 128 * f

11: BICLK = 256 * f

[3:2] S2P2_MAP_L

Map left

00: slot 0

01: slot 1

10: slot 2

11: slot 3

[1:0] S2P2_MAP_R

Map right

00: slot 0

01: slot 1

10: slot 2

11: slot 3

4 3

S2P2_MAP_L

Register description

S2P2_MAP_R

Doc ID 15351 Rev 3 127/157

Register description STA321

AUIFSHARE

7 6 5

Reserved

4 3 2 1

SHARE_BILR

Address:

Type:

Reset:

Description:

0xB6

0x00

[7:2] Reserved

[1:0] SHARE_BILR

00: no clock sharing

01: SAI_in1, SAI_in2 share the clocks: BICLKI1 and LRCLKI1 (others are not used)

SAI1: can be master/slave (see config)

SAI2: always slave

10: SAI_in1, SAI_in2, SAI_out share the clocks: BICLKI1 and LRCLKI1 (others arenot used)

SAI_out: can be master/slave (see config)

SAI1 and SAI2: always slave

11: no clock sharing

SRCINSEL

SRC1_INSEL

Address:

Type:

Reset:

Description:

0xB7

0x28

SRC2_INSEL

4 3

MUTE_SRCU

2 1

Reserved

[7:6] SRC1_INSEL

Sample rate converter IN channels 0 and 1:

00: serial audio interface IN 1

01: ADC

1x: serial audio interface IN 2

[5:4] SRC2_INSEL

Sample rate converter IN channels 2 and 3:

00: serial audio interface IN 1

01: ADC

1x: serial audio interface IN 2

[3] MUTE_SRCU0:

1: The device will be put in mute if the SRC is not locked at the 96 kHz sample frequency

[2:0] Reserved

128/157 Doc ID 15351 Rev 3

STA321

P2SDATA

Reserved

Address:

Type:

Reset:

Description:

P2S_HFS

0xB8

0x00

5 4

P2S1_DSEL

[7] Reserved

[6] P2S_HFS

SAI OUT:

0: 96 kHz

1: half processing frequency (48 kHz)

[5:3] P2S1_DSEL

SAI OUT 1

000: ADC

001: SAI IN 1

010: SAI IN 2

011: SRC channels 0-1

100: SRC channels 2-3

101: processing channels 0 - 1

110: processing channels 2 - 3

[2:0] P2S2_DSEL

SAI OUT 2

000: ADC

001: SAI IN 1

010: SAI IN 2

011: SRC channels 0-1

100: SRC channels 2-3

101: processing channels 0 - 1

110: processing channels 2 - 3

Register description

2 1

P2S2_DSEL

Doc ID 15351 Rev 3 129/157

Register description STA321

PLLCFG0

PLL_DPROG

PLL_FR_CTRL

Address:

Type:

Reset:

Description:

0xC0

0x00

PLL_DDIS

4 3 2

PLL_IDF

[7] 0: PLL takes the internal settings

1: PLL takes the register settings

[6] PLL_FR_CTRL

0: fractional frequency synthesis disabled

1: fractional frequency synthesis enabled

[5:4] PLL_DDIS

PLL dither disable x0: triangular PDF dither input enabled x1: triangular PDF dither input disabled

0x: rectangular PDF dither input enabled

1x: rectrangular PDF dither input disabled

[3:0] PLL_IDF

Set the input division factor of the PLL (see Section 5.3: Fractional PLL on page 31

)

PLLCFG1

Address:

Type:

Reset:

Description:

0xC1

0x00

See also

5 4

PLL_FRAC[15:8]

Section 5.3: Fractional PLL on page 31

2 1

[7:0] PLL_FRAC[15:8]

The MSBs of PLL_FRAC[15:0] which is used to set the PLL multiplication factor

130/157 Doc ID 15351 Rev 3

STA321 Register description

PLLCFG2

7 6 5 4

PLL_FRAC[7:0]

3 2 1

Address:

Type:

Reset:

Description:

0xC2

0x00

[7:0] PLL_FRAC[7:0]

The LSBs of PLL_FRAC[15:0] which is used to set the PLL multiplication factor

PLLCFG3

PLL_STRB

PLL_STRBBYP

Address:

Type:

Reset:

Description:

5 4 3

PLL_NDIV

0xC3

0x00

2 1 0

[7] PLL_STRB

0: normal behaviour

1: asynchronous strobe input, a new configuration input is loaded into the fraction controller

[6] PLL_STRBBYP

0: normal behaviour

1: bypass the strobe signal

[5:0] PLL_NDIV

Set the PLL multiplication factor (integral part), loop division factor (LDF)

Doc ID 15351 Rev 3 131/157

Register description

PLLPFE

PLL_BYP_UNL

BICLK2PLL

Address:

Type:

Reset:

Description:

0xC4

0x80

PLL_PWDN

PLL_NOPDDIV

3 2

Reserved

[7] PLL_BYP_UNL

0: PLL clock is not bypassed if it is unlock

1: PLL clock is bypassed if it is unlock, the external clock is used as system clock

[6] BICLK2PLL

PLL clock in selection

0: normal behaviour

1: BICLKI1 is used as PLL clock source

[5] PLL_PWDN

0: normal behaviour

1: PLL goes into power-down mode

[4] PLL_NOPDDIV

0: PLL goes to power-down when the divider settings are changed

1: PLL remains active when the divider settings are changed

[3:0] Reserved

PLLST

PLL_UNLOCK

PLL_PWD_ST

Address:

Type:

Reset:

Description:

0xC5

0x00

PLL_BYP_ST

PLL status

[7] PLL_UNLOCK

0: normal behaviour

1: PLL is not locked

[6] PLL_PWD_ST

0: normal behaviour

1: PLL is in power-down mode

[5] PLL_BYP_ST

0: PLL is selected

1: PLL is bypassed

3 2

Reserved

STA321

132/157 Doc ID 15351 Rev 3

STA321 Register description

[4:0] Reserved

ADCCFG0

Address:

Type:

Reset:

Description:

ADC_PGA

0xC6

0x00

5 4

ADC_INSEL

ADC_STBY

[7:5] ADC_PGA

Programmable gain amplifier:

000: 0 dB

001: +6 dB

010: +12 dB

011: +18 dB

100: +24 dB

101: +30 dB

110: +36 dB

111: +42 dB

[4] ADC_INSEL

0: line input mode selected

1: mike input mode selected

[3] ADC_STBY

0: ADC normal mode

1: ADC standby mode for power reduction

[2] ADC_BYPCAL

0: DC-removal block enabled

1: bypass DC-removal block

[1] CLK_ADC_ON

0: ADC clock disabled

1: ADC clock active

[0] Reserved

2 1

ADC_BYPCAL CLK_ADC_ON

Reserved

Doc ID 15351 Rev 3 133/157

Register description STA321

CKOCFG

CLKOUT_DIS

CLKOUT_SEL

5 4

CLK_FFX_ON

3 2 1

CLK_SRC_ON CLK_PROC_ON EAPWM_DIS

Address:

Type:

Reset:

Description:

0xC7

0x1C

[7] CLKOUT_DIS

0: CLKOUT is enabled

1: CLKOUT is disabled

[6:5] CLKOUT_SEL

00: system clock / 4

01: system clock / 2

10: system clock / 4

11: system clock / 8

[4] CLK_FFX_ON

0: FFX clock disabled

1: FFX clock active

[3] CLK_SRC_ON

0: sample rate converter clock disabled

1: sample rate converter clock active

[2] CLK_PROC_ON

0: process block clock disabled

1: process block clock active

[1] EAPWM_DIS

0: EA PWM output is enable

1: EA PWM output is disabled

[0] PWM00ACT

0: output PWM00 is at logical 0

1: Output PWM00 is active

PWM00ACT

134/157 Doc ID 15351 Rev 3

STA321

MISC

OSC_DIS

Address:

Type:

Reset:

Description:

0xC8

0x20

S2P_FS_RNG

4 3

ADC_FS_RNG

[7] OSC_DIS

0: normal behaviour

1: XT oscillator is disabled

[6:4] S2P_FS_RNG

Serial audio interface sampling frequency, f

, range:

000: 8 - 12 kHz (very low)

001: 16 - 24 kHz (low)

010: 32 - 48 kHz (normal)

011: 64 - 96 kHz (high)

100: 128 - 192 kHz (very high)

[3:2] ADC_FS_RNG

ADC sampling frequency, f

, range:

00: 32 - 48 kHz (normal)

01: 16 - 24 kHz (low)

1x: 8 - 12 kHz (very low)

[1] Reserved

[0] CLK_CORE_ON

0: core clock disabled

1: core clock active

Register description

Reserved

CLK_CORE_ON

Doc ID 15351 Rev 3 135/157

Register description STA321

PLLB

PLL_BYP

Address:

Type:

Reset:

Description:

Reserved

ADC_CLKSEL

Reserved

P2S1_CLKSEL

Reserved

0xC9

0x80

P2S2_CLKSEL

[7] PLL_BYP

0: PLL not bypassed

1: PLL bypassed

[6] Reserved

[5] ADC_CLKSEL

0: clk_adc / 4

1: pll_clk_in

[4] Reserved

[3] P2S1_CLKSEL

0: processing clock

1: pll_clk_in

[2] Reserved

[1] P2S2_CLKSEL

0: processing clock

1: pll_clk_in

[0] Reserved

Reserved

136/157 Doc ID 15351 Rev 3

STA321

HPDET1

HPD_SEL

HPD_POL

HPD_ACT_MODE

4 3

HPD_HPMOD

Address:

Type:

Reset:

Description:

0xCA

0x40

[7] HPD_SEL

Select the headphone detection threshold

0: HP1

1: HP2

[6] HPD_POL

Polarity of the detection signal

[5:4] HPD_ACT_MODE

Action to be done in case of detection:

00: inactive

01: mute EA and un-mute CB

10: 3-state EA and un-3-state CB

11: power-down EA and power-up CB

[3] HPD_HPMOD

0: normal behaviour

1: FFX is in headphone modulation mode

[2:0] HPD_TIM_F

000: 1.33 ms

001: 2.66 ms

010: 5.33 ms

011: 10.66 ms

100: 21.33 ms

101: 42.66 ms

110: 85.33 ms

111: 170.67 ms

Register description

HPD_TIM_F

Doc ID 15351 Rev 3 137/157

Register description

HPDET2

E_HP2

Address:

Type:

Reset:

Description:

E_HP1

0xCB

0xC0

TUD_EN

4 3

Reserved

[7] E_HP2

0: headphone detection 2 is disabled

1: headphone detection 2 is enabled

[6] E_HP1

0: headphone detection 1 is disabled

1: headphone detection 1 is enabled

[5] TUD_EN

1: disable the pull-up resistor of the headphones detector

[4:2] Reserved

[1] E_HPDET1

Headphone 1 detector line (not filtered)

[0] E_HPDET2

Headphone 2 detector line (not filtered)

HPDST Headphone detection status

HPD_DET_FILT

Address:

Type:

Reset:

Description:

0xCC

0x00

[7] HPD_DET_FILT

0: no headphones

1: headphones detected

[6:0] Reserved

4 3

Reserved

E_HPDET1

E_HPDET2

STA321

138/157 Doc ID 15351 Rev 3

STA321 Register description

STBY_MODES

PAD_PULLDIS

6 5 4

Reserved

3 2 1

CMP_EN_N

DC_STBY_EN_

Address:

Type:

Reset:

Description:

0xCD

0x00

[7] PAD_PULLDIS

0: Enable the pull (up/down) of the pads

1: Disable the pull (up/down) of the pads

[6:2] Reserved

[1] CMP_EN_N

0: compensation cell is active

1: compensation cell goes into power-down mode when pin STBY is asserted

[0] DC_STBY_EN_N

0: DC regulators are active

1: DC regulators go into power-down mode when pin STBY is asserted

ADCCFG1

ADC_ANA_SEL

Address:

Type:

Reset:

Description:

0xCE

0x00

[7:6] ADC_ANA_SEL

00: INL1, INR1

01: INL2, INR2

1x: reserved

[5:0] Reserved

ADC analog input selection

4 3

Reserved

2 1 0

Doc ID 15351 Rev 3 139/157

Register description

PFEFAULT

7 6

Reserved

5 4

PFE1

PFE2

Address:

Type:

Reset:

Description:

0xCF

0x00

[7:5] Reserved

[4] PFE1

0: analog pop free disabled on bridge output 1

1: analog pop free enabled bridge output 1

[3] PFE2

0: analog pop free disabled on bridge output 2

1: analog pop free enabled bridge output 2

[2] PFE3

0: analog pop free disabled on bridge output 3

1: analog pop free enabled bridge output 3

[1] RESET_EA_FT

0: normal operation

1: reset register bit POWST [1]

[0] RESET_CB_FT

0: normal operation

1: reset register bits

POWST1

[5:3]

STA321

PFE3

1 0

RESET_EA_FT RESET_CB_FT

140/157 Doc ID 15351 Rev 3

STA321

BISTRUN0 BIST control

SF1_BRUN

SF2_BRUN

Address:

Type:

Reset:

Description:

0xD0

0x00

SS1_BRUN

[7] SF1_BRUN

SRC1 RAM

0: normal functional mode

1: start the BIST

[6] SF2_BRUN

SRC2 RAM

0: normal functional mode

1: start the BIST

[5] SS1_BRUN

SRC1 RAM

0: normal functional mode

1: start the BIST

[4] SS2_BRUN

SRC2 RAM

0: normal functional mode

1: start the BIST

[3] CF_BRUN

PROC RAM (coefficients)

0: normal functional mode

1: start the BIST

[2] PR_BRUN

PROC RAM (program)

0: normal functional mode

1: start the BIST

[1] CF_ROM_BRUN

PROC RAM (coefficients)

0: normal functional mode

1: start the BIST

[0] Reserved

SS2_BRUN

CF_BRUN

Register description

PR_BRUN

CF_ROM_BRUN

Reserved

Doc ID 15351 Rev 3 141/157

Register description

BISTRUN1

OS_BRUN

DB_BRUN

Address:

Type:

Reset:

Description:

0xD1

0x00

[7] OS_BRUN

FFX RAM

0: normal functional mode

1: start the BIST

[6] DB_BRUN

FFX RAM

0: normal functional mode

1: start the BIST

[5:0] Reserved

4 3

Reserved

BISTST0 BIST status register 0

SF1_BEND

SF1_BBAD

Address:

Type:

Reset:

Description:

0xD2

0x00

SF1_BFAIL

SF2_BEND

SF2_BBAD

[7] SF1_BEND:

For SRC1 RAM BIST

0: normal functional mode

1: BIST is finished

[6] SF1_BBAD

For SRC1 RAM BIST

0: no faults detected

1: at least one fault detected

[5] SF1_BFAIL

For SRC1 RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

SF2_BFAIL

STA321

SS1_BEND

SS1_BBAD

142/157 Doc ID 15351 Rev 3

STA321

[4] SF2_BEND

For SRC2 RAM BIST

0: normal functional mode

1: BIST is finished

[3] SF2_BBAD

For SRC2 RAM BIST

0: no faults detected

1: at least one fault detected

[2] SF2_BFAIL

For SRC2 RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

[1] SS1_BEND

For SRC1 RAM BIST

0: normal functional mode

1: BIST is finished

[0] SS1_BBAD

For SRC1 RAM BIST

0: no faults detected

1: at least one fault detected

Register description

Doc ID 15351 Rev 3 143/157

Register description

BISTST1 BIST status register 1

SS1_BFAIL

SS2_BEND

Address:

Type:

Reset:

Description:

0xD3

0x00

SS2_BBAD

SS2_BFAIL

CF_BEND

[7] SS1_BFAIL

For SRC1 RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

[6] SS2_BEND:

For SRC2 RAM BIST

0: normal functional mode

1: BIST is finished

[5] SS2_BBAD

For SRC2 RAM BIST

0: no faults detected

1: at least one fault detected

[4] SS2_BFAIL

For SRC2 RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

[3] CF_BEND:

For PROC RAM BIST

0: normal functional mode

1: BIST is finished

[2] CF_BBAD

For PROC RAM BIST

0: no faults detected

1: at least one fault detected

[1] CF_BFAIL

For PROC RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

[0] PR_BEND:

For PROC RAM BIST

0: normal functional mode

1: BIST is finished

CF_BBAD

STA321

CF_BFAIL

PR_BEND

144/157 Doc ID 15351 Rev 3

STA321

BISTST2 BIST status register 2

PR_BBAD

PR_BFAIL

Address:

Type:

Reset:

Description:

0xD4

0x00

OS_BEND

OS_BBAD

OS_BFAIL

[7] PR_BBAD

For PROC RAM BIST

0: no faults detected

1: at least one fault detected

[6] PR_BFAIL

For PROC RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

[5] OS_BEND:

For FFX RAM BIST

0: normal functional mode

1: BIST is finished

[4] OS_BBAD

For FFX RAM BIST

0: no faults detected

1: at least one fault detected

[3] OS_BFAIL

For FFX RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

[2] DB_BEND:

For FFX RAM BIST

0: normal functional mode

1: BIST is finished

[1] DB_BBAD

For FFX RAM BIST

0: no faults detected

1: at least one fault detected

[0] DB_BFAIL

For FFX RAM BIST

0: no faults detected in the current location

1: at least one fault detected in the current location

DB_BEND

Register description

DB_BBAD

DB_BFAIL

Doc ID 15351 Rev 3 145/157

Register description

BISTST3 BIST status register 3

CF_ROM_BEND

Address:

Type:

Reset:

Description:

0xD5

0x00

5 4

[7] CF_ROM_BEND

ROM BIST computation is finished

[6:0] Reserved

Reserved

2 1

STA321

146/157 Doc ID 15351 Rev 3

STA321 Register description

ROMSIGN0 ROM BIST signature (LSBs)

7 6 5 4

CF_ROMS[7:0]

Address:

Type:

Reset:

Description:

0xD6

0x00

[7:0] CF_ROMS[7:0]

LSBs of ROM BIST signature CF_ROMS[23:0]

ROMSIGN1 ROM BIST signature (middle bits)

7 6 5 4

CF_ROMS[15:8]

Address:

Type:

Reset:

Description:

0xD7

0x00

[7:0] CF_ROMS[15:8]

Middle bits of ROM BIST signature CF_ROMS[23:0]

2 1

ROMSIGN2 ROM BIST signature (MSBs)

7 6 5 4

CF_ROMS[23:16]

Address:

Type:

Reset:

Description:

0xD8

0x00

[7:0] CF_ROMS[23:16]

MSBs of ROM BIST signature CF_ROMS[23:0]

2 1

Doc ID 15351 Rev 3 147/157

Register description

DEBUG0

DBGCKO_ON

6 5 4 3

DBGCKO_VAL

Address:

Type:

Reset:

Description:

0xD9

0x00

[7] DBGCKO_ON

0: normal behaviour

1: CLKOUT exports internal clocks as defined by bits DBGCKO_VAL

[6:0] DBGCKO_VAL

0x00: invalid_inp_fbk

0x01: mute_int_fbk

0x02: binss_fbk

0x21: debug_start

0x22: debug_data_end

0x23: debug_data_ok

0x24: debug_lrclk_old

0x25: debug_biclk

0x40: clk_proc

0x41: clk_src

0x42: clk_ffx

0x50: src_1_lock

0x51: src_2_lock

0x52: src_1_bypass_state[0]

0x53: src_1_bypass_state[1]

0x54: src_2_bypass_state[0]

0x55: src_2_bypass_state[1]

0x56: pwm_sync

0x57: s2p_1_bad_clocks

0x58: s2p_2_bad_clocks

0x59: s2p_1_missing_biclk all other values: no clock exported

STA321

148/157 Doc ID 15351 Rev 3

STA321 Register description

PADST0

PAD_RSTN

Reserved

PAD_SCL

Address:

Type:

Reset:

Description:

0xF0

0xA0

[7] PAD_RSTN

[6] Reserved

[5] PAD_SCL

[4] PAD_SDA

[3] PAD_I2CDIS

[2:1] Reserved

[0] PAD_STBY

Pad status 0

PAD_SDA

PAD_I2CDIS

Reserved

PADST1

PAD_MUTE

PAD_BICLKI

Address:

Type:

Reset:

Description:

0xF1

0x74

PAD_LRCLKI

[7] PAD_MUTE

[6] PAD_BICLKI

[5] PAD_LRCLKI

[4] PAD_SDATAI

[3] PAD_BICLKO

[2] PAD_LRCLKO

[1:0] Reserved

PAD_SDATAI

PAD_BICLKO

PAD_LRCLKO

Reserved

PAD_STBY

Doc ID 15351 Rev 3 149/157

C disabled (microless) mode

15 I

C disabled (microless) mode

Figure 55.

Microless mode block diagram

STA321

SDATAO1

BICLKI1

LRCLKI1

SDATAI1

BICLKI2

LRCLKI2

SDATAI2

INL1

INL2

INR1

INR2

V_BIAS

VCM

VHI

VLO

Output

SAI

Input

SAI

4-channel sample rate converter

ADC

Osc PLL Divider

Vol ctrl

FFX™ modulator

CMOS bridge

EAFTN

EATSN

EAPDN

EAPWM4

EAPWM3

EAPWM2

EAPWM1

OUT1

OUT2

OUT3

PWM00

150/157

In microless mode (I2CDIS = 1) the I

C interface is inhibited and SDA and SCL are used as static inputs. The device is working in the configuration shown in

Figure 55

with the ADC connected to input line 1 and to SAI out. The processing chain uses the inputs from SAI input 1. The working modes are selected via the logical levels on the inputs SDA, SCL as follows: z z

SCL = 0 : CMOS bridge outputs come from digital input serial audio interface;

SCL = 1 : CMOS bridge outputs come from analog ADC input.

SDA = 0 : external amplifier outputs come from digital input serial audio interface;

SDA = 1 : external amplifier outputs come from analog ADC input.

At power-up the channel volume is set to -60 dB. The volume is controlled by pulsing the inputs LRCLKO and BICLKO as follows: z z when pulsing LRCLKO = 1 and BICLKO = 1 simultaneously the channel volume is set to 0 dB.

Any LRCLKO = 1 pulse causes a channel volume decrease of 0.5 dB.

z Any BICLKO = 1 pulse causes a channel volume increase of 0.5 dB.

The channel volume change applies only to the external amplifier.

The digital output serial audio interface is always fed with the result of the ADC conversion with no volume control (line-out mode). It is in master mode when SCL = 1 and SDA = 1 otherwise it is in slave mode. It is configured in I

S format.

The LRCLK and BICLK signals are shared between input and output SAI.

Doc ID 15351 Rev 3

STA321 I

C disabled (microless) mode

The input sampling frequency must be between 32 kHz and 48 kHz and the master clock input (MCLK or XTI) must be 256 * f

z z z z

The CMOS bridge FFX output is configured in line-out mode: z left channel binary on OUT1 right channel binary on OUT2 zero signal binary (duty cycle 50%) on OUT3 z pop-free digital ramp active volume control not effective (always 0 dB) switching frequency 384 kHz.

z z

The external amplifier FFX output is configured in BTL mode: z left channel BTL (new ternary modulation) on EAPWM1 and EAPWM2 z right channel BTL (new ternary modulation) on EAPWM1 and EAPWM2 volume control is effective switching frequency 384 kHz.

The headphone detection is disabled.

The CLKOUT pad is active at the PLL frequency of 2048 * f

Doc ID 15351 Rev 3 151/157

Package mechanical data

16 Package mechanical data

STA321

The STA321 comes in a 64-pin, 10 mm x 10 mm, LQFP, exposed pad down (EPD) package.

The reference number is JEDEC MS-026-BCD-HD.

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

Figure 56.

LQFP-64L EPD outline drawing

152/157 Doc ID 15351 Rev 3

STA321 e

E3 c

A2 b

Table 36.

LQFP-64L EPD dimensions

Dimensions in mm

Symbol

Min Typ Max

12.00

10.00

7.50

0.50

5.89

0.60

1.00

1.40

0.22

12.00

10.00

7.50

11.80

9.80

0.45

0.05

1.35

0.17

0.09

11.80

9.80

12.20

10.20

0.75

1.60

0.15

1.45

0.27

0.20

12.20

10.20

S 6.00

S1 ccc k

6.00

3.5

0.08

7.0

Package mechanical data

3.5

0.003

7.0

Doc ID 15351 Rev 3 153/157

Glossary

17 Glossary

STA321

Total harmonic distortion + noise (THDN)

The ratio of the RMS value of all the spectral components in the specified band (20 Hz -

20 kHz) to the RMS values of the signal fundamental component. THDN is measured at

0 dBfs input at a frequency of 1 kHz.

Signal to noise plus distortion ratio (SNDR)

Ratio between power of signal fundamental component and “noise+distortion”. It is measured at different input levels: 0 dBfs, -3 dBfs, -6 dBfs, -10 dBfs, -20 dBfs, -40 dBfs,

-60 dBfs. When the signal amplitude is less than 0 dBfs, that much dB is added to obtain the final SNR. For example, if SNDR is 87 dB with -6dBfs signal, then SNR = 87 + 6 = 93 dB.

Dynamic range (DR)

Dynamic range is measured using SNDR at -60 dBfs, 1 kHz signal and adding 60 dB. For example, if SNDR with -60 dBfs is 38 dB then the dynamic range is 38 + 60 = 98 dB.

Crosstalk

Crosstalk is the measure of the inter-channel isolation between the left and right channels of a stereo system. It is measured at each output with zero input to the channel under test and a full-scale input applied to the other channel.

Deviation from linear phase

Measurement bandwidth 20 Hz to 20 kHz, f

= 48 kHz. The measurement takes into account the combined digital and analog filter characteristics.

Pass band, pass-band ripple, stop band, stop-band attenuation

These parameters take into account both analog and digital filter characteristics. Stop-band attenuation should be measured between 0.55 * f

and 3.45 * f

154/157 Doc ID 15351 Rev 3

STA321

18

Trademarks and other acknowledgements

Trademarks and other acknowledgements

SoundTerminal, FFX and pfStart are trademarks of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.

Doc ID 15351 Rev 3 155/157

Revision history STA321

Table 37.

Document revision history

Date Revision

27-Mar-2009

11-May-2009

30-Oct-2009

Changes

Initial release.

Updated Table 1: Device summary on page 1

Added ambient temperature to

Updated Table 6: Electrical specifications on page 14

Updated resistor to 32 Ω

in Figure 3: Test circuit on page 17

Updated and moved Headphone detector threshold limits table

from Chapter 12 on page 72

and merged into

Table 6: Electrical specifications on page 14

Updated HPDET2 bitfield in Table 34: Register summary on page 77

Updated description of register

HPDET2 on page 138

Updates to feature list

on page 1

Updated Chapter 1: Overview on page 9

Updated Chapter 16: Package mechanical data on page 152

156/157 Doc ID 15351 Rev 3

STA321

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Doc ID 15351 Rev 3 157/157

Reklama

4-channel digital audio system with FFX™ driver

Features

Contents

List of tables

List of figures

1 Overview

STA321

3.1

3.2

Absolute maximum ratings

Recommended operating conditions

4 Power-up and power-down sequences

4.3

Hardware power-down mode

5.2

Peripheral clock manager

Phase/frequency detector (PFD)

Charge pump and loop filter (LPF/CPUMP)

Voltage controlled oscillator (VCO)

Input frequency divider (IDF)

Loop frequency divider (LDF)

Lock circuit

6 Digital processing stage

6.2 Sampling rate converter

6.3

Pre-EQ mix 1 and post-EQ mix

6.5 Equalization, tone control and effects

6.6 Biquads

6.9

Bass and treble control

6.11 Volume and mute control

6.13 FFX channel re-mapping

7 FFX

7.3

PWM shift feature

without shift

AB

A

B with shift

A

B

AB

7.5 Minimum pulse limitation

8 CMOS power stage

9 Fault detection and recovery

10 ADC

10.1 Description

11 Serial audio interface

13 I

C interface

Byte write

Multi-byte write

Current address byte read

Current address multi-byte read

Random address byte read

Random address multi-byte read

15 I

C disabled (microless) mode

16 Package mechanical data

17 Glossary

Total harmonic distortion + noise (THDN)

Signal to noise plus distortion ratio (SNDR)

Dynamic range (DR)

Crosstalk

Deviation from linear phase

Pass band, pass-band ripple, stop band, stop-band attenuation

18

Trademarks and other acknowledgements

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