Digital processing stage
6 Digital processing stage
STA321
The STA321 provides 4 channels of audio signal processing. The block diagram is shown in the following figure.
Figure 13.
Processing flow
Sample rate converter
- G0
- G1
- G2
- G3
Pre scaler
Bq0 Bq12
Bq0 Bq12
Bq0 Bq12
Bq0 Bq12
EQ - tone control
13 biquads kZ
-1 kZ
-1 kZ
-1 kZ
-1
Delay
Vol 0
Vol 1
Vol 2
Vol 3
Volume control Limiter
Left and right channels coming from the two serial audio interfaces and ADC (left and right channels) are fed into the selection multiplexer (controlled by register
SRCINSEL on page 128
), so that each channel can be connected to any desired processing chain. The four channels are then sample rate converted to the fixed internal sampling rate. Pre mix,
EQ/tone processing, programmable delay, post mix, and volume/limiter make up the
STA321 signal processing chain.
Figure 14.
Processing data multiplexer
SRCINSEL[7:6]
SAI_in1
ADC
SAI_in2
32
16
32
00
01
10
SAI_in1
ADC
SAI_in2
32
16
32
00
01
10
SRC1
SRC2
24
24 ch0_in ch1_in
PROC ch0
PROC ch1
PROC ch2
PROC ch3
Processing ch2_in ch3_in ch0_out ch1_out ch2_out ch3_out
20
20
20
20
24
24
24
24
To SAI_out multiplexers
FFX
SRCINSEL[5:4]
2-channel signal
1-channel signal
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