STMicroelectronics ST72521AR9-Auto Datasheet
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ST72521xx-Auto
8-bit MCU for automotive with 32/60 Kbyte Flash/ROM,
ADC, 5 timers, SPI, SCI, I2C, CAN interface
Features
■
■
Memories
■ 32 to 60 Kbyte dual voltage High Density Flash
(HDFlash) or ROM with readout protection capability. In-application programming and incircuit programming for HDFlash devices
1 to 2 Kbyte RAM
HDFlash endurance: 100 cycles, data retention
20 years
■
■
Clock, reset and supply management
■
■
Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector
(AVD) with interrupt capability
Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
PLL for 2x frequency multiplication
4 power saving modes: Halt, Active Halt, Wait and Slow
Interrupt management
■
■
■
■
Nested interrupt controller
14 interrupt vectors plus TRAP and RESET
Top Level Interrupt (TLI) pin
15 external interrupt lines (on 4 vectors)
Analog peripheral
■ 10-bit ADC with up to 16 input ports
Up to 64 I/O ports
■
■
■
48 multifunctional bidirectional I/O lines
34 alternate function lines
16 high sink outputs
LQFP80
14 x 14
LQFP64
14 x 14
LQFP64
10 x 10
■
■
5 timers
■
■
Main clock controller with Real-time base,
Beep and Clock-out capabilities
Configurable watchdog timer
Two 16-bit timers with 2 input captures, 2 output compares, external clock input on 1 timer, PWM and pulse generator modes
8-bit PWM auto-reload timer with 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
4 communications interfaces
■
■
■
■
SPI synchronous serial interface
SCI asynchronous serial interface
I
2
C multimaster interface (SMbus V1.1 compliant)
CAN interface (2.0B passive)
Instruction set
■
■
■
■
8-bit data manipulation
63 basic instructions
17 main addressing modes
8x8 unsigned multiply instruction
Development tools
■ Full HW/SW development pkg, ICT capability
Table 1.
Reference
Device summary
Part number
ST72521xx-Auto
ST72521R6-Auto
ST72521R9-Auto
ST72521AR9-Auto
ST72521M9-Auto
July 2010 Doc ID 17660 Rev 1 1/276 www.st.com
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Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 44
Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 50
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 57
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 62
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 83
Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Main clock controller with real-time clock and beeper (MCC/RTC) . . 85
Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 88
PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 93
External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 93
External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . . 99
Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 119
Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 120
Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 120
Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 120
Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 121
13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 121
13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 133
Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 138
Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 155
Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 156
I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
I2C control register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
I2C status register 2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
I2C clock control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
I2C data register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
I2C own address register (OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
I2C own address register (OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
General purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
CPU write access (more than one cycle) corrupts CAN frame . . . . . . 196
Unexpected message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
WKPS functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Bus-off state not entered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
A/D converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Starting the conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
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Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 222
Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 222
External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . 223
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 229
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 233
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 233
EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 235
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
PP
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
20.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 244
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C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
20.11.3 CAN - Controller area network interface . . . . . . . . . . . . . . . . . . . . . . . 249
20.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 250
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Device configuration and ordering information . . . . . . . . . . . . . . . . . 257
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Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
ROM device ordering information and transfer of customer code . . . . . 261
Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 266
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Safe connection of OSC1/OSC2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 267
Reset pin protection with LVD enabled . . . . . . . . . . . . . . . . . . . . . . . . 267
Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 271
SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 273
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C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Internal RC oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
I/O behavior during ICC mode entry sequence . . . . . . . . . . . . . . . . . . 274
Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Doc ID 17660 Rev 1 11/276
List of tables
List of tables
ST72521xx-Auto
12/276 Doc ID 17660 Rev 1
ST72521xx-Auto List of tables
Doc ID 17660 Rev 1 13/276
List of tables ST72521xx-Auto
Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes 213
PP
pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
14/276 Doc ID 17660 Rev 1
ST72521xx-Auto List of tables
2
C control interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Doc ID 17660 Rev 1 15/276
List of figures
List of figures
ST72521xx-Auto
DD
(AVDS bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
min
and t max
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16/276 Doc ID 17660 Rev 1
ST72521xx-Auto List of figures
Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 113
Abort with the software workaround - by NRTX, BUSY and LOCK . . . . . . . . . . . . . . . . . 202
CAN error state diagram showing “BUSOFF not entered” limitation . . . . . . . . . . . . . . . . 203
CPU
max versus V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
in Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
in Slow Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
versus T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
vs V
at V
DD
DD
with V
IN
= V
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
= 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
at V
DD
= 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Doc ID 17660 Rev 1 17/276
List of figures ST72521xx-Auto
at V
DD
= 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
versus V
DD
(standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
versus V
DD
(high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
- V
OH
versus V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 107. Two typical applications with ICCSEL/V
pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 111. Typical application with I
2
C BUS and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . 248
maximum versus f
ADC
with C
AIN
= 0pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
and R
AIN
values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
18/276 Doc ID 17660 Rev 1
ST72521xx-Auto
1 Description
Description
The ST72521xx-Auto Flash and ROM devices are members of the ST7 microcontroller family designed for mid-range automotive applications running from 3.8 to 5.5V.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.
The on-chip peripherals include an A/D converter, a PWM autoreload timer, two general purpose timers, I
2
C, SPI, SCI and CAN (controller area network) bus interfaces.
For power economy, the microcontroller can switch dynamically into Wait, Slow, Active Halt or Halt mode when the application is in idle or standby state.
Table 2.
Device summary
Reference Program memory RAM (stack) Voltage range Temp. range
ST72521M9-Auto
ST72521R9-Auto
ST72521AR9-Auto
ST72521R6-Auto
ST72521AR6-Auto
ST72521BM9-Auto
ST72521BR9-Auto
ST72521BAR9-Auto
ST72521BR6-Auto
ST72521BAR6-Auto
60 Kbytes Flash 2048 (256) bytes
32 Kbytes Flash 1024 (256) byte
60 Kbytes ROM 2048 (256) bytes
32 Kbytes ROM 1024 (256) byte
3.8V to 5.5V
Up to
-40°C to 125°C
Package
LQFP80 14x14
LQFP64 14x14
LQFP64 10x10
LQFP64 14x14
LQFP64 10x10
LQFP80 14x14
LQFP64 14x14
LQFP64 10x10
LQFP64 14x14
LQFP64 10x10
●
●
●
Typical applications include all types of car body applications such as window lift, DC motor control, rain sensors car body controllers, low end junction boxes auxiliary functions in car radios
Related documentation
Migrating applications from ST72511/311/314 to ST72521/321/324 (AN1131)
Doc ID 17660 Rev 1 19/276
Description
Figure 1.
Device block diagram
RESET
V
PP
TLI
V
SS
V
DD
EVD
OSC1
OSC2
PF7:0
(8-bits)
PE7:0
(8-bits)
PD7:0
(8-bits)
V
AREF
V
SSA
8-bit CORE
ALU
CONTROL
LVD
AVD
OSC
MCC/RTC/BEEP
PORT F
TIMER A
BEEP
PORT E
CAN
SCI
PORT D
10-bit ADC
PROGRAM
MEMORY
(32 or 60 Kbytes)
RAM
(1024 or 2048 bytes)
PORT G
(1)
PORT H
(1)
1.
On certain devices only (see
Section Table 3.: Device pin description on page 23 )
WATCHDOG
I2C
PORT A
PORT B
PWM ART
PORT C
TIMER B
SPI
ST72521xx-Auto
PA7:0
(8-bits)
PB7:0
(8-bits)
PC7:0
(8-bits)
PG7:0
(8-bits)
PH7:0
(8-bits)
20/276 Doc ID 17660 Rev 1
ST72521xx-Auto
2
Package pinout and pin description
Package pinout and pin description
Figure 2.
80-pin LQFP 14x14 package pinout
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
PG0
PG1
PG2
PG3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
14
15
16
17
18
9
10
11
12
13
19
20
3
4
1
2
5
6
7
8 ei2 ei3 ei1 ei0
48
47
46
45
52
51
50
49
44
43
42
41
60
59
58
57
56
55
54
53
V
SS_1
V
DD_1
PA3 (HS)
PA2
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK /ICCCLK
PH3
PH2
PH1
PH0
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
V
SS_0
V
DD_0
Doc ID 17660 Rev 1
(HS) 20mA high sink capability eix associated external interrupt vector
21/276
Package pinout and pin description
Figure 3.
64-pin LQFP 14x14 and 10x10 package pinout
ST72521xx-Auto
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2 47
3 46
4 45 ei0
5 44
6 43
7 ei2
42
8 41
9 40
10 39
11 ei3
38
12 37
13 36
14 35
15 ei1 34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
V
SS_1
V
DD_1
PA3 (HS)
PA2
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
V
SS_0
V
DD_0
(HS) 20mA high sink capability eix associated external interrupt vector
For external pin connection guidelines, refer to Section 20: Electrical characteristics
.
22/276 Doc ID 17660 Rev 1
ST72521xx-Auto Package pinout and pin description
Table 3.
No.
In the device pin description table, the RESET configuration of each pin is shown in bold.
This configuration is valid as long as the device is in reset state.
Refer to
Section 9: I/O ports on page 73 for more details on the software configuration of the
I/O ports.
Device pin description
Pin
Level
Name
Input
Port
Output
Main function
(after reset)
Alternate function
1
2
3
4
5
6
1
2
3
4
5
6
PE4 (HS)
PE5 (HS)
PE6 (HS)
PE7 (HS)
PB0/PWM3
PB1/PWM2
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
7
8
9
7
8
PB2/PWM1
PB3/PWM0
I/O C
T
I/O C
T
-
(1)
PG0 I/O T
T
HS X X
HS
HS
HS
X
X
X
X
X
X
X
X
X
X
X
X ei2 ei2 ei2 ei2
10
-
(1)
PG1 I/O T
T
X X
X
X
X
X
X
X
X
X
X
X
Port E4
X X Port E5
X X Port E6
X X Port E7
X X Port B0 PWM Output 3
X X Port B1
Port B2
Port B3
Port G0
Port G1
PWM Output 2
PWM Output 1
PWM Output 0
11
-
(1)
PG2 I/O T
T
12
-
(1)
PG3 I/O T
T
X
X
X
X
X
X
X
X
Port G2
Port G3
13 9 PB4 (HS)/ARTCLK
14 10 PB5/ARTIC1
15 11 PB6/ARTIC2
16 12 PB7
17 13 PD0 /AIN0
18 14 PD1/AIN1
19 15 PD2/AIN2
20 16 PD3/AIN3
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
T
21
-
(1)
PG6 I/O T
T
HS X
X
X
X
X
X
X
X
X
X
X
X
X
X ei3 ei3 ei3 ei3
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B4
Port B5
Port B6
Port B7
Port D0
Port G6
PWM-ART External Clock
PWM-ART Input Capture 1
PWM-ART Input Capture 2
ADC Analog Input 0
X X X Port D1 ADC Analog Input 1
X X X Port D2 ADC Analog Input 2
X X X Port D3 ADC Analog Input 3
22
-
(1)
PG7 I/O T
T
X X X X Port G7
Doc ID 17660 Rev 1 23/276
Package pinout and pin description
Table 3.
No.
Device pin description (continued)
Pin
Level
Name
Input
Port
Output
Main function
(after reset)
ST72521xx-Auto
Alternate function
23 17 PD4/AIN4
24 18 PD5/AIN5
25 19 PD6/AIN6
26 20 PD7/AIN7
27 21 V
AREF
(2)
28 22 V
SSA
(2)
29 23 V
DD_3
(2)
30 24 V
SS_3
(2)
I/O C
T
I/O C
T
I/O C
T
I/O
I
S
S
S
C
T
31
-
(1)
PG4 I/O T
T
32
-
(1)
PG5 I/O T
T
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port D4
Port D5
Port D6
Port D7
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
Analog Reference Voltage for ADC
Analog Ground Voltage
Digital Main Supply Voltage
Digital Ground Voltage
Port G4
Port G5
33 25 PF0/MCO/AIN8
34 26 PF1 (HS)/BEEP
35 27 PF2 (HS)
36 28 PF3/OCMP2_A/AIN9
37 29 PF4/OCMP1_A/AIN10
I/O C
T
I/O C
T
I/O C
T
HS X
HS X
I/O
I/O
C
C
T
T
X
X X
X X ei1 ei1 ei1
X X X Port F0
Main clock out (f
CPU
)
ADC Analog
Input 8
X X Port F1 Beep signal output
X X Port F2
X
X
X
X
X
X
Port F3
Port F4
Timer A
Output
Compare 2
Timer A
Output
Compare 1
ADC Analog
Input 9
ADC Analog
Input 10
38 30 PF5/ICAP2_A/AIN11
39 31 PF6 (HS)/ICAP1_A
40 32 PF7 (HS)/EXTCLK_A
41 33 V
DD_0
(2)
42 34 V
SS_0
(2)
43 35 PC0/OCMP2_B/AIN12
44 36 PC1/OCMP1_B/AIN13
I/O
I/O
I/O
S
S
I/O
I/O
C
C
C
C
C
T
T
T
T
T
HS
HS
X
X
X
X
X
X
X
X
X
X
X X X Port F5
Timer A Input
Capture 2
ADC Analog
Input 11
X X Port F6 Timer A Input Capture 1
X X Port F7
Timer A External Clock
Source
Digital Main Supply Voltage
X
X
X
X
X
X
Digital Ground Voltage
Port C0
Port C1
Timer B
Output
Compare 2
Timer B
Output
Compare 1
ADC Analog
Input 12
ADC Analog
Input 13
24/276 Doc ID 17660 Rev 1
ST72521xx-Auto Package pinout and pin description
Table 3.
No.
Device pin description (continued)
Pin
Level
Name
Input
Port
Output
Main function
(after reset)
Alternate function
45 37 PC2 (HS)/ICAP2_B
46 38 PC3 (HS)/ICAP1_B
47 39 PC4/MISO/ICCDATA
48 40 PC5/MOSI/AIN14
I/O
I/O
I/O
C
I/O C
C
C
T
T
T
T
HS
HS
X
X
X
X
X
X
X
X X
X X Port C2 Timer B Input Capture 2
X X Port C3 Timer B Input Capture 1
X
X
X
X
Port C4
Port C5
SPI Master
In / Slave Out
Data
ICC Data
Input
SPI Master
Out / Slave In
Data
ADC Analog
Input 14
49
-
(1)
PH0 I/O T
T
50
-
(1)
PH1 I/O T
T
51
-
(1)
PH2 I/O T
T
52
-
(1)
PH3 I/O T
T
53 41 PC6/SCK/ICCCLK
54 42 PC7/SS/AIN15
55 43 PA0
56 44 PA1
57 45 PA2
58 46 PA3 (HS)
59 47 V
DD_1
(2)
60 48 V
SS_1
(2)
61 49 PA4 (HS)
62 50 PA5 (HS)
63 51 PA6 (HS)/SDAI
64 52 PA7 (HS)/SCLI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port H0
Port H1
Port H2
Port H3
I/O
I/O
C
C
T
T
X
X
X
X
I/O C
T
I/O C
T
I/O C
T
I/O C
T
S
S
X
HS X
X
X
I/O C
T
I/O C
T
I/O C
T
I/O C
T
HS X X
HS
HS
X
X
HS X
X ei0 ei0 ei0 ei0
X
X
X
X
X
Port C6
Port C7
SPI Serial
Clock
ICC Clock
Output
Caution: Negative current injection not allowed on this pin (Flash devices only)
SPI Slave
Select (active low)
ADC Analog
Input 15
X X Port A0
X X Port A1
X X Port A2
X X Port A3
Digital Main Supply Voltage
Digital Ground Voltage
X X Port A4
X X Port A5
T Port A6 I
2
C Data
T Port A7 I
2
C Clock
Doc ID 17660 Rev 1 25/276
Package pinout and pin description
Table 3.
No.
Device pin description (continued)
Pin
Level
Name
Input
Port
Output
Main function
(after reset)
ST72521xx-Auto
Alternate function
65 53 V
PP
/ ICCSEL I
66 54 RESET
67 55 EVD
I/O C
T
I A
68 56 TLI I C
T
69
-
(1)
PH4 I/O T
T
70
-
(1)
PH5 I/O T
T
X
X X
X X
X
Must be tied low. In Flash programming mode, this pin acts as the programming voltage input V
PP
..
See
Section 20.9.2 on page 242 for
more details. High voltage must not be applied to ROM devices.
Top priority non-maskable interrupt
External voltage detector
Top level interrupt input pin
X X Port H4
X X Port H5
71
-
(1)
PH6 I/O T
T
X X X X Port H6
72
-
(1)
PH7 I/O T
T
X X X X Port H7
73 57 V
SS_2
(2)
74 58 OSC2
(3)
S
I/O
Digital Ground Voltage
Resonator oscillator inverter output
75 59 OSC1
(3)
I
External clock input or Resonator oscillator inverter input
76 60 V
DD_2
(2)
77 61 PE0/TDO
S Digital Main Supply Voltage
78 62 PE1/RDI
79 63 PE2/CANTX
I/O C
T
I/O C
T
I/O C
T
X
X
X
X
X
X
X
X
X
Port E0
Port E1
Port E2
SCI Transmit Data Out
SCI Receive Data In
CAN Transmit Data Output
80 64 PE3/CANRX I/O C
T
X X X X Port E3 CAN Receive Data Input
1.
On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption
2.
It is mandatory to connect all available V
DD
and V
AREF
pins to the supply voltage and all V
SS
and V
SSA
pins to ground.
3.
OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see
Multi-oscillator (MO) on page 41 and
Section 20.5: Clock and timing characteristics on page 228
for more details.
Legend / Abbreviations for Table 3
:
Type: I = input
O = output
S = supply
Input level: A = dedicated analog input
26/276 Doc ID 17660 Rev 1
ST72521xx-Auto Package pinout and pin description
In/Output level: C = CMOS 0.3V
DD
/0.7V
DD
C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
HS = 20mA high sink (on N-buffer only) Output level:
Port and control configuration:
●
●
Input: float = floating wpu = weak pull-up int = interrupt
(a) ana = analog open-drain
(b)
PP = push-pull a.
In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column
(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, otherwise the configuration is floating interrupt input.
b.
In the open-drain output column, “T” defines a true open-drain I/O (P-Buffer and protection diode to V
DD
are not
implemented). See Section 9: I/O ports on page 73
and
Section 20.8: I/O port pin characteristics on page 236
for more details.
Doc ID 17660 Rev 1 27/276
Register and memory map
3 Register and memory map
ST72521xx-Auto
As shown in
Figure 4 , the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of
RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Related documentation
Executing Code in ST7 RAM ( AN 985)
Figure 4.
Memory map
0000h
HW Registers
(see
007Fh
0080h
RAM
(2048 or 1024 Bytes)
087Fh
0880h
0FFFh
1000h
Reserved
Program Memory
(60K or 32K)
FFDFh
FFE0h
FFFFh
Interrupt & Reset Vectors
(see
)
0080h
Short Addressing
RAM (zero page)
00FFh
0100h
256 Bytes Stack
01FFh
0200h or 047Fh or 067Fh or 087Fh
16-bit Addressing
RAM
1000h
60 KBytes
8000h
32 KBytes
FFFFh
Table 4.
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
Hardware register map
Block Register label
Port A
Port B
Port C
Port D
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
Register name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Reset status Remarks
00h
(1)
00h
00h
00h
(1)
00h
00h
00h
(1)
00h
00h
00h
(1)
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
28/276 Doc ID 17660 Rev 1
ST72521xx-Auto Register and memory map
Table 4.
Address
Hardware register map (continued)
Block Register label Register name
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
Port E
Port F
Port G
2)
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
Port H
I
2
C
2)
SPI
ITC
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
0028h
0029h FLASH
002Ah WATCHDOG WDGCR
002Bh SICSR
002Ch
002Dh
MCC
MCCSR
MCCBCR
002Eh to
0030h
EICR
FCSR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
PGDR
PGDDR
PGOR
PHDR
PHDDR
PHOR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
Port G Data Register
Port G Data Direction Register
Port G Option Register
Port H Data Register
Port H Data Direction Register
Port H Option Register
I
2
C Control Register
I
2
C Status Register 1
I
2
C Status Register 2
I
2
C Clock Control Register
I
2
C Own Address Register 1
I
2
C Own Address Register2
I
2
C Data Register
Reserved Area (2 bytes)
Reset status Remarks
00h
(1)
00h
00h
00h
(1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
(2)
R/W
(2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Flash Control/Status Register
Watchdog Control Register
System Integrity Control/Status Register
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register xxh
0xh
00h
FFh
FFh
FFh
FFh
00h
00h
R/W
R/W
7Fh R/W
000x 000x b R/W
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved Area (3 bytes)
Doc ID 17660 Rev 1 29/276
Register and memory map ST72521xx-Auto
Table 4.
Address
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0058h
0059h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h to
006Fh
Hardware register map (continued)
Block Register label Register name
TIMER A
TIMER B
SCI
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
SCIETPR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Reserved Area (1 byte)
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
CAN
CANISR
CANICR
CANCSR
CANBRPR
CANBTR
CANPSR
Reserved Area (2 Bytes)
CAN Interrupt Status Register
CAN Interrupt Control Register
CAN Control / Status Register
CAN Baud Rate Prescaler Register
CAN Bit Timing Register
CAN Page Selection Register
First address to
Last address of CAN page x
Reset status Remarks
00h
00h xxxx x0xx b xxh xxh
80h
00h
FFh
FCh
FFh
FCh xxh xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
00h
00h xxxx x0xx b xxh xxh
80h
00h
FFh
FCh
FFh
FCh xxh xxh
80h
00h
C0h xxh
00h x000 0000b
00h
00h
---
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
23h
00h
--
R/W
R/W
R/W
R/W
R/W
R/W
See CAN
Descriptio n
30/276 Doc ID 17660 Rev 1
ST72521xx-Auto Register and memory map
Table 4.
Address
Hardware register map (continued)
Block Register label Register name Reset status Remarks
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
ADC
PWM ART
ADCCSR
ADCDRH
ADCDRL
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
Control/Status Register
Data High Register
Data Low Register
PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
Reserved Area (2 bytes)
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
1.
The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
2.
The bits associated with unavailable pins must always keep their reset value.
Note: Legend: x = undefined, R/W = read/write
Doc ID 17660 Rev 1 31/276
Flash program memory
4 Flash program memory
ST72521xx-Auto
4.1 Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external V
PP
supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.
●
●
●
●
3 Flash programming modes:
– Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.
– ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (in-application programming). In this mode, all sectors except Sector 0 can be programmed or erased without removing the device from the application board and while the application is running.
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
Readout protection
Register Access Security System (RASS) to prevent accidental programming or erasing
4.3 Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Table 5
). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.
Table 5.
Sectors available in Flash devices
Flash size (bytes)
4K
8K
> 8K
Available sectors
Sector 0
Sectors 0, 1
Sectors 0, 1, 2
The first two sectors have a fixed size of 4 Kbytes (see
Figure 5 ). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
32/276 Doc ID 17660 Rev 1
ST72521xx-Auto Flash program memory
Figure 5.
Memory map and sector address
4K 8K 10K 16K 24K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
32K 48K 60K
FLASH
MEMORY SIZE
SECTOR 2
2 Kbytes 8 Kbytes 16 Kbytes
4 Kbytes
4 Kbytes
24 Kbytes 40 Kbytes 52 Kbytes
SECTOR 1
SECTOR 0
Note:
Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
V
SS
:
ICCCLK: device power supply ground
ICC output serial clock pin
ICCDATA:
V
DD
:
ICC input/output serial data pin
ICCSEL/V
PP
OSC1 (or OSCIN): main clock input for external source (optional) application board power supply (optional, see
Note 3 )
Doc ID 17660 Rev 1 33/276
Flash program memory
Figure 6.
Typical ICC interface
ST72521xx-Auto
APPLICATION
POWER SUPPLY
PROGRAMMING TOOL
(See Note 3)
C
L2
OPTIONAL
(See Note 4)
C
L1
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
HE10 CONNECTOR TYPE
9 7 5 3
10 8 6 4
1
2
APPLICATION
RESET SOURCE
See Note 2
10k
See Note 1
APPLICATION
I/O
ST7
1.
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the programming tool documentation for recommended resistor values.
2.
During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push-pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical
RC network with R > 1K or a reset management IC with open-drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the
ICC session.
3.
The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.
4.
Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
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To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see
Figure 6 ). For more details on the pin locations, refer
to the device pinout description.
Doc ID 17660 Rev 1
ST72521xx-Auto Flash program memory
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.8
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual .
Flash control/status register (FCSR)
FSCR
7
0
RW
6
0
RW
5
0
RW
4
0
RW
3
0
RW
2
Reset value: 0000 0000 (00h)
1 0
0 0 0
RW RW RW
This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations.
Table 6.
Flash control/status register address and reset value
Address (Hex.) Register label 7 6 5 4 3
0029h
FCSR
Reset value 0 0 0 0 0
2
0
1
0
0
0
Doc ID 17660 Rev 1 35/276
Central processing unit (CPU)
5 Central processing unit (CPU)
ST72521xx-Auto
5.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
●
●
●
●
●
●
●
●
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power Halt and Wait modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
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The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
Figure 7.
CPU registers
7 0
Accumulator
Reset value = XXh
7 0
X index register
Reset value = XXh
7 0
Y index register
15 PCH 8
Reset value = XXh
7 PCL 0
Program counter
Reset value = reset vector @ FFFEh-FFFFh
7
1
Reset value = 1
1 I1 H I0 N Z
1 1 X 1 X X
0
C
X
15 8 7 0
Condition code register
Stack pointer
Reset value = stack higher address
X = undefined value
Doc ID 17660 Rev 1
ST72521xx-Auto Central processing unit (CPU)
5.3.2
5.3.3
The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations.
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
The 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
CC
7
1
6
1
5
I1
RW
4
H
RW
3
I0
RW
2
N
RW
Reset value: 111x1xxx
1 0
Z C
RW RW
Table 7.
Bit Name
Arithmetic management bits
Function
4
2
H
N
Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Doc ID 17660 Rev 1 37/276
Central processing unit (CPU)
5.3.5
ST72521xx-Auto
Table 7.
Bit Name
Arithmetic management bits
(continued)
Function
1
0
Z
C
Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Table 8.
Bit Name
Interrupt management bits
5
3
I1
I0
Function
Interrupt Software Priority 1
The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority 0
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 9.
Interrupt software priority selection
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Level
Low
High
I1
1
0
0
1
I0
0
1
0
1
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.
See
Chapter 7: Interrupts on page 52 for more details.
Stack pointer (SP) register
7
SP
15 14 13 12 11 10
0 0 0 0 0 0
9
0
8 7 6 5 4 3
Reset value: 01 FFh
2 1 0
1 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
RW RW RW RW RW RW RW RW
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ST72521xx-Auto
Note:
Central processing unit (CPU)
The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see
).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a reset stack pointer instruction (RSP), the stack pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by an LD instruction.
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. The other registers are then stored in the next locations as shown in
● When an interrupt is received, the SP is decremented and the context is pushed on the stack.
● On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 8.
Stack manipulation example
CALL
Subroutine
Interrupt
Event
PUSH Y
@ 0100h
POP Y IRET RET or RSP
SP
SP
@ 01FFh
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
Doc ID 17660 Rev 1 39/276
Supply, reset and clock management
6 Supply, reset and clock management
ST72521xx-Auto
6.1 Introduction
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 9
.
For more details, refer to the dedicated parametric section.
●
●
●
●
Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-oscillator Clock Management (MO)
– 5 crystal/ceramic resonator oscillators
– 1 internal RC oscillator
System Integrity Management (SI)
– Main supply low voltage detection (LVD)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin
Figure 9.
Clock, reset and supply block diagram
OSC2
OSC1
RESET
V
SS
V
DD
EVD
MULTI-
OSCILLATOR
(MO) f
OSC
PLL
(option)
RESET SEQUENCE
MANAGER
(RSM) f
OSC2
MAIN CLOCK
CONTROLLER
WITH REAL-TIME
CLOCK (MCC/RTC) f
CPU
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
SICSR
AVD AVD AVD LVD
S IE F RF
0 0 0
WDG
RF
WATCHDOG
TIMER (WDG)
0
1
LOW VOLTAGE
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
40/276 Doc ID 17660 Rev 1
ST72521xx-Auto Supply, reset and clock management
6.3 Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f
OSC2
of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f
OSC2
= f
OSC
/2.
Caution: The PLL is not recommended for applications where timing accuracy is required (see
Section 20.5.5: PLL characteristics on page 231
).
Figure 10.
PLL block diagram f
OSC
PLL x 2
/ 2
0
1
PLL OPTION BIT f
OSC2
●
●
●
The main clock of the ST7 can be generated by three different source types coming from the multi-oscillator block: an external source
4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in
. Refer to
Section 20: Electrical characteristics for more details.
Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an f
OSC
clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state. The product behavior must therefore be considered undefined when the OSC pins are left unconnected.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Doc ID 17660 Rev 1 41/276
Supply, reset and clock management ST72521xx-Auto
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to
Section 22.1.1: Flash configuration on page 257
for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time.
The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.
Internal RC oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
Table 10.
ST7 clock sources
Hardware configuration
OSC1
ST7
OSC2
EXTERNAL
SOURCE
OSC1
ST7
OSC2
C
L1
LOAD
CAPACITORS
C
L2
OSC1
ST7
OSC2
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ST72521xx-Auto Supply, reset and clock management
6.5 Reset sequence manager (RSM)
6.5.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 11 :
●
●
●
External RESET source pulse
Internal LVD RESET (low voltage detection)
Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
●
●
●
The basic RESET sequence consists of three phases as shown in Figure 12 :
Active phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by option byte)
RESET vector fetch
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see
Section 22.1.1: Flash configuration on page 257
).
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11.
Reset block diagram
V
DD
R
ON
RESET Filter
INTERNAL
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
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Supply, reset and clock management
Figure 12.
RESET sequence phases
ACTIVE PHASE
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
ST72521xx-Auto
FETCH
VECTOR
6.5.2
6.5.3
6.5.4
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
ON
weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
for more details.
A RESET signal originating from an external source must have a duration of at least t h(RSTL)in
in order to be recognized (see Figure 13
). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in
.
If the external RESET pulse is shorter than t w(RSTL)out
(see short ext. Reset in
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see long ext. Reset in
Figure 13 ). Starting from the external RESET pulse recognition, the
device RESET pin acts as an output that is pulled low during at least t w(RSTL)out
.
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V
DD
is over the minimum level specified for the selected f
OSC
frequency (see Section 20.3: Operating conditions on page 221
).
A proper reset signal for a slow rising V
DD
RC network connected to the RESET pin.
supply can generally be provided by an external
Internal low voltage detector (LVD) RESET
●
●
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
Power-on RESET
Voltage drop RESET
The device RESET pin acts as an output that is pulled low when V
DD
V
DD
< V
IT-
(falling edge) as shown in
.
< V
IT+
(rising edge) or
The LVD filters spikes on V
DD larger than t g(VDD) to avoid parasitic resets.
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The RESET sequence generated by an internal Watchdog counter overflow is shown in
.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out
.
Figure 13.
RESET sequences
V
DD
V
IT+(LVD)
V
IT-(LVD)
RUN
LVD
RESET
Active Phase
SHORT EXT.
RESET
RUN
Active
Phase
RUN
LONG EXT.
RESET
Active
Phase
RUN
WATCHDOG
RESET
Active
Phase
RUN t w(RSTL)out t h(RSTL)in t w(RSTL)out t h(RSTL)in
DELAY t w(RSTL)out
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
CPU
)
VECTOR FETCH
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Supply, reset and clock management
6.6
6.6.1
Note:
ST72521xx-Auto
System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the V
DD
supply voltage is below a V
IT-
reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
The V
IT-
reference value for a voltage drop is lower than the V
IT+
reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD reset circuitry generates a reset when V
DD
is below:
– V
IT+
when V
DD
is rising
– V
IT-
when V
DD
is falling
The LVD function is illustrated in Figure 14 .
The voltage threshold can be configured by option byte to be low, medium or high.
Provided the minimum V
DD
value (guaranteed for the oscillator frequency) is above V
MCU can only be in two modes:
IT-
, the
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
The LVD allows the device to be used without any external RESET circuitry.
If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.
The LVD is an optional function which can be selected by option byte.
It is recommended to make sure that the V
DD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.
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Figure 14.
Low voltage detector versus reset
V
DD
V
IT+
V
IT-
V hys
Supply, reset and clock management
RESET
6.6.2 Auxiliary voltage detector (AVD)
The auxiliary voltage detector function (AVD) is based on an analog comparison between a
V
IT-(AVD)
and V
IT+(AVD)
reference value and the V
DD
main supply or the external EVD pin voltage level (V
EVD
). The V
IT-
reference value for falling voltage is lower than the V
IT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator can be read directly by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only.
Caution: The AVD function is active only if the LVD is enabled through the option byte.
Monitoring the V
DD
main supply
This mode is selected by clearing the AVDS bit in the SICSR register.
The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see Section 22.1.1: Flash configuration on page 257 ).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V
IT+(AVD)
or V
IT-(AVD)
threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 15
.
The interrupt on the rising edge is used to inform the application that the V
DD
warning state is over.
If the voltage rise time t rv
is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V
IT+(AVD)
is reached.
If t rv
is greater than 256 or 4096 cycles
● two AVD interrupts will be received if the AVD interrupt is enabled before the V threshold is reached: the first when the AVDIE bit is set, and the second when the threshold is reached.
IT+(AVD)
● only one AVD interrupt will occur if the AVD interrupt is enabled threshold is reached.
after the V
IT+(AVD)
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Supply, reset and clock management ST72521xx-Auto
Figure 15.
Using the AVD to monitor V
DD
(AVDS bit = 0)
V
DD
Early Warning Interrupt
(Power has dropped, MCU not not yet in reset)
V hyst
V
IT+(AVD)
V
IT-(AVD)
V
IT+(LVD)
V
IT-(LVD) t rv VOLTAGE RISE TIME
1 RESET VALUE 1 0 AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
0
INTERRUPT PROCESS INTERRUPT PROCESS
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register.
●
●
The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This means it is generated when either one of these two events occur:
V
V
EVD
EVD
rises up to V
IT+(EVD)
falls down to V
IT-(EVD)
The EVD function is illustrated in
For more details, refer to Section 20: Electrical characteristics
.
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ST72521xx-Auto Supply, reset and clock management
Figure 16.
Using the voltage detector to monitor the EVD pin (AVDS bit = 1)
V
EVD
V hyst
V
IT+(EVD)
V
IT-(EVD)
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
0 1 0
INTERRUPT PROCESS INTERRUPT PROCESS
6.6.3 Low power modes
Table 11.
Effect of low power modes on SI
Mode Effect
Wait
Halt
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
6.6.4 Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 12.
AVD interrupt control/wake-up capability
Interrupt event Event flag Enable control bit Exit from Wait
AVD event AVDF AVDIE Yes
Exit from Halt
No
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Supply, reset and clock management
6.6.5
ST72521xx-Auto
System Integrity (SI) Control/Status register (SICSR)
SICSR
7
AVDS
RW
6
AVDIE
RW
5
AVDF
RW
4
LVDRF
RW
3
Reset value: 000x 000x (00h)
2 1 0
WDGRF Reserved
RW
Table 13.
Bit Name
SICSR description
Function
7
6
AVDS
AVDIE
Voltage Detection selection
This bit is set and cleared by software. Voltage Detection is available only if the
LVD is enabled by option byte.
0: Voltage detection on V
DD
supply
1: Voltage detection on EVD pin
Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
5
4
AVDF
LVDRF
Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to
Monitoring the VDD main supply on page 47 for additional details.
0: V
DD
or V
EVD
over V
IT+(AVD)
threshold
1: V
DD
or V
EVD
under V
IT-(AVD)
threshold
LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See Table 14: Reset source flags
for more details. When the LVD is disabled by OPTION BYTE, the
LVDRF bit value is undefined.
3:1 Reserved, must be kept cleared.
0 WDGRF
Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an
LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given in
.
Table 14.
Reset source flags
Reset sources
External RESET pin
Watchdog
LVD
LVDRF
0
0
1
WDGRF
0
1
X
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Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the
LVDRF flag remains set to keep trace of the original failure.
In this case, software can detect a watchdog reset but cannot detect an external reset.
Caution: When the LVD is not activated with the associated option byte, the WDGRF flag cannot be used in the application.
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Interrupts
7 Interrupts
ST72521xx-Auto
7.1 Introduction
The ST7 enhanced interrupt management provides the following features:
●
●
●
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non-maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI
●
●
●
This interrupt management is based on:
Bit 5 and bit 3 of the CPU CC register (I1:0)
Interrupt software priority registers (ISPRx)
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2
Note:
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see
15 ). The processing flow is shown in Figure 17 .
●
●
●
When an interrupt request has to be serviced:
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector.
● The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to
for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.
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Table 15.
Interrupt software priority levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Figure 17.
Interrupt processing flowchart
RESET
RESTORE PC, X, A, CC
FROM STACK
Level
Low
High
I1
1
0
0
1
Interrupts
PENDING
INTERRUPT
N
FETCH NEXT
INSTRUCTION
Y
Interrupt has the same or a lower software priority than current one
TRAP
N
I1:0
THE INTERRUPT
STAYS PENDING
Y
Y
“IRET”
N
EXECUTE
INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
I0
0
1
0
1
Servicing pending interrupts
●
●
As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.
describes this decision process.
Figure 18.
Priority decision process flowchart
PENDING
INTERRUPTS
Same
SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
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Interrupts ST72521xx-Auto
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.
Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.
2 TLI, RESET and TRAP can be considered as having the highest software priority in the decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 17 ). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode.
● TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 17 .
Caution: TRAP can be interrupted by a TLI.
● RESET
The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority.
See
Section 6.5: Reset sequence manager (RSM) on page 43
for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
● TLI (top level hardware interrupt)
Caution: This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It
will be serviced according to the flowchart in Figure 17
as a trap.
A TRAP instruction must not be used in a TLI service routine.
● External Interrupts
External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.
● Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those mentioned in
. A peripheral interrupt occurs when a specific
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Note:
Interrupts flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be serviced) will therefore be lost if the clear sequence is executed.
7.3
Note:
7.4
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column “Exit from Halt/Active Halt” in
). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with “exit from Halt mode” capability and it is selected through the same decision process
.
If an interrupt that is not able to exit from Halt mode is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced.
Concurrent and nested management
Figure 20 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 20 . The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
Figure 19.
Concurrent interrupt management
RIM
MAIN
11 / 10
IT2
IT1
TRAP
IT1
IT0
IT3
IT4
SOFTWARE
PRIORITY
LEVEL
I1
3
3
3
3
3
3
3/0
1 1
1 1
1 1
1 1
1 1
1 1
I0
10
MAIN
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Interrupts
Figure 20.
Nested interrupt management
ST72521xx-Auto
RIM
MAIN
11 / 10
IT2
IT1
SOFTWARE
PRIORITY
LEVEL
IT4
TRAP
IT4
IT0
IT3
IT1
IT2
10
MAIN
I1
3
3
3
3
2
1
3/0
1 1
1 1
0 0
0 1
1 1
1 1
I0
7.5.1 CPU CC register interrupt bits
CPU CC
7
1
6
1
5
I1
RW
4
H
RW
3
I0
RW
2
Reset value: 111x 1010 (xAh)
1 0
N Z C
RW RW RW
Table 16.
CPU CC register interrupt bits description
Bit Name Function
5
3
I1
I0
Interrupt Software Priority 1
Interrupt Software Priority 0
These two bits indicate the current interrupt software priority (see Table 17
) and are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
Table 19: Interrupt dedicated instruction set ).
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Table 17.
Interrupt software priority levels
Interrupt software priority Level
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable
(1)
)
1.
TLI, TRAP and RESET events can interrupt a level 3 program.
Low
High
I1
1
0
0
1
Interrupts
I0
0
1
0
1
These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read only.
ISPRx
ISPR0
ISPR1
ISPR2
ISPR3
7
I1_3
I1_7
I1_11
1
6
I0_3
I0_7
I0_11
1
5
I1_2
I1_6
I1_10
1
4
I0_2
I0_6
I0_10
1
3
I1_1
I1_5
I1_9
I1_13
Reset value: 1111 1111 (FFh)
2 1 0
I0_1 I1_0 I0_0
I0_5 I1_4 I0_4
I0_9
I0_13
I1_8
I1_12
I0_8
I0_12
These four registers contain the interrupt software priority of each interrupt vector.
● Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following
Table 18.
Interrupt priority bits
Vector address
FFFBh-FFFAh
FFF9h-FFF8h
...
FFE1h-FFE0h
ISPRx bits
I1_0 and I0_0 bits
(1)
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
1.
Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management.
●
●
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h).
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Interrupts ST72521xx-Auto
The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the
I1 and I0 bits of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 19.
Interrupt dedicated instruction set
Instruction New description Function/Example
HALT
IRET
JRM
Entering Halt mode
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Pop CC, A, X, PC
I1:0 = 11 ?
JRNM Jump if I1:0 <> 11
POP CC Pop CC from the Stack
RIM
I1:0 <> 11 ?
Mem => CC
Enable interrupt (level 0 set) Load 10 in I1:0 of CC
SIM
TRAP
WFI
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
Software trap Software NMI
Wait for interrupt
I1 H I0 N Z C
1 0
I1 H I0 N Z C
1
1
1
I1 H I0 N Z C
1 0
1
1
0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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Table 20.
Interrupt mapping
No.
Source block
Description
Register label
Priority order
Exit from
Halt /
Active
Halt
(1)
0
1
2
5
6
3
4
7
RESET Reset
TRAP
TLI
Software interrupt
External top level interrupt
MCC/RTC Main clock controller time base interrupt ei0 External interrupt port A3..0
ei1 ei2 ei3
CAN
SPI
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
CAN peripheral interrupts
SPI peripheral interrupts
N/A
EICR
MCCSR
N/A
CANISR
SPICSR
Higher priority yes no yes yes yes yes yes yes yes yes
(2)
8
9
10
TIMER A TIMER A peripheral interrupts
TIMER B TIMER B peripheral interrupts
SCI SCI peripheral interrupts
TASR
TBSR
SCISR no no no
Lower priority
11
12
AVD
I2C
Auxiliary voltage detector interrupt
I2C peripheral interrupts
SICSR
(see peripheral) no no
13 PWM ART PWM ART interrupt ARTCSR yes
(3)
1.
In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
2.
Exit from HALT possible when SPI is in slave mode.
3.
Exit from HALT possible when PWM ART is in external clock mode.
Address vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
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Interrupts ST72521xx-Auto
7.6.1 I/O interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (
). This control allows to have up to four fully independent external interrupt source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
●
●
●
●
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR.
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Figure 21.
External interrupt control bits
PORT A [3:0] INTERRUPTS EICR
IS20 IS21
PAOR.3
PADDR.3
PA3
SENSITIVITY
CONTROL
IPA BIT
PA3
PA2
PA1
PA0
PORT F [2:0] INTERRUPTS
PFOR.2
PFDDR.2
PF2
EICR
IS20 IS21
SENSITIVITY
CONTROL
PF2
PF1
PF0
PORT B [3:0] INTERRUPTS
PBOR.3
PBDDR.3
PB3
IPB BIT
PORT B [7:4] INTERRUPTS
PBOR.7
PBDDR.7
PB7
EICR
IS10 IS11
SENSITIVITY
CONTROL
PB3
PB2
PB1
PB0
EICR
IS10 IS11
SENSITIVITY
CONTROL
PB7
PB6
PB5
PB4
Interrupts ei0 INTERRUPT SOURCE ei1 INTERRUPT SOURCE ei2 INTERRUPT SOURCE ei3 INTERRUPT SOURCE
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Interrupts ST72521xx-Auto
EICR
7
IS1[1:0]
RW
6 5
IPB
RW
4
IS2[1:0]
RW
3 2
IPA
RW
Reset value: 0000 0000 (00h)
1
TLIS
RW
0
TLIE
RW
Table 21.
EICR register description
Bit Name Function
7:6 IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts:
- ei2 (port B3..0) (see Table 22 )
- ei3 (port B7..4) (see Table 23 )
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
5 IPB
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
4:3 IS2[1:0]
2 IPA ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:
- ei0 (port A3..0) (see Table 24 )
- ei1 (port F2..0) (see Table 25 )
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
1
0
TLIS
TLIE
TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared.
0: Falling edge
1: Rising edge
TLI enable
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software.
0: TLI disabled
1: TLI enabled
Note: A parasitic interrupt can be generated when clearing the TLIE bit.
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Table 22.
Interrupt sensitivity - ei2 (port B3..0)
External interrupt sensitivity
IS11 IS10
IPB bit = 0 IPB bit = 1
1
1
0
0
0
1
0
1
Falling edge and low level
Rising edge only
Rising edge and high level
Falling edge only
Falling edge only
Rising and falling edge
Rising edge only
Table 23.
Interrupt sensitivity - ei3 (port B7..4)
IS11 IS10 External interrupt sensitivity
1
1
0
0
0
1
0
1
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
Table 24.
Interrupt sensitivity - ei0 (port A3..0)
External interrupt sensitivity
IS21 IS20
IPA bit = 0 IPA bit = 1
0
0
1
1
0
1
0
1
Falling edge and low level
Rising edge only
Falling edge only
Rising edge and high level
Rising and falling edge
Falling edge only
Rising edge only
Table 25.
Interrupt sensitivity - ei1 (port F2..0)
IS21 IS20 External interrupt sensitivity
0
0
1
1
0
1
0
1
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
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Interrupts ST72521xx-Auto
Table 26.
Nested interrupts register map and reset values
Address (Hex.) Register label 7 6 5 4
0024h
0025h
0026h
ISPR0
Reset value
ISPR1
Reset value
ISPR2
Reset value ei1
I1_3
1
I0_3
1
SPI
I1_7
1
I0_7
1
I1_11
1
AVD
I0_11
1 ei0
I1_2
1
I0_2
1
CAN
I1_6
1
I0_6
1
I1_10
1
SCI
I0_10
1
0027h
0028h
ISPR3
Reset value
EICR
Reset value
1
IS11
0
1
IS10
0
1
IPB
0
1
IS21
0
3 2
MCC
I1_1
1
I0_1
1 ei3
I1_5
1
I0_5
TIMER B
1
I1_9
1
I0_9
1
PWMART
I1_13
1
I0_13
1
IS20
0
IPA
0
1
TLI
0
1 1 ei2
I1_4
1
I0_4
TIMER A
1
I1_8
1
I0_8
1
I2C
I1_12
1
TLIS
0
I0_12
1
TLIE
0
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ST72521xx-Auto Power saving modes
8.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 22 ): Slow, Wait (Slow
Wait), Active Halt and Halt.
After a RESET the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (f
OSC2
).
From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.
Figure 22.
Power saving mode transitions
High
RUN
SLOW
WAIT
SLOW WAIT
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
Note:
This mode has two targets:
●
●
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f
CPU
) to the available supply voltage.
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f
CPU
).
In this mode, the master clock frequency (f
OSC2
) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (f
CPU
).
Slow Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
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Power saving modes
Figure 23.
Slow mode clock transitions f
OSC2/2 f
CPU f
OSC2
CP1:0
SMS
00 01 f
OSC2/4
NEW SLOW
FREQUENCY
REQUEST
NORMAL RUN MODE
REQUEST
ST72521xx-Auto f
OSC2
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.
Refer to the following
.
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Figure 24.
Wait mode flowchart
Power saving modes
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
N
N
RESET
Y
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
10
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX
(1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1.
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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Power saving modes ST72521xx-Auto
8.4 Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register) as shown in Table 27
.
Table 27.
MCC/RTC low power mode selection
MCCSR OIE bit Power saving mode entered when HALT instruction is executed
0
1
Halt
Active Halt
8.4.1 Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see
Section 12.3: ART registers on page 96 for
more details on the MCCSR register).
The MCU can exit Active Halt mode on reception of an MCC/RTC interrupt or a RESET. In
ROM devices, external interrupts can be used to wake up the MCU. When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see
).
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering Active Halt mode while the Watchdog is active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving mode.
Caution: When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register must not be cleared before t
DELAY
after the interrupt occurs (t
DELAY
= 256 or 4096 t
CPU delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining t
DELAY period.
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Figure 25.
Active Halt timing overview
RUN
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
(1)
HALT
INSTRUCTION
[MCCSR.OIE = 1]
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
Power saving modes
1.
This delay occurs only if the MCU exits Active Halt mode by means of a RESET.
Figure 26.
Active Halt mode flowchart
HALT
N
INSTRUCTION
(MCCSR.OIE = 1)
INTERRUPT
(3)
Y
OSCILLATOR
PERIPHERALS
(1)
CPU
I[1:0] BITS
ON
OFF
OFF
10
N
RESET
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX
(2)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX
(2)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1.
Peripheral clocked with an external clock source can still be active.
2.
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
3.
In Flash devices only the MCC/RTC interrupt can exit the MCU from Active Halt mode.
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Power saving modes ST72521xx-Auto
The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see
The MCU can exit Halt mode on reception of either a specific interrupt (see
20.: Interrupt mapping on page 59
) or a RESET. When exiting Halt mode by means of a
RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see
).
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’ option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 22.1.1: Flash configuration on page 257
for more details).
Figure 27.
Halt timing overview
RUN HALT
HALT
INSTRUCTION
[MCCSR.OIE = 0]
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
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Figure 28.
Halt mode flowchart
Power saving modes
HALT INSTRUCTION
(MCCSR.OIE = 0)
ENABLE
0
WDGHALT
(1)
1
WATCHDOG
RESET
WATCHDOG
DISABLE
OSCILLATOR
PERIPHERALS
(2)
CPU
I[1:0] BITS
OFF
OFF
OFF
10
N
N
RESET
Y
INTERRUPT
(3)
Y OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX
(4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX
(4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1.
WDGHALT is an option bit. See Section 22.1.1: Flash configuration on page 257 for more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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Power saving modes ST72521xx-Auto
Halt mode recommendations
●
●
●
●
●
Make sure that an external event is available to wake up the microcontroller from Halt mode.
When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
Related documentation
ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke (AN 980)
How to Minimize the ST7 Power Consumption (AN1014)
Using an active RC to wake up the ST7LITE0 from power saving mode (AN1605)
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ST72521xx-Auto I/O ports
9.1 Introduction
The I/O ports offer different functional modes:
● transfer of data through digital inputs and outputs
●
● and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals.
An I/O port contains up to eight pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.
Each port has two main registers:
●
●
Data Register (DR)
Data Direction Register (DDR) and one optional register:
● Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers (bit X corresponding to pin X of the port). The same correspondence is used for the DR register.
The following description takes into account the OR register (for specific ports which do not provide this register refer to
Section 9.3: I/O port implementation on page 77 ). The generic
I/O block diagram is shown in
.
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.
2 When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.
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I/O ports ST72521xx-Auto
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.
The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. The DR register value and output pin status are shown in the following
.
Table 28.
I/O output mode selection
DR Push-pull
0
1
V
SS
V
DD
Open-drain
V
SS
Floating
Note:
When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open-drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.
Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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Figure 29.
I/O port general block diagram
REGISTER
ACCESS
ALTERNATE
OUTPUT
1
0
ALTERNATE
ENABLE
DR
DDR
OR
OR SEL
If implemented
PULL-UP
CONDITION
I/O ports
V
DD
P-BUFFER
(see table below)
PULL-UP
(see table below)
V
DD
PAD
N-BUFFER
DDR SEL
DIODES
(see table below)
ANALOG
INPUT
DR SEL
1
0
CMOS
SCHMITT
TRIGGER
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei x
)
Table 29.
I/O port mode options
Diodes
Configuration mode Pull-up P-buffer to V
DD to V
SS
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open-drain (logic level)
True open-drain
Off
On
Off
Off
On
Off
NI
On
On
NI NI
(1)
1.
The diode to V
DD
V
SS
is not implemented in the true open-drain pads. A local protection between the pad and
is implemented to protect the device against positive stress.
Legend:
Off - Implemented not activated
On - Implemented and activated
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I/O ports
Table 30.
I/O port configurations
ST72521xx-Auto
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PU
PAD
Hardware configuration
PULL-UP
CONDITION
DR REGISTER ACCESS
DR
REGISTER
W
R
DATA BUS
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei x
)
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PU
PAD
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PU
PAD
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
1.
When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.
2.
When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.
Warning: The analog input voltage level must be within the limits stated in the absolute maximum ratings.
9.3 I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open-drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 30 .
Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 30.
Interrupt I/O port state transitions
01 00
INPUT floating/pull-up interrupt
INPUT floating
(reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX = DDR, OR
The I/O port register configurations are summarized in the following table.
Table 31.
I/O port configuration
Input (DDR = 0)
Port Pin name
OR = 0 OR = 1
PA7:6
Port A
PA5:4
PA3
PA2:0 floating floating floating floating pull-up floating interrupt pull-up interrupt
Output (DDR = 1)
OR = 0 OR = 1 true open-drain open-drain push-pull open-drain open-drain push-pull push-pull
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I/O ports ST72521xx-Auto
Table 31.
I/O port configuration (continued)
Input (DDR = 0)
Port Pin name
OR = 0 OR = 1
Output (DDR = 1)
OR = 0
Port F
PB7, PB3
Port B
PB6:5, PB4, PB2:0
Port C PC7:0
Port D PD7:0
PE7:3, PE1:0
Port E
PE2
PF7:3
PF2
PF1:0
Port G PG7:0
Port H PH7:0 floating floating floating floating floating floating floating floating floating floating floating interrupt pull-up interrupt pull-up pull-up open-drain open-drain open-drain open-drain pull-up open drain
pull-up input only
(1) pull-up floating interrupt pull-up interrupt pull-up pull-up open-drain open-drain open-drain open drain open drain
1.
When the CANTX alternate function is selected the I/O port operates in output push-pull mode.
OR = 1 push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull
9.4 Low power modes
Table 32.
Effect of low power modes on I/O ports
Mode Effect
Wait
Halt
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
9.5 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 33.
I/O port interrupt control/wake-up capability
Interrupt event Event flag
Enable control bit
External interrupt on selected external event
DDRx, ORx
Exit from
Wait
Yes
Exit from
Halt
Yes
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Table 34.
I/O port register map and reset values
Address (Hex.) Register label 7 6 5 4
Reset value of all I/O port registers
0008h
0009h
000Ah
000Bh
000Ch
000Dh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
PGDR
PGDDR
PGOR
PHDR
PHDDR
PHOR
0
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
0 0
Related documentation
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Watchdog timer (WDG)
10 Watchdog timer (WDG)
ST72521xx-Auto
10.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
●
●
●
●
●
Programmable free-running downcounter
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware Watchdog selectable by option byte
The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 f
OSC2
cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (bits
T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the
RESET pin low for typically 30µs.
The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: It counts down even if the watchdog is disabled. The value to be stored in the WDGCR register must be between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments which represents the time delay
unknown status of the prescaler when writing to the WDGCR register (see
).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
80/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 31.
Watchdog block diagram
MCC/RTC f
OSC2
DIV 64
RESET
Watchdog timer (WDG)
WDGA T6
WATCHDOG CONTROL REGISTER (WDGCR)
T5 T4 T3 T2 T1
6-BIT DOWNCOUNTER (CNT)
T0
11
12-BIT MCC
RTC COUNTER
MSB LSB
6 5 0
TB[1:0] bits
(MCCSR
Register)
WDG PRESCALER
DIV 4
10.4 How to program the watchdog timeout
shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in
.
Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.
Figure 32.
Approximate timeout duration
3F
38
30
28
20
18
10
08
00
1.5
18 34 50 65 82
Watchdog timeout (ms) @ 8 MHz f
OSC2
98 114 128
Doc ID 17660 Rev 1 81/276
Watchdog timer (WDG) ST72521xx-Auto
Figure 33.
Exact timeout duration (t min
and t max
)
WHERE : t min0
= (LSB + 128) x 64 x t
OSC2 t max0
= 16384 x t
OSC2 t
OSC2
= 125ns if f
OSC2
= 8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register
TB1 bit
(MCCSR reg.)
0
0
1
1
TB0 bit
(MCCSR reg.)
0
1
0
1
Selected MCCSR timebase
2ms
4ms
10ms
25ms
MSB LSB
4
8
20
49
59
53
35
54
To calculate the minimum Watchdog Timeout (t min
):
IF CNT <
4
THEN t min
= t min0
+ 16384
CNT
t osc2
ELSE t min
= t min0
+ 16384
CNT –
MSB
+
192 + LSB
64
MSB
t osc2
To calculate the maximum Watchdog Timeout (t max
):
IF CNT
4
THEN t max
= t max0
+ 16384
CNT
t osc2
ELSE t max
= t max0
+ 16384
CNT –
MSB
+
192 + LSB
64
MSB
t osc2
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Value of T[5:0] bits in
WDGCR register (Hex.)
00
3F
Min. Watchdog
Timeout (ms) t min
1.496
128
Max. Watchdog
Timeout (ms) t max
2.048
128.552
82/276 Doc ID 17660 Rev 1
ST72521xx-Auto Watchdog timer (WDG)
10.5 Low power modes
Table 35.
Effect of low power modes on WDG
Mode Effect
Slow No effect on Watchdog
Wait No effect on Watchdog
OIE bit in
MCCSR register
WDGHALT bit in
Option
Byte
Halt
0
0
1
0
1 x
No Watchdog reset is generated. The MCU enters Halt mode.
The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware
Watchdog is selected by option byte. For application
recommendations see Section 10.7
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The
Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or
4096 CPU clocks.
10.6 Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 22.1.1:
Flash configuration on page 257 .
10.7 Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
10.8 Interrupts
None.
Doc ID 17660 Rev 1 83/276
Watchdog timer (WDG) ST72521xx-Auto
10.9.1 Control register (WDGCR)
WDGCR
7
WDGA
RW
6 5 4 3
T[6:0]
RW
2
Reset value: 0111 1111 (7Fh)
1 0
Table 36.
WDGCR register description
Bit Name Function
7 WDGA
Activation bit
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
6:0 T[6:0]
7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every 16384 f
OSC2
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Table 37.
Watchdog timer register map and reset values
Address
(Hex.)
Register label
7 6 5 4 3
002Ah
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
2
T2
1
1
T1
1
0
T0
1
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ST72521xx-Auto
11
Main clock controller with real-time clock and beeper (MCC/RTC)
Main clock controller with real-time clock and beeper
(MCC/RTC)
11.1 Introduction
●
●
The Main Clock Controller consists of three different functions:
● a programmable CPU clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
11.2 Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages Slow power saving mode (see
Section 8.2: Slow mode on page 65
for more details).
The prescaler selects the f
CPU
main clock frequency and is controlled by three bits in the
MCCSR register: CP[1:0] and SMS.
11.3 Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a f
CPU drive external devices. It is controlled by the MCO bit in the MCCSR register.
clock to
Caution: When selected, the clock out pin suspends the clock during Active Halt mode.
11.4 Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. Four different time bases depending directly on f
OSC2
are available.
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the
HALT instruction is executed. See
Section 8.4: Active Halt and Halt modes on page 68 for
more details.
11.5 Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function).
Doc ID 17660 Rev 1 85/276
Main clock controller with real-time clock and beeper (MCC/RTC)
Figure 34.
Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
BEEP SIGNAL
SELECTION f
OSC2
ST72521xx-Auto
BEEP
MCO
DIV 64
12-BIT MCC RTC
COUNTER
TO
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
DIV 2, 4, 8, 16 1
0
MCC/RTC INTERRUPT f
CPU
CPU CLOCK
TO CPU AND
PERIPHERALS
11.6 Low power modes
Table 38.
Effect of low power modes on MCC/RTC
Mode Effect
Wait
Active Halt
Halt
No effect on MCC/RTC peripheral.
MCC/RTC interrupt causes the device to exit from Wait mode.
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt causes the device to exit from Active Halt mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the MCU is woken up by an interrupt with
“exit from HALT” capability.
11.7 Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Table 39.
MCC/RTC interrupt control/wake-up capability
Interrupt event Event flag
Enable control bit
Exit from
Wait
Time base overflow event OIF OIE Yes
1.
The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.
Exit from
Halt
No
(1)
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ST72521xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)
11.8 Main clock controller registers
11.8.1 MCC control/status register (MCCSR)
MCCSR
7
MCO
RW
6
CP[1:0]
RW
5 4
SMS
RW
3
TB[1:0]
RW
2
Reset value: 0000 0000 (00h)
1 0
OIE OIF
RW RW
Table 40.
MCCSR register description
Bit Name Function
7 MCO
Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (f
CPU on I/O port)
Note: To reduce power consumption, the MCO function is not active in Active Halt mode.
6:5 CP[1:0]
CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software.
00: f
CPU
in Slow mode = f
OSC2
/2
01: f
CPU
in Slow mode = f
OSC2
/4
10: f
CPU
in Slow mode = f
OSC2
/8
11: f
CPU
in Slow mode = f
OSC2
/16
4 SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
CPU
= f
OSC2
1: Slow mode. f
CPU
is given by CP1, CP0
See Section 8.2: Slow mode on page 65
and Chapter 11: Main clock controller with real-time clock and beeper (MCC/RTC)
for more details.
3:2 TB[1:0]
Time base control
These bits select the programmable divider time base. They are set and cleared by software (see
).
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base as a real-time clock.
1 OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active Halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active Halt power saving mode.
Doc ID 17660 Rev 1 87/276
Main clock controller with real-time clock and beeper (MCC/RTC) ST72521xx-Auto
Table 40.
MCCSR register description (continued)
Bit Name Function
0 OIF
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution : The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.
Table 41.
Time base selection
Time base
Counter prescaler TB1 TB0
16000
32000
80000
200000 f
OSC2
= 4 MHz
4ms
8ms
20ms
50ms f
OSC2
= 8 MHz
2ms
4ms
10ms
25ms
0
0
1
1
0
1
0
1
11.8.2 MCC beep control register (MCCBCR)
MCCBCR
7 6 5
Reserved
-
4 3 2
Reset value: 0000 0000 (00h)
1 0
BC[1:0]
RW
Table 42.
MCCBCR register description
Bit Name Function
7:2 Reserved, must be kept cleared.
1:0 BC[1:0]
Beep control
These 2 bits select the PF1 pin beep capability (see
).
Table 43.
Beep frequency selection
BC1 BC0
0
0
1
1
0
1
0
1
Beep mode with f
OSC2
= 8 MHz
Off
~2 kHz
~1 kHz
~500 Hz
Output
Beep signal
~50% duty cycle
The beep output signal is available in Active Halt mode but has to be disabled to reduce consumption.
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ST72521xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)
Table 44.
Main clock controller register map and reset values
Address (Hex.) Register label 7 6 5 4
002Bh
002Ch
002Dh
SICSR
Reset value
MCCSR
Reset value
MCCBCR
Reset value
AVDS
0
MCO
0
0
AVDIE
0
CP1
0
0
AVDF
0
CP0
0
0
LVDRF x
SMS
0
0
3
0
TB1
0
0
2
0
TB0
0
0
1
0
OIE
0
BC1
0
0
WDGRF x
OIF
0
BC0
0
Doc ID 17660 Rev 1 89/276
PWM auto-reload timer (ART)
12 PWM auto-reload timer (ART)
ST72521xx-Auto
12.1 Introduction
The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit autoreload counter with compare/capture capabilities and of a 7-bit prescaler clock source.
These resources allow five possible operating modes:
●
●
●
●
●
Generation of up to 4 independent PWM signals
Output compare and Time base interrupt
Up to 2 input capture functions
External event detector
Up to 2 external interrupt sources
The three first modes can be used together with a single counter frequency.
The timer can be used to wake up the MCU from Wait and Halt modes.
Figure 35.
PWM auto-reload timer block diagram
PWMx
PWMCR OEx
PORT
ALTERNATE
FUNCTION
OPx
POLARITY
CONTROL
OCRx
REGISTER
LOAD
COMPARE
DCRx
REGISTER
ARR
REGISTER
8-BIT COUNTER
(CAR REGISTER)
LOAD
ARTICx
INPUT CAPTURE
CONTROL
LOAD ICRx
REGISTER
ARTCLK
ICSx ICIEx ICFx ICCSR
ICx INTERRUPT f
EXT f
CPU f
COUNTER
MUX f
INPUT PROGRAMMABLE
PRESCALER
EXCL CC2 CC1 CC0 TCE FCRL OIE OVF ARTCSR
OVF INTERRUPT
90/276 Doc ID 17660 Rev 1
ST72521xx-Auto PWM auto-reload timer (ART)
12.2.1 Counter
The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal.
It is possible to read or write the contents of the counter on the fly by reading or writing the
Counter Access register (ARTCAR).
When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected).
12.2.2 Counter clock and prescaler
The counter clock frequency is given by: f
COUNTER
= f
INPUT
/ 2
CC[2:0]
The timer counter’s input clock (f
INPUT
) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the
Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2 n
(where n = 0, 1,..7).
This f
INPUT
frequency source is selected through the EXCL bit of the ARTCSR register and can be either the f
CPU
or an external input frequency f
EXT
.
The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the
ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source.
12.2.3 Counter and prescaler initialization
After RESET, the counter and the prescaler are cleared and f
INPUT
= f
CPU
.
The counter can be initialized by:
● writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR register
● writing to the ARTCAR counter access register
In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
12.2.4 Output compare control
The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.
This double buffering method avoids glitch generation when changing the duty cycle on the fly.
Doc ID 17660 Rev 1 91/276
PWM auto-reload timer (ART)
Figure 36.
Output compare control f
COUNTER
COUNTER FDh
OCRx
PWMDCRx
FEh
ARTARR = FDh
FFh FDh
FDh
FDh
PWMx
FEh
ST72521xx-Auto
FFh
FEh
FDh
FEh
FEh FFh
Note:
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during Halt mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function.
The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value.
f
PWM
= f
COUNTER
/ (256 - ARTARR)
When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored.
It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the
OCRx register must be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 / (256 - ARTARR)
To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.
92/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 37.
PWM auto-reload timer function
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
000
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 38.
PWM signal from 0% to 100% duty cycle f
COUNTER
ARTARR = FDh
COUNTER
FDh FEh FFh FDh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
FEh
PWM auto-reload timer (ART)
FFh FDh FEh t t
On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application.
12.2.7 External clock and event detector mode
Using the f
EXT
external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the n
EVENT
number of events to be counted before setting the OVF flag.
n
EVENT
= 256 - ARTARR
Caution: The external clock function is not available in Halt mode. If Halt mode is used in the application, prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the ARTCSR register to avoid spurious counter increments.
Doc ID 17660 Rev 1 93/276
PWM auto-reload timer (ART)
Figure 39.
External event detector example (3 counts) f
EXT
= f
COUNTER
ARTARR = FDh
COUNTER
FDh
OVF
FEh FFh FDh FEh FFh FDh
ST72521xx-Auto
INTERRUPT
IF OIE = 1
ARTCSR READ
INTERRUPT
IF OIE = 1
ARTCSR READ t
Note:
Note:
This mode allows the measurement of external signal pulse widths through ARTICRx registers.
Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture
Control/Status register (ARTICCSR).
These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register.
The read only input capture registers (ARTICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register).
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
After a capture detection, data transfer in the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled
(CIEx bit set). This means that the ARTICRx register has to be read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload counter cycle time (1/f
COUNTER
).
During Halt mode, if both the input capture and the external clock are enabled, the ARTICRx register value is not guaranteed if the input capture pin and the external clock change simultaneously.
94/276 Doc ID 17660 Rev 1
ST72521xx-Auto PWM auto-reload timer (ART)
This mode allows the input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal.
The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR register) and they are independently enabled through CIEx bits of the ARTICCSR register.
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
During Halt mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set).
Figure 40.
Input capture timing diagram f
COUNTER
COUNTER
01h
ARTICx PIN
CFx FLAG
ICRx REGISTER
02h 03h xxh
04h 05h 06h
INTERRUPT
07h
04h t
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PWM auto-reload timer (ART) ST72521xx-Auto
96/276
ARTCSR
7
EXCL
RW
6 5
CC[2:0]
RW
4 3
TCE
RW
2
Reset value: 0000 0000 (00h)
1 0
FCRL OIE OVF
RW RW RW
Table 45.
ARTCSR register description
Bit Name Function
7 EXCL
External Clock
This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler.
0: CPU clock
1: External clock
6:4 CC[2:0]
Counter Clock Control
These bits are set and cleared by software. They determine the prescaler division ratio from f
INPUT
).
3 TCE
Timer Counter Enable
This bit is set and cleared by software. It puts the timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen)
1: Counter running
2
1
0
FCRL
OIE
OVF
Force Counter Re-Load
This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count.
Overflow Interrupt Enable
This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set.
0: Overflow Interrupt disable
1: Overflow Interrupt enable
Overflow Flag
This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value.
0: New transition not yet reached
1: Transition reached
Table 46.
Prescaler selection for ART f
COUNTER
With f
INPUT
= 8 MHz f
INPUT f
INPUT
/ 2 f
INPUT
/ 4
8 MHz
4 MHz
2 MHz
CC2
0
0
0
CC1
0
0
1
CC0
0
1
0
Doc ID 17660 Rev 1
ST72521xx-Auto PWM auto-reload timer (ART)
Table 46.
Prescaler selection for ART (continued) f
COUNTER f
INPUT
/ 8 f
INPUT
/ 16 f
INPUT
/ 32 f
INPUT
/ 64 f
INPUT
/ 128
With f
INPUT
= 8 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
CC2
0
1
1
1
1
CC1
1
0
0
1
1
CC0
1
0
1
0
1
12.3.2 Counter access register (ARTCAR)
ARTCAR
7 6 5 4
CA[7:0]
RW
3 2
Reset value: 0000 0000 (00h)
1 0
Table 47.
ARTCAR register description
Bit Name Function
7:0 CA[7:0]
Counter Access Data
These bits can be set and cleared either by hardware or by software. The
ARTCAR register is used to read or write the auto-reload counter “on the fly”
(while it is counting).
12.3.3 Auto-reload register (ARTARR)
ARTARR
7 6 5 4 3 2
Reset value: 0000 0000 (00h)
1 0
AR[7:0]
RW
Table 48.
ARTAAR register description
Bit Name Function
7:0 AR[7:0]
Counter Auto-Reload Data
These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding
OPx bit in the PWMCR register.
This register has two PWM management functions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
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PWM auto-reload timer (ART) ST72521xx-Auto
Table 49.
PWM frequency versus resolution
ARTARR value Resolution
0
[ 0..127 ]
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
8-bit
> 7-bit
> 6-bit
> 5-bit
> 4-bit
Min
~0.244 kHz
~0.244 kHz
~0.488 kHz
~0.977 kHz
~1.953 kHz f
PWM
Max
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
12.3.4 PWM control register (PWMCR)
PWMCR
7 6
OE[3:0]
RW
5 4 3 2
Reset value: 0000 0000 (00h)
1 0
OP[3:0]
RW
Table 50.
PWMCR register description
Bit Name Function
7:4 OE[3:0]
PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin.
0: PWM output disabled
1: PWM output enabled
3:0 OP[3:0]
PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity
of the four PWM output signals (see Table 51 ).
Table 51.
PWM output signal polarity selection
PWMx output level
Counter <= OCRx Counter > OCRx
1
0
0
1
1.
When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
OPx
(1)
0
1
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ST72521xx-Auto PWM auto-reload timer (ART)
12.3.5 Duty cycle registers (PWMDCRx)
PWMDCRx
7 6 5 4
DC[7:0]
RW
3 2
Reset value: 0000 0000 (00h)
1 0
Table 52.
PWMDCRx register description
Bit Name Function
7:0 DC[7:0]
Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel.
12.3.6 Input capture control / status register (ARTICCSR)
ARTICCSR
7
Reserved
6
-
5
CS[2:1]
RW
4 3
CIE[2:1]
2
Reset value: 0000 0000 (00h)
1 0
CF[2:1]
RW RW
Table 53.
ARTICCSR register description
Bit Name Function
7:6 -
5:4 CS[2:1]
Reserved, always read as 0.
Capture Sensitivity
These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x
1: Rising edge triggers capture on channel x
3:2 CIE[2:1]
Capture Interrupt Enable
These bits are set and cleared by software. They enable or disable the Input capture channel interrupts independently.
0: Input capture channel x interrupt disabled
1: Input capture channel x interrupt enabled
1:0 CF[2:1]
Capture Flag
These bits are set by hardware and cleared by software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x has occurred.
0: No input capture on channel x
1: An input capture has occurred on channel x.
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PWM auto-reload timer (ART) ST72521xx-Auto
12.3.7 Input capture registers (ARTICRx)
ARTICRx
7 6 5 4
IC[7:0]
RO
3 2
Reset value: 0000 0000 (00h)
1 0
Table 54.
ARTICRx register description
Bit Name
7:0 IC[7:0]
Function
Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event.
Table 55.
PWM auto-reload timer register map and reset values
Address (Hex.) Register label 7 6 5 4 3 2
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
PWMDCR3
Reset value
PWMDCR2
Reset value
PWMDCR1
Reset value
PWMDCR0
Reset value
PWMCR
Reset value
ARTCSR
Reset value
ARTCAR
Reset value
ARTARR
Reset value
ARTICCSR
Reset value
ARTICR1
Reset value
ARTICR2
Reset value
0
IC7
0
IC7
0
DC7
0
DC7
0
DC7
0
DC7
0
OE3
0
EXCL
0
CA7
0
AR7
0
0
IC6
0
IC6
0
DC6
0
DC6
0
DC6
0
DC6
0
OE2
0
CC2
0
CA6
0
AR6
0
CS2
0
IC5
0
IC5
0
CC1
0
CA5
0
AR5
0
DC5
0
DC5
0
DC5
0
DC5
0
OE1
0
CS1
0
IC4
0
IC4
0
CC0
0
CA4
0
AR4
0
DC4
0
DC4
0
DC4
0
DC4
0
OE0
0
CIE2
0
IC3
0
IC3
0
TCE
0
CA3
0
AR3
0
DC3
0
DC3
0
DC3
0
DC3
0
OP3
0
CIE1
0
IC2
0
IC2
0
FCRL
0
CA2
0
AR2
0
DC2
0
DC2
0
DC2
0
DC2
0
OP2
0
1
CF2
0
IC1
0
IC1
0
RIE
0
CA1
0
AR1
0
DC1
0
DC1
0
DC1
0
DC1
0
OP1
0
0
CF1
0
IC0
0
IC0
0
OVF
0
CA0
0
AR0
0
DC0
0
DC0
0
DC0
0
DC0
0
OP0
0
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ST72521xx-Auto 16-bit timer
13.1 Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after an MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).
Note:
●
●
●
●
●
●
●
●
●
Programmable prescaler: f
CPU
divided by 2, 4 or 8
Overflow status flag and maskable interrupt
External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge
1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Pulse Width Modulation mode (PWM)
One Pulse mode
Reduced Power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
(a)
The block diagram is shown in
When reading an input signal on a non-bonded pin, the value will always be ‘1’.
a.
Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout description.
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16-bit timer ST72521xx-Auto
13.3.1 Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low.
Counter Register (CR)
●
●
Counter High Register (CHR) is the most significant byte (MS Byte)
Counter Low Register (CLR) is the least significant byte (LS Byte)
Alternate Counter Register (ACR)
●
●
Alternate Counter High Register (ACHR) is the most significant byte (MS Byte)
Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte)
These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence ).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 61: Timer clock selection
. The value in the counter register repeats every 131072,
262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
CPU
/2, f
CPU
/4, f
CPU
/8 or an external frequency.
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Figure 41.
Timer block diagram
16-bit timer
ST7 INTERNAL BUS f
CPU
EXTCLK pin
MCU-PERIPHERAL INTERFACE
8 high 8 low
8-bit buffer
8 8 8 8 8 8 8 8
EXEDG
1/2
1/4
1/8
CC[1:0]
16
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
16
OUTPUT
COMPARE
REGISTER
1
OUTPUT
COMPARE
REGISTER
2
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16 16
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
EDGE DETECT
CIRCUIT1
ICAP1 pin
6 EDGE DETECT
CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(Control/Status Register)
CSR
LATCH2
OCMP1 pin
OCMP2 pin
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
(Control Register 2) CR2
(1)
TIMER INTERRUPT
1.
If IC, OC and TO interrupt request have separate vectors, then the last OR is not present (see device interrupt vector table).
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16-bit timer
Note:
ST72521xx-Auto
16-bit read sequence
The 16-bit read sequence (from either the Counter Register or the Alternate Counter
Register) is illustrated in
.
Figure 42.
16-bit read sequence
Beginning of the sequence
At t0
Read
MS Byte
LS Byte is buffered
Other instructions
At t0 +Dt
Read
LS Byte
Sequence completed
Returns the buffered
LS Byte value at t0
The user must read the MS Byte first; the LS Byte value is then buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.
●
●
Whatever timer mode is used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h, after which the TOF bit of the SR register is set a timer interrupt is generated if
– the TOIE bit of the CR1 register is set and
– the I bit of the CC register is cleared
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps:
1.
Reading the SR register while the TOF bit is set
2. An access (read or write) to the CLR register
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).
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Note:
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus, the external clock frequency must be less than a quarter of the CPU clock frequency.
Figure 43.
Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFD FFFE FFFF 0000 0001 0002 0003
Figure 44.
Counter timing diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
TIMER OVERFLOW FLAG (TOF)
FFFD 0000 0001
Figure 45.
Counter timing diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000
The MCU is in reset state when the internal reset signal is high; when it is low the MCU is running.
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16-bit timer ST72521xx-Auto
In this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAP i pin (see
ICiR
MS Byte
IC i HR
LS Byte
IC i LR
IC i R register is a read-only register.
The active transition is software programmable through the IEDG i bit of Control Registers
(CR i ).
Timing resolution is one count of the free running counter: (f
CPU
/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
●
●
Select the timer clock (CC[1:0]) (see
Table 61: Timer clock selection ).
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available).
And select the following in the CR1 register:
● Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available).
When an input capture occurs:
●
●
ICF i bit is set.
The IC i R register contains the value of the free running counter on the active transition on the ICAP i pin (see
).
● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input capture interrupt request (that is, clearing the ICF i bit) is done in two steps:
1.
Reading the SR register while the ICF i bit is set
2. An access (read or write) to the IC i LR register
Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read.
2 The ICiR register contains the free running counter value which corresponds to the most recent input capture.
3 The two input capture functions can be used together even if the timer also uses the two output compare functions.
4 In One pulse Mode and PWM mode only Input Capture 2 can be used.
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5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function.
6 Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
7 This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
8 The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).
Figure 46.
Input capture block diagram
ICAP1 pin
ICAP2 pin
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
IC2R Register IC1R Register
16-BIT
16-BIT FREE RUNNING
COUNTER
ICIE
ICF1 ICF2
(Control Register 1) CR1
IEDG1
(Status Register) SR
0 0 0
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 47.
Input capture timing diagram
TIMER CLOCK
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
FF01
Note: The rising edge is the a ctive edge.
FF02 FF03
FF03
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16-bit timer ST72521xx-Auto
108/276
In this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time has elapsed.
●
●
●
When a match is found between the Output Compare register and the free running counter, the output compare function:
Assigns pins with a programmable value if the OC
Sets a flag in the status register
Generates an interrupt if enabled i E bit is set
Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
OC i R
MS byte
OC i HR
LS byte
OC i LR
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC i
R value to 8000h.
Timing resolution is one count of the free running counter: (f
CPU/CC[1:0]
).
Procedure
To use the output compare function, select the following in the CR2 register:
● Set the OC i E bit if an output is needed then the OCMP compare i signal.
i pin is dedicated to the output
● Select the timer clock (CC[1:0]) (see
Table 61: Timer clock selection ).
●
●
And select the following in the CR1 register:
Select the OLVL i bit to applied to the OCMP i pins after the match occurs.
Set the OCIE bit to generate an interrupt if it is needed.
●
●
●
When a match is found between OCRi register and CR register:
OCF i bit is set.
The OCMP i pin takes OLVL i bit value (OCMP
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC).
i pin latch is forced low during reset).
The OC i
R register value required for a specific timing application can be calculated using the following formula:
OC i R =
t
*
f
CPU
PRESC
Where:
t = Output compare period (in seconds) f
CPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 61:
)
Doc ID 17660 Rev 1
ST72521xx-Auto 16-bit timer
If the timer clock is an external clock, the formula is:
OC i R =
t
*
f
EXT
Where:
t = Output compare period (in seconds) f
CPU
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (that is, clearing the OCF i bit) is done by:
1.
Reading the SR register while the OCF i bit is set
2. An access (read or write) to the OC i LR register
●
●
The following procedure is recommended to prevent the OCF i bit from being set between the time it is read and the write to the OC i
R register:
Write to the OC i HR register (further compares are inhibited).
Read the SR register (first step of the clearance of the OCF i bit, which may be already set).
● Write to the OC bit).
i LR register (enables the output compare function and clears the OCF i
Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written.
2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 49 on page 110
for an example with f
CPU
/2 and
Figure 50 on page 110 for an example with f
CPU
PWM mode.
/4). This behavior is the same in OPM or
4 The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
5 The value in the 16-bit OC i
R register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.
13.3.5 Forced compare output capability
When the FOLV i bit is set by software, the OLVL i bit is copied to the OCMP i pin. The OLV i bit has to be toggled in order to toggle the OCMP i pin when it is enabled (OC i E bit = 1). The
OCF i bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVL i bits have no effect in both one pulse mode and PWM mode.
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16-bit timer
Figure 48.
Output compare block diagram
ST72521xx-Auto
16-BIT FREE RUNNING
COUNTER
16-bit
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R Register
16-bit
OC2R Register
OC1E OC2E
OCIE
CC1 CC0
(Control Register 2) CR2
(Control Register 1) CR1
FOLV2 FOLV1 OLVL2 OLVL1
Latch
1
Latch
2
OCF1 OCF2 0 0 0
(Status Register) SR
OCMP1 pin
OCMP2 pin
Figure 49.
Output compare timing diagram, f
TIMER
= f
CPU
/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i )
OUTPUT COMPARE FLAG i (OCF i )
OCMP i PIN (OLVL i = 1)
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
Figure 50.
Output compare timing diagram, f
TIMER
= f
CPU
/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i )
OUTPUT COMPARE FLAG i (OCF i )
OCMP i PIN (OLVL i = 1)
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
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One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use one pulse mode:
1.
Load the OC1R register with the value corresponding to the length of the pulse (using the appropriate formula below according to the timer clock source used).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
–
Select the timer clock CC[1:0] (see Table 61: Timer clock selection ).
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Figure 51.
One pulse mode cycle flowchart
When event occurs on ICAP1
When counter = OC1R
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
OCMP1 = OLVL1
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICF i bit) is done in two steps:
1.
Reading the SR register while the ICF i bit is set
2. An access (read or write) to the IC i LR register
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16-bit timer ST72521xx-Auto
The OC1R register value required for a specific timing application can be calculated using the following formula:
OC i R value = t
* f
CPU
PRESC
- 5
Where: t = Pulse period (in seconds) f
CPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see
)
If the timer clock is an external clock the formula is:
OC i R = t
*
f
EXT
- 5
Where: t = Pulse period (in seconds) f
EXT
= External clock frequency (in hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (see
).
Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt.
2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
4 The ICAP1 pin cannot be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.
5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 52.
One pulse mode timing example
IC1R
COUNTER
01F8 FFFC FFFD FFFE
ICAP1
OCMP1
OLVL2
01F8
2ED0 2ED1 2ED2
2ED3
2ED3
FFFC FFFD
OLVL2 compare1
OLVL1
Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
112/276 Doc ID 17660 Rev 1
ST72521xx-Auto 16-bit timer
Figure 53.
Pulse width modulation mode timing example with 2 output compare functions
COUNTER 34E2
FFFC FFFD FFFE
OLVL2
OCMP1 compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
2ED0 2ED1 2ED2 34E2 FFFC compare1
OLVL1 OLVL2 compare2
Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length.
13.3.7 Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality cannot be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1.
Load the OC2R register with the value corresponding to the period of the signal using the appropriate formula below according to the timer clock source used.
2. Load the OC1R register with the value corresponding to the period of the pulse if
OLVL1 = 0 and OLVL2 = 1 using the appropriate formula below according to the timer clock source used.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
–
Select the timer clock (CC[1:0]) (see Table 61: Timer clock selection ).
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16-bit timer
Figure 54.
Pulse width modulation cycle flowchart
ST72521xx-Auto
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OC i
R register value required for a specific timing application can be calculated using the following formula:
OC i R value = t
* f
CPU
PRESC
- 5
Where: t = Signal or pulse period (in seconds) f
CPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 61:
)
If the timer clock is an external clock the formula is:
OC i R = t
*
f
EXT
-5
Where: t = Signal or pulse period (in seconds) f
EXT
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 53 ).
Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written.
2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.
4 In PWM mode the ICAP1 pin cannot be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set.
5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
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ST72521xx-Auto 16-bit timer
13.4 Low power modes
Table 56.
Effect of low power modes on 16-bit timer
Mode Effect
Wait
Halt
No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from Halt mode” capability or from the counter reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAP i pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from Halt mode” capability, the ICF i bit is set, and the counter value present when exiting from Halt mode is captured into the IC i R register.
13.5 Interrupts
Note:
Table 57.
16-bit timer interrupt control/wake-up capability
Interrupt event
Event flag
Enable control bit
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
ICIE
OCIE
TOIE
Exit from
Wait
Yes
Exit from
Halt
No
The 16-bit timer interrupt events are connected to the same interrupt vector (see
Interrupts on page 52 ). These events generate an interrupt if the corresponding Enable
Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
13.6 Summary of timer modes
Table 58.
Timer modes
Modes
Input
Capture 1
Timer resources
Input
Capture 2
Output
Compare 1
Input Capture
(1 and/or 2)
Output Compare
(1 and/or 2)
Yes Yes Yes
Output
Compare 2
Yes
Doc ID 17660 Rev 1 115/276
16-bit timer
Table 58.
Timer modes
Timer resources
Modes
Input
Capture 1
Input
Capture 2
One Pulse mode
PWM mode
No
Not recommended
(1)
Not recommended
(3)
1.
See Note 4
in Section 13.3.6 One Pulse mode
2.
See Note 5
in Section 13.3.6 One Pulse mode
3.
See Note 4
in Section 13.3.7 Pulse width modulation mode
Output
Compare 1
No
ST72521xx-Auto
Output
Compare 2
Partially
(2)
No
13.7 16-bit timer registers
Each timer is associated with 3 control and status registers, and with 6 pairs of data registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter and the alternate counter.
13.7.1 Control register 1 (CR1)
CR1
7
ICIE
RW
6
OCIE
RW
5
TOIE
RW
4
FOLV2
RW
3
FOLV1
RW
2
Reset value: 0000 0000 (00h)
1 0
OLVL2 IEDG1 OLVL1
RW RW RW
Table 59.
CR1 register description
Bit Name Function
7
6 OCIE
5
ICIE
TOIE
Input Capture Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
Output Compare Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set.
Timer Overflow Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
4 FOLV2
Forced Output Compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison
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ST72521xx-Auto 16-bit timer
Table 59.
CR1 register description (continued)
Bit Name Function
3 FOLV1
Forced Output Compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison
2 OLVL2
Output Level 2
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.
1 IEDG1
Input Edge 1
This bit determines which type of level transition on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0 OLVL1
Output Level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
13.7.2 Control register 2 (CR2)
CR2
7
OC1E
RW
6
OC2E
RW
5
OPM
RW
4
PWM
RW
3
CC[1:0]
2
Reset value: 0000 0000 (00h)
1 0
IEDG2 EXEDG
RW RW RW
Table 60.
CR2 register description
Bit Name Function
7 OC1E
Output Compare 1 Pin Enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode).
Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP1 pin alternate function enabled
6 OC2E
Output Compare 2 Pin Enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare
2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP2 pin alternate function enabled
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16-bit timer ST72521xx-Auto
Table 60.
CR2 register description (continued)
Bit Name Function
5 OPM
One Pulse Mode
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
4 PWM
Pulse Width Modulation
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.
3:2 CC[1:0]
Clock Control
The timer clock mode depends on these bits (see
).
1 IEDG2
Input Edge 2
This bit determines which type of level transition on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0 EXEDG
External Clock Edge
This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
Table 61.
Timer clock selection
Timer clock CC1 CC0 f
CPU
/ 4 f
CPU
/ 2 f
CPU
/ 8
External clock (where available)
(1)
0
0
1
1
0
1
0
1
1.
If the external clock pin is not available, programming the external clock configuration stops the counter.
CSR
7
ICF1
RO
6
OCF1
RO
5
TOF
RO
4
ICF2
RO
3
OCF2
RO
2
Reset value: xxxx x0xx (xxh)
1 0
TIMD Reserved
RW -
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Table 62.
CSR register description
Bit Name
7
6
5
4
3
2
1:0
Function
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
-
Input Capture Flag 1
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register.
Output Compare Flag 1
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.
Timer Overflow Flag
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
Input Capture Flag 2
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the
SR register, then read or write the low byte of the IC2R (IC2LR) register.
Output Compare Flag 2
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.
Timer disable
This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Reserved, must be kept cleared
13.7.4 Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
IC1HR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
RO
Reset value: Undefined
1 0
RO
LSB
RO
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16-bit timer ST72521xx-Auto
13.7.5 Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
IC1LR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
RO
Reset value: Undefined
1 0
RO
LSB
RO
This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
OC1HR
7
MSB
RW
6
RW
5
RW
4
RW
3
RW
2
Reset value: 1000 0000 (80h)
1 0
LSB
RW RW RW
This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
OC1LR
7
MSB
RW
6
RW
5
RW
4
RW
3
RW
2
RW
Reset value: 0000 0000 (00h)
1
RW
0
LSB
RW
This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
OC2HR
7
MSB
RW
6
RW
5
RW
4
RW
3
RW
2
Reset value: 1000 0000 (80h)
1 0
LSB
RW RW RW
120/276 Doc ID 17660 Rev 1
ST72521xx-Auto 16-bit timer
This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
OC2LR
7
MSB
RW
6
RW
5
RW
4
RW
3
RW
2
Reset value: 0000 0000 (00h)
1 0
RW RW
LSB
RW
This is an 8-bit register that contains the high part of the counter value.
CHR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
Reset value: 1111 1111 (FFh)
1 0
LSB
RO RO RO
13.7.11 Counter low register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
CLR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
Reset value: 1111 1100 (FCh)
RO
1
RO
0
LSB
RO
This is an 8-bit register that contains the high part of the counter value.
ACHR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
Reset value: 1111 1111 (FFh)
1 0
LSB
RO RO RO
Doc ID 17660 Rev 1 121/276
16-bit timer ST72521xx-Auto
This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.
ACLR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
Reset value: 1111 1100 (FCh)
1 0
RO RO
LSB
RO
13.7.14 Input capture 2 high register (IC2HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
IC2HR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
RO
Reset value: Undefined
1 0
LSB
RO RO
13.7.15 Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
IC2LR
7
MSB
RO
6
RO
5
RO
4
RO
3
RO
2
RO
Reset value: Undefined
1
RO
0
LSB
RO
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Table 63.
16-bit timer register map and reset values
Address
(Hex.)
Register label
7 6 5 4
Timer A: 32
Timer B: 42
CR1
Reset value
Timer A: 31
Timer B: 41
CR2
Reset value
Timer A: 33
Timer B: 43
CSR
Reset value
Timer A: 34
Timer B: 44
IC1HR
Reset value
Timer A: 35
Timer B: 45
IC1LR
Reset value
Timer A: 36
Timer B: 46
OC1HR
Reset value
Timer A: 37
Timer B: 47
OC1LR
Reset value
Timer A: 3E
Timer B: 4E
OC2HR
Reset value
Timer A: 3F
Timer B: 4F
OC2LR
Reset value
Timer A: 38
Timer B: 48
CHR
Reset value
Timer A: 39
Timer B: 49
CLR
Reset value
Timer A: 3A
Timer B: 4A
ACHR
Reset value
Timer A: 3B
Timer B: 4B
ACLR
Reset value
Timer A: 3C
Timer B: 4C
IC2HR
Reset value
Timer A: 3D
Timer B: 4D
IC2LR
Reset value
MSB x
MSB
1
MSB
0
MSB
1
MSB
0
ICIE
0
OC1E
0
ICF1 x
MSB x
MSB
1
MSB x
MSB x
MSB
1
MSB
1
MSB
1
OCIE
0
OC2E
0
OCF1 x x x
0
0
0
0
1
1
1
1 x x
TOIE
0
OPM
0
TOF x x x
0
0
0
0
1
1
1
1 x x
3 2 1 0
FOLV2
0
PWM
0
ICF2 x
FOLV1
0
CC1
0
OCF2 x x x
0
0
0
0
1
1
1
1 x x x x
0
0
0
0
1
1
1
1 x x
OLVL2
0
IEDG1
0
OLVL1
0
CC0
0
TIMD
0 x
IEDG2
0
x x
EXEDG
0
x
LSB x x
0
0
0
0 x
0
0
0
0
LSB x
LSB
0
LSB
0
LSB
0
LSB
0
1
1
1
1 x x
1
0
1
0 x x
LSB
0
LSB x
LSB x
LSB
1
LSB
0
LSB
1
Related documentation
SCI software communications using 16-bit timer (AN 973)
Real-time Clock with ST7 Timer Output Compare (AN 974)
Driving a buzzer through the ST7 Timer PWM function (AN 976)
Using ST7 PWM signal to generate analog input (sinusoid) (AN1041)
UART emulation software (AN1046)
PWM duty cycle switch implementing true 0 or 100 per cent duty cycle (AN1078)
Starting a PWM signal directly at high level using the ST7 16-bit timer (AN1504)
Doc ID 17660 Rev 1 123/276
Serial peripheral interface (SPI)
14 Serial peripheral interface (SPI)
ST72521xx-Auto
14.1 Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface cannot be a master in a multimaster system.
Note:
●
●
●
●
●
●
●
●
●
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
6 master mode frequencies (f
CPU
/4 max.) f
CPU
/2 max. slave mode frequency (see note)
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun flags
In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.
●
●
●
shows the serial peripheral interface (SPI) block diagram. There are three registers:
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
●
●
●
●
The SPI is connected to external devices through four pins:
MISO (Master In / Slave Out data)
MOSI (Master Out / Slave In data)
SCK (Serial Clock out by SPI masters and input by SPI slaves)
SS (Slave select): This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master MCU.
124/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 55.
Serial peripheral interface block diagram
Data/Address Bus
Read
SPIDR
Read Buffer
MOSI
MISO 8-bit Shift Register
Write
SOD bit
Serial peripheral interface (SPI)
Interrupt request
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
SCK
SPI
STATE
CONTROL
SS
1
0
7 SPICR 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
A basic example of interconnections between a single master and a single slave is illustrated in
.
The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 59 ) but master and
slave must be programmed with the same timing mode.
Doc ID 17660 Rev 1 125/276
Serial peripheral interface (SPI)
Figure 56.
Single master/single slave application
MASTER
MSBit LSBit
8-BIT SHIFT REGISTER
MISO MISO
MOSI MOSI
ST72521xx-Auto
SLAVE
MSBit LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
+5V
SCK
SS
Not used if SS is managed by software
14.3.2 Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 58 )
In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode
● SS internal must be held high continuously
In Slave mode
There are two cases depending on the data/clock timing relationship (see Figure 57 ):
If CPHA = 1 (data latched on 2nd clock edge):
● SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to V
SS
, or made free for standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on 1st clock edge):
● SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
).
126/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 57.
Generic SS timing diagram
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Byte 1 Byte 2
Serial peripheral interface (SPI)
Figure 58.
Hardware/Software slave select management
SSM bit
Byte 3
SSI bit
SS external pin
1
0
SS internal
Note:
Note:
Note:
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
Write to the SPICR register: a) Select the clock frequency by configuring the SPR[2:0] bits.
b) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
shows the four possible configurations.
The slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence.
3. Write to the SPICR register:
Set the MSTR and SPE bits
MSTR and SPE bits remain set only if SS is high).
IMPORTANT : If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may not be taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
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Serial peripheral interface (SPI) ST72521xx-Auto
14.3.4 Master mode transmit sequence
Note:
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1.
An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
Note:
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
Write to the SPICSR register to perform the following actions: a) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
).
The slave must have the same CPOL and CPHA settings as the master.
the
Slave select management on page 126
and
. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register.
2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Note:
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware.
– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1.
An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
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The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see
).
14.4 Clock phase and clock polarity
Note:
Note:
Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (see
).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge
shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
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Serial peripheral interface (SPI)
Figure 59.
Data clock timing diagram
ST72521xx-Auto
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSBit
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 6
Bit 5 Bit 4
Bit 5 Bit 4
Bit3 Bit 2 Bit 1 LSBit
Bit3 Bit 2 Bit 1 LSBit
Note: This figure should not be used as a replacement for parametric information.
Refer to
Section 20: Electrical characteristics .
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14.5.1 Master mode fault (MODF)
Note:
Master mode fault occurs when the master device has its SS pin pulled low.
When a Master mode fault occurs:
●
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral.
● The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
1.
A read access to the SPICSR register while the MODF bit is set.
2. A write to the SPICR register.
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.
14.5.2 Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs:
● The OVR bit is set and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
14.5.3 Write collision error (WCOL)
Note:
A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.
A “read collision” will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 60 ).
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Serial peripheral interface (SPI) ST72521xx-Auto
Figure 60.
Clearing the WCOL bit (Write Collision Flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
2nd Step
Read SPIDR
RESULT
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
2nd Step Read SPIDR
RESULT
WCOL = 0
Note: Writing to the SPIDR register instead of reading it does not reset the
WCOL bit.
14.5.4 Single master systems
Note:
A typical single master system may be configured, using an MCU as the master and four
).
The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.
To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with command fields.
Figure 61.
Single master / multiple slave configuration
SCK
Slave
MCU
SS
MOSI MISO
SCK
Slave
MCU
SS
MOSI MISO
SCK
Slave
MCU
SS
MOSI MISO
SCK
Slave
MCU
SS
MOSI MISO
5V
MOSI
SCK
Master
MCU
MISO
SS
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14.6 Low power modes
Table 64.
Effect of low power modes on SPI
Mode Effect
Wait
Halt
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from Halt mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wake-up event, then an overrun error is generated.
This error can be detected after the fetch of the interrupt routine that woke up the device.
14.6.1 Using the SPI to wake up the MCU from Halt mode
Note:
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately.
Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave
selection is configured as external (see Slave select management on page 126 ), make sure
the master drives a low level on the SS pin when the slave enters Halt mode.
14.7 Interrupts
Note:
Table 65.
SPI interrupt control/wake-up capability
Interrupt event Event flag
Enable control bit
SPI End of Transfer event
Master Mode Fault event
Overrun error
SPIF
MODF
OVR
SPIE
Exit from
Wait
Yes
Exit from
Halt
Yes
No
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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Serial peripheral interface (SPI) ST72521xx-Auto
14.8.1 Control register (SPICR)
SPICR
7
SPIE
RW
6
SPE
RW
5
SPR2
RW
4
MSTR
RW
3
CPOL
RW
2
Reset value: 0000 xxxx (0xh)
1 0
CPHA SPR[1:0]
RW RW
Table 66.
SPICR register description
Bit Name
7
6
5
4
3
2
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
Function
Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see Master mode fault (MODF) on page 131 ). The SPE bit
is cleared by reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see
Master mode fault (MODF) on page 131 ).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
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Table 66.
SPICR register description (continued)
Bit Name Function
1:0 SPR[1:0]
Serial Clock Frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode.
Note: These 2 bits have no effect in slave mode.
Table 67.
SPI master mode SCK frequency
Serial clock SPR2 f
CPU
/4 f
CPU
/8 f
CPU
/16 f
CPU
/32 f
CPU
/64 f
CPU
/128
0
1
1
0
0
0
SPR1
0
1
0
0
1
1
SPR0
1
0
0
0
0
1
14.8.2 Control/status register (SPICSR)
SPICSR
7
SPIF
RO
6
WCOL
RO
5
OVR
RO
4
MODF
RO
3
Reserved
-
2
Reset value: 0000 0000 (00h)
1 0
SOD SSM SSI
RW RW RW
Table 68.
SPICSR register description
Bit Name Function
7
5
SPIF
OVR
Serial Peripheral Data Transfer Flag
This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
6 WCOL
Write Collision status
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see Figure 60
).
0: No write collision occurred.
1: A write collision has been detected.
SPI Overrun error
This bit is set by hardware when the byte currently being received in the shift register
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
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Serial peripheral interface (SPI) ST72521xx-Auto
Table 68.
SPICSR register description (continued)
Bit Name Function
4 MODF
Mode Fault flag
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page 131
). An SPI interrupt can be generated if
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An access to the SPICR register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
3 Reserved, must be kept cleared
2
1
0
SOD
SSM
SSI
SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
SS Management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave select management on page 126 .
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)
SS Internal Mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
14.8.3 Data I/O register (SPIDR)
Note:
SPIDR
7 6 5 4 3 2
Reset value: Undefined
1 0
D[7:0]
RW
The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
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Warning: A write to the SPIDR register places data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 55
).
Table 69.
SPI register map and reset values
Address
(Hex.)
Register label
7 6 5
0021h
0022h
0023h
SPIDR
Reset value
SPICR
Reset value
SPICSR
Reset value
MSB x
SPIE
0
SPIF
0
4 3 2 x
SPE
0
WCOL
0 x
SPR2
0
OVR
0 x
MSTR
0
MODF
0 x
CPOL x
0 x
CPHA x
SOD
0
1 x
SPR1 x
SSM
0
0
LSB x
SPR0 x
SSI
0
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Serial communications interface (SCI) ST72521xx-Auto
15.1 Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.
●
●
●
●
●
●
●
●
●
●
●
●
●
Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
Dual baud rate generator systems
Independently programmable transmit and receive baud rates up to 500K baud
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and End of Transmission flags
2 receiver wake-up modes:
– Address bit (MSB)
– Idle line
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and Receiver
4 error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
5 interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
Parity control:
– Transmits parity bit
– Checks parity of received data byte
Reduced power consumption mode
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The interface is externally connected to another device by two pins (see Figure 63 ):
● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.
● RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●
●
●
●
An Idle Line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
A Stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
●
●
A conventional type for commonly-used baud rates
An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies
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Serial communications interface (SCI)
Figure 62.
SCI block diagram
TDO
RDI
ST72521xx-Auto
Write
Transmit Data Register (TDR)
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Transmit Shift Register Received Shift Register
R8
CR1
T8 SCID M WAKE PCE PS PIE
TRANSMIT
CONTROL
WAKE
UP
UNIT
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK f
CPU
/16 /PR
RECEIVER
CONTROL
RECEIVER
CLOCK
TDRE TC RDRF IDLE OR NF FE PE
SR
TRANSMITTER RATE
CONTROL
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72521xx-Auto Serial communications interface (SCI)
●
●
●
●
●
The block diagram of the Serial Control Interface, is shown in
dedicated registers:
2 control registers (SCICR1 and SCICR2) a status register (SCISR) a baud rate register (SCIBRR) an extended prescaler receiver register (SCIERPR) an extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 15.7
for the definitions of each bit.
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next frame which contains data.
A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 63.
Word length programming
9-bit Word length (M bit is set)
Data Frame
Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Possible
Parity
Bit
Bit8
Stop
Bit
Next Data Frame
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame Extra
‘1’
Start
Bit
8-bit Word length (M bit is reset)
Data Frame
Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible
Parity
Bit
Bit7
Stop
Bit
Next Data Frame
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame Extra
‘1’
Start
Bit
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Serial communications interface (SCI) ST72521xx-Auto
15.4.2 Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Note:
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 62 ).
Procedure
1.
Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIETPR registers.
3. Set the TE bit to assign the TDO pin to the alternate function and to send an idle frame as first transmission.
4. Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1.
An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
●
●
●
The TDR register is empty.
The data transfer is beginning.
The next data can be written in the SCIDR register without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.
When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1.
An access to the SCISR register
2. A write to the SCIDR register
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
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Note: bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the SCIDR.
15.4.3 Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see
Procedure
1.
Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIERPR registers.
3. Set the RE bit, this enables the receiver which begins searching for a start bit.
●
●
When a character is received:
● The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The error flags can be set if a frame error, noise or an overrun error has been detected during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1.
An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data cannot be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared.
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Serial communications interface (SCI)
Note:
ST72521xx-Auto
●
●
●
●
When an overrun error occurs:
The OR bit is set.
The RDR content is not lost.
The shift register is overwritten.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples.
●
●
●
When noise is detected in a frame:
The NF flag is set at the rising edge of the RDRF bit.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation.
During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011,
101, 110), the frame is discarded and the receiving sequence is not started for this frame.
There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received.
If the application Start Bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received.
See also Noise error causes on page 148 .
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Figure 64.
SCI baud rate and extended prescaler block diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER f
CPU
/16 /PR
TRANSMITTER RATE
CONTROL
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
Framing error
A framing error is detected when:
● The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise.
● A break is received.
When the framing error is detected:
●
●
●
The FE bit is set by hardware.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation.
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Serial communications interface (SCI)
Note:
Note:
ST72521xx-Auto
Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows:
Tx =
(16 f
CPU
*
PR)
*
TR
Rx =
(16 f
CPU
*
PR)
*
RR with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f
CPU
is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud.
The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.
Extended baud rate generation
The extended prescaler option provides a very fine tuning of the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility.
The extended baud rate generator block diagram is described in the
The output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows:
Tx = f
CPU
16
*
ETPR
*
(PR
*
TR)
Rx =
16 f
CPU
*
ERPR
*
(PR
*
RR) with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,..,255 (see SCIERPR register)
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non-addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
●
●
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the following two ways:
●
● by Idle Line detection if the WAKE bit is reset by Address Mark detection if the WAKE bit is set
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A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes up by Address Mark detection when it received a ‘1’ as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU = 1) and a address mark wake-up event occurs (RWU is reset) before the write operation, the RWU bit is set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 70
.
Note:
Table 70.
Frame formats
M bit PCE bit
0
0
1
1
0
1
0
1
SCI frame
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit
In case of wake-up by an address mark, the MSB bit of the data is taken into account and not the parity bit
Even parity: the parity bit is calculated to obtain an even number of ‘1’s inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an odd number of ‘1’s inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of ‘1’s if even parity is selected (PS = 0) or an odd number of ‘1’s if odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the Noise Flag bit is set because the three samples values are not the same.
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Serial communications interface (SCI)
Note:
ST72521xx-Auto
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 Kbaud
(bit length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by
~4us. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
– D
TRA
: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate).
– D
QUANT
: Error due to the baud rate quantization of the receiver.
– D
REC
: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message.
– D
TCL
: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
D
TRA
+ D
QUANT
+ D
REC
+ D
TCL
< 3.75%
Noise error causes
See also description of noise error in
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as ‘1’ and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ‘1’.
2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ‘1’.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
● During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag from getting set.
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Figure 65.
Bit sampling in reception mode
Serial communications interface (SCI)
RDI LINE
Sample
clock sampled values
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
7/16
6/16
7/16
One bit time
15.5 Low power modes
Table 71.
Effect of low power modes on SCI
Mode Effect
Wait
Halt
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
15.6 Interrupts
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 72.
SCI interrupt control/wake-up capability
Interrupt event Event flag
Enable control bit
Transmit Data Register Empty
Transmission Complete
Received Data Ready to be Read
Overrun Error Detected
TDRE
TC
RDRF
OR
TIE
TCIE
RIE
Exit from
Wait
Yes
Yes
Yes
Yes
Exit from
Halt
No
No
No
No
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Serial communications interface (SCI) ST72521xx-Auto
Table 72.
SCI interrupt control/wake-up capability
Interrupt event Event flag
Enable control bit
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
Exit from
Wait
Yes
Yes
Exit from
Halt
No
No
SCISR
7
TDRE
RO
6
TC
RO
5
RDRF
RO
4
IDLE
RO
3
OR
RO
2
Reset value: 1100 0000 (C0h)
1 0
NF FE PE
RO RO RO
Table 73.
SCISR register description
Bit Name Function
7 TDRE
Transmit data register empty
This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the
SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register unless the TDRE bit is cleared.
6 TC
Transmission complete
This bit is set by hardware when transmission of a frame containing Data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
5 RDRF
Received data ready flag
This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
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Table 73.
SCISR register description (continued)
Bit Name Function
4 IDLE
3 OR
Idle line detect
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line occurs).
Overrun error
This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is not lost but the shift register is overwritten.
2
1
0
NF
FE
PE
Noise flag
This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set.
Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
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Serial communications interface (SCI) ST72521xx-Auto
15.7.2 Control register 1 (SCICR1)
SCICR1
7
R8
RW
6
T8
RW
5
SCID
RW
4
M
RW
3
WAKE
RW
2
Reset value: X000 0000 (x0h)
1 0
PCE PS PIE
RW RW RW
Table 74.
SCICR1 register description
Bit Name Function
7
6
2
1
R8
T8
PCE
PS
Receive data bit 8
This bit is used to store the 9th bit of the received word when M = 1.
Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when M = 1.
5
4
SCID
M
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and reception).
3 WAKE
Wake-up method
This bit determines the SCI wake-up method. It is set or cleared by software.
0: Idle line
1: Address mark
Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
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Table 74.
SCICR1 register description (continued)
Bit Name Function
0 PIE
Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
15.7.3 Control register 2 (SCICR2)
SCICR2
7
TIE
RW
6
TCIE
RW
5
RIE
RW
4
ILIE
RW
3
TE
RW
2
Reset value: 0000 0000 (00h)
1 0
RE RWU SBK
RW RW RW
Table 75.
SCICR2 register description
Bit Name Function
7 TIE
Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
6 TCIE
Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
5
4
3
RIE
ILIE
TE
Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register.
Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(idle line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Caution : The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).
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Serial communications interface (SCI) ST72521xx-Auto
Table 75.
SCICR2 register description (continued)
Bit Name Function
2 RE
Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
1 RWU
Receiver wake-up
This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with wake-up by idle line detection.
0 SBK
Send break
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a BREAK word at the end of the current word .
This register contains the Received or Transmitted data character, depending on whether it is read from or written to.
SCIDR
7 6 5 4 3 2
Reset value: Undefined
1 0
DR[7:0]
RW
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
).
The RDR register provides the parallel interface between the input shift register and the internal bus (see
).
SCIBRR
7
SCP[1:0]
6
RW
5 4
SCT[2:0]
RW
3 2
Reset value: 0000 0000 (00h)
1 0
SCR[2:0]
RW
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Table 76.
SCIBRR register description
Bit Name Function
7:6 SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges.
00: PR prescaling factor = 1
01: PR prescaling factor = 3
10: PR prescaling factor = 4
11: PR prescaling factor = 13
5:3 SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate
Generator mode.
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
2:0 SCR[2:0]
SCI Receiver rate divisor
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate
Generator mode.
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
This register allows setting of the extended prescaler rate division factor for the receive circuit.
SCIERPR
7 6 5 2
Reset value: 0000 0000 (00h)
1 0 4
ERPR[7:0]
RW
3
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Serial communications interface (SCI) ST72521xx-Auto
Table 77.
SCIERPR register description
Bit Name Function
7:0 ERPR[7:0]
8-bit Extended Receive Prescaler Register
The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider
) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
This register allows setting of the external prescaler rate division factor for the transmit circuit.
SCIETPR
7 6 5 2
Reset value: 0000 0000 (00h)
1 0 4
ETPR[7:0]
RW
3
Table 78.
SCIETPR register description
Bit Name Function
7:0 ETPR[7:0]
8-bit Extended Transmit Prescaler Register
The extended baud rate generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider
) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
Table 79.
Baud rate selection
Conditions
Symbol Parameter f
CPU
Accuracy versus standard
Prescaler
Standard Baud rate Unit f
Tx f
Rx
Communication frequency
8 MHz
~0.16%
~0.79%
Conventional mode
TR (or RR) = 128, PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR = 13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR = 13
Extended mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
Hz
14400 ~14285.71
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Table 80.
SCI register map and reset values
Address (Hex.) Register label 7 6
0050h
0051h
0052h
0053h
0054h
0055h
0057h
SCISR
Reset value
SCIDR
Reset value
SCIBRR
Reset value
SCICR1
Reset value
SCICR2
Reset value
SCIERPR
Reset value
SCIPETPR
Reset value
TIE
0
MSB
0
MSB
0
TDRE
1
MSB x
SCP1
0
R8 x
TC
1 x
SCP0
0
T8
0
TCIE
0
0
0
5
RDRF
0 x
SCT2
0
SCID
0
RIE
0
0
0
4
IDLE
0
3
OR
0
2
NF
0 x
SCT1
0
M
0
ILIE
0 x
SCT0
0
WAKE
0
TE
0 x
SCR2
0
PCE
0
RE
0
0
0
0
0
0
0
1
FE
0 x
SCR1
0
PS
0
RWU
0
0
0
0
SBK
0
LSB
0
LSB
0
PE
0
LSB x
SCR0
0
PIE
0
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I2C bus interface (I2C)
16 I
2
C bus interface (I2C)
ST72521xx-Auto
16.1 Introduction
The I
2
C bus interface serves as an interface between the microcontroller and the serial I
2
C bus. It provides both multimaster and slave functions, and controls all I
2
C bus-specific sequencing, protocol, arbitration and timing. It supports fast I
2
C mode (400 kHz).
●
●
●
●
●
●
●
Parallel-bus/I
2
C protocol converter
Multimaster capability
7-bit/10-bit addressing
SMBus V1.1 compliant
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
16.2.1 I
2
C master features
●
●
●
●
●
●
●
Clock generation
I
2
C bus busy flag
Arbitration Lost flag
End of byte transmission flag
Transmitter/Receiver flag
Start bit detection flag
Start and Stop generation
16.2.2 I
2
C slave features
●
●
●
●
●
●
●
Stop bit detection
I
2
C bus busy flag
Detection of misplaced start or stop condition
Programmable I
2
C address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
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ST72521xx-Auto I2C bus interface (I2C)
In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I
2
C bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I
2
C bus and a fast I
2
C bus. This selection is made by software.
●
●
The interface can operate in the four following modes:
Slave transmitter/receiver
Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multimaster capability.
In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7- or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to
Figure 66.
I
2
C bus protocol
SDA
MSB ACK
SCL
1 2 8 9
START
CONDITION
STOP
CONDITION
VR02119B
Acknowledge may be enabled and disabled by software.
The I
2
C interface address and/or general call address can be selected by software.
The speed of the I
2
C interface may be selected between standard (up to 100 kHz) and fast
I
2
C (up to 400 kHz).
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I2C bus interface (I2C) ST72521xx-Auto
16.3.3 SDA/SCL line control
Transmitter mode
The interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register.
Receiver mode
The interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register.
The SCL frequency (f
SCL the I
2
C bus mode.
) is controlled by a programmable clock divider which depends on
When the I
2
C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
When the I
2
C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 67.
I
2
C interface block diagram
DATA REGISTER (DR)
SDA or SDAI DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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Refer to the CR, SR1 and SR2 registers in Section 16.7
By default the I
2
C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Note:
As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software).
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address.
Header matched (10-bit mode only): The interface generates an acknowledge pulse if the
ACK bit is set.
Address not matched : The interface ignores it and waits for another Start condition.
●
●
Address matched : The interface generates in sequence: an acknowledge pulse if the ACK bit is set
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 68: Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
●
●
Following the address reception and after the SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: an acknowledge pulse if the ACK bit is set
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low
(see Figure 68: Transfer sequencing
EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low
(see Figure 68: Transfer sequencing EV3).
When the acknowledge pulse is received:
● The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
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Note:
ST72521xx-Auto
Closing slave communication
After the last data byte is transferred, a Stop Condition is generated by the master. The interface detects this condition and sets:
● EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see
Figure 68: Transfer sequencing
EV4).
Error cases
●
●
BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address on the bus.
AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.
In case of errors, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF = 1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte.
SMBus compatibility
The ST7 I
2
C is compatible with the SMBus V1.1 protocol. It supports all SMBus addressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to SMBus Slave
Driver For ST7 I
2
C Peripheral (AN1713).
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
● The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see
Figure 68: Transfer sequencing
EV5).
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Note:
Note:
I2C bus interface (I2C)
Slave address transmission
●
●
Then the slave address is sent to the SDA line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence causes the following event:
– The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low
(see Figure 68: Transfer sequencing
EV9).
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
● The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low
(see Figure 68: Transfer sequencing
EV6).
Next, the master must enter Receiver or Transmitter mode.
In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
●
●
Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low
(see Figure 68: Transfer sequencing
EV7).
To close the communication: Before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low
(see Figure 68: Transfer sequencing
EV8).
When the acknowledge bit is received, the interface sets:
● EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: After writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).
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I2C bus interface (I2C)
Note:
ST72521xx-Auto
Error cases
●
●
●
BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first or second pulse of each 9-bit transaction:
– Single Master Mode
If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication makes it possible to re-initiate transmission.
– Multimaster Mode
Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I
2
C master is on the first or second pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I
2
C master mode transmission. The resetting of the
BUSY bit can then be handled in a similar manner as the BERR flag being set.
AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared).
In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible ‘0’ bits transmitted last. It is then necessary to release both lines by software.
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Figure 68.
Transfer sequencing
7-bit Slave receiver:
S Address A
EV1
Data1 A
EV2
Data2 A
EV2
.....
DataN A
EV2
P
EV4
7-bit Slave transmitter:
S Address A
EV1 EV3
7-bit Master receiver:
S Address A
EV5 EV6
Data1
Data1
A
A
EV3
Data2
Data2
A
A
EV3
.....
.....
DataN
DataN
NA
NA
EV3-1
P
P
EV4
7-bit Master transmitter:
S Address A
EV5 EV6 EV8
10-bit Slave receiver:
S Header A Address A
EV1
Data1 A
Data1
EV8
A
Data2
EV2
.....
A
EV8
.....
DataN A
DataN
EV2
P
A
EV4
EV8
P
10-bit Slave transmitter:
EV7 EV7 EV7
S r
Header A
EV1 EV3
Data1 A
EV3
....
.
DataN A
EV3-1
P
EV4
10-bit Master transmitter:
S Header A
EV5 EV9
Address A
EV6 EV8
10-bit Master receiver:
S r
EV5
Header A
EV6
Data1 A
EV8
.....
Data1 A
EV7
.....
DataN A
DataN A
EV8
EV7
P
P
Legend:
S = Start, Sr = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITE = 1)
EV1: EVF = 1, ADSL = 1, cleared by reading SR1 register.
EV2: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF = 1, AF = 1, BTF = 1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP = 1, STOP = 0) or by writing DR register (DR = FFh). Note: If lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen.
EV4: EVF = 1, STOPF = 1, cleared by reading SR2 register.
EV5: EVF = 1, SB = 1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF = 1, cleared by reading SR1 register followed by writing CR register (for example PE = 1).
EV7: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF = 1, ADD10 = 1, cleared by reading SR1 register followed by writing DR register.
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I2C bus interface (I2C) ST72521xx-Auto
16.5 Low power modes
Table 81.
Effect of low power modes on I
2
C
Mode
Wait
Halt
Effect
No effect on I
2
C interface.
I
2
C interrupts cause the device to exit from Wait mode.
I
2
C registers are frozen.
In Halt mode, the I
2
C interface is inactive and does not acknowledge data on the bus. The
I
2
C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
16.6 Interrupts
Figure 69.
Interrupt control logic diagram
ADD10
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
*
ITE
* EVF can also be set by EV6 or an error from the SR2 register.
Note:
INTERRUPT
EVF
Table 82.
I
2
C interrupt control/wake-up capability
Interrupt event Event flag
Enable control bit
Exit from
Wait
Exit from
Halt
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
ADD10
BTF
ADSEL
SB
AF
STOPF
ARLO
BERR
ITE Yes No
The I
2
C interrupt events are connected to the same interrupt vector (see
chapter).
They generate an interrupt if the corresponding Enable Control bit is set and the I-bit in the
CC register is reset (RIM instruction).
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16.7.1 I
2
C control register (CR)
CR
7
Reserved
-
6 5
PE
RW
4
ENGC
RW
3
START
RW
2
Reset value: 0000 0000 (00h)
1 0
ACK STOP ITE
RW RW RW
Table 83.
CR register description
Bit Name Function
7:6
5
-
PE
Reserved. Forced to 0 by hardware.
Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
- When PE = 0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE = 0
- When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I
2
C interface, write the CR register TWICE with PE = 1 as the first write only activates the interface (only PE is set).
4
2
ENGC
ACK
Enable General Call
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Note: In accordance with the I2C standard, when GCAL addressing is enabled, an
I2C slave can only receive data. It will not transmit data to the master.
3 START
Generation of a Start condition
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0) or when the Start condition is sent (with interrupt generation if ITE = 1).
In Master mode
0: No start generation
1: Repeated start generation
In Slave mode
0: No start generation
1: Start generation when the bus is free
Acknowledge enable
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE = 0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
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I2C bus interface (I2C) ST72521xx-Auto
Table 83.
CR register description (continued)
Bit Name Function
1 STOP
0 ITE
Generation of a Stop condition
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE = 0).
In Master mode
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In Slave mode
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF = 1). In this mode the STOP bit has to be cleared by software.
Interrupt enable
This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE = 0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (see
) is detected.
16.7.2 I
2
C status register 1 (SR1)
SR1
7
EVF
RO
6
ADD10
RO
5
TRA
RO
4
BUSY
RO
3
BTF
RO
2
Reset value: 0000 0000 (00h)
1 0
ADSL M/SL SB
RO RO RO
Table 84.
SR1 register description
Bit Name
7 EVF
Function
Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in Figure 68
. It is also cleared by hardware when the interface is disabled (PE = 0).
0: No event
1: One of the following events has occurred:
- BTF = 1 (Byte received or transmitted)
- ADSL = 1 (Address matched in Slave mode while ACK = 1)
- SB = 1 (Start condition generated in Master mode)
- AF = 1 (No acknowledge received after byte transmission)
- STOPF = 1 (Stop condition detected in Slave mode)
- ARLO = 1 (Arbitration lost in Master mode)
- BERR = 1 (Bus error, misplaced Start or Stop condition detected)
- ADD10 = 1 (Master has sent header byte)
- Address byte successfully transmitted in Master mode
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Table 84.
SR1 register description (continued)
Bit Name Function
6 ADD10
10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE = 0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
5 TRA
Transmitter/Receiver
When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF = 1), loss of bus arbitration (ARLO = 1) or when the interface is disabled (PE = 0).
0: Data byte received (if BTF = 1)
1: Data byte transmitted
4 BUSY
Bus busy
This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE = 0). This can have consequences when operating in Multimaster mode; that is, a second active I
2
C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. A software workaround consists of checking that the
I
2
C is not busy before enabling the I
2
C Multimaster cell.
3 BTF
2 ADSL
Byte transfer finished
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE = 1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE = 0).
Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (see
Figure 68 ). BTF is cleared by reading SR1 register followed by writing the next byte
in DR register.
Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the byte from DR register.
The SCL line is held low while BTF = 1.
0: Byte transfer not done
1: Byte transfer succeeded
Address matched (Slave mode)
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if
ITE = 1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE = 0).
The SCL line is held low while ADSL = 1.
0: Address mismatched or not received
1: Received address matched
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I2C bus interface (I2C) ST72521xx-Auto
Table 84.
SR1 register description (continued)
Bit Name Function
1 M/SL
0 SB
Master/Slave
This bit is set by hardware as soon as the interface is in Master mode (writing
START = 1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled
(PE = 0).
0: Slave mode
1: Master mode
Start bit (Master mode)
This bit is set by hardware as soon as the Start condition is generated (following a write START = 1). An interrupt is generated if ITE = 1. It is cleared by software reading SR1 register followed by writing the address byte in DR register.
It is also cleared by hardware when the interface is disabled (PE = 0).
0: No Start condition
1: Start condition generated
16.7.3 I
2
C status register 2 (SR2)
SR2
7 6
Reserved
-
5 4
AF
RO
3
STOPF
RO
2
Reset value: 0000 0000 (00h)
1 0
ARLO BERR GCAL
RO RO RO
Table 85.
SR2 register description
Bit Name Function
7:5
4
-
AF
Reserved. Forced to 0 by hardware.
Acknowledge failure
This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE = 0).
The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set at the same time.
0: No acknowledge failure
1: Acknowledge failure
Note: When an AF event occurs, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software.
3 STOPF
Stop detection (Slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled
(PE = 0).
The SCL line is not held low while STOPF = 1.
0: No Stop condition detected
1: Stop condition detected
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Table 85.
SR2 register description (continued)
Bit Name Function
2 ARLO
Arbitration lost
This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE = 1. It is cleared by software reading
SR2 register or by hardware when the interface is disabled (PE = 0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL = 0).
The SCL line is not held low while ARLO = 1.
0: No arbitration lost detected
1: Arbitration lost detected
Note: In a Multimaster environment, when the interface is configured in Master
Receive mode it does not perform arbitration during the reception of the
Acknowledge bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I
2
C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set.
1 BERR
Bus error
This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE = 1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE = 0).
The SCL line is not held low while BERR = 1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication.
0 GCAL
General Call (Slave mode)
This bit is set by hardware when a general call address is detected on the bus while
ENGC = 1. It is cleared by hardware detecting a Stop condition (STOPF = 1) or when the interface is disabled (PE = 0).
0: No general call address detected on bus
1: General call address detected on bus
16.7.4 I
2
C clock control register (CCR)
CCR
7
FM/SM
RW
6 5 4 3
CC[6:0]
RW
2
Reset value: 0000 0000 (00h)
1 0
Table 86.
CCR register description
Bit Name Function
7 FM/SM
Fast/Standard I
2
C mode
This bit is set and cleared by software.
It is not cleared when the interface is disabled (PE = 0).
0: Standard I
2
C mode
1: Fast I
2
C mode
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I2C bus interface (I2C) ST72521xx-Auto
Table 86.
CCR register description (continued)
Bit Name Function
6:0 CC[6:0]
7-bit clock divider
These bits select the speed of the bus (f
SCL
) depending on the I
2
C mode. They are not cleared when the interface is disabled (PE = 0).
Refer to
Section 20: Electrical characteristics for the table of values.
Note: The programmed f
SCL
assumes no load on SCL and SDA lines.
16.7.5 I
2
C data register (DR)
DR
7 6 5 4 3 2
Reset value: 0000 0000 (00h)
1 0
D[7:0]
RW
Table 87.
DR register description
Bit Name Function
7:0 D[7:0]
8-bit Data Register
These bits contain the byte to be received or transmitted on the bus.
Transmitter mode: Byte transmission start automatically when the software writes in the DR register.
Receiver mode: The first data byte is received automatically in the DR register using the least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR register.
16.7.6 I
2
C own address register (OAR1)
OAR1
7
ADD7
RW
6
ADD6
RW
5
ADD5
RW
4
ADD4
RW
3
ADD3
RW
2
Reset value: 0000 0000 (00h)
1 0
ADD2 ADD1 ADD0
RW RW RW
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Table 88.
OAR1 register description
Function
Bit Name
7-bit addressing mode
7:1 ADD[7:1]
Interface address
These bits define the I
2
C bus address of the interface. They are not cleared when the interface is disabled
(PE = 0).
0 ADD0
Address direction bit
This bit is ‘don’t care’, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled
(PE = 0).
Address 01h is always ignored.
7:0 ADD[7:0] Not applicable
10-bit addressing mode
Not applicable
Interface address
These are the least significant bits of the I
2
C bus address of the interface.
They are not cleared when the interface is disabled (PE = 0).
16.7.7 I
2
C own address register (OAR2)
OAR2
7
FR[1:0]
RW
6 5 4
Reserved
-
3 2
Reset value: 0100 0000 (40h)
1 0
ADD[9:8] Reserved
RW -
Table 89.
OAR2 register description
Bit Name Function
7:6
5:3
FR[1:0]
-
Frequency bits
These bits are set by software only when the interface is disabled (PE = 0). To configure the interface to I
2
C specified delays, select the value corresponding to the CPU frequency f
CPU
.
00: f
CPU
< 6 MHz
01: f
CPU
= 6 to 8 MHz
Reserved
2:1 ADD[9:8]
Interface address
These are the most significant bits of the I
2
C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE = 0).
0 Reserved
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I2C bus interface (I2C) ST72521xx-Auto
Table 90.
I
2
C register map and reset values
Address
(Hex.)
Register label
7 6 5
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
I2CCR
Reset value
I2CSR1
Reset value
I2CSR2
Reset value
I2CCCR
Reset value
I2COAR1
Reset value
I2COAR2
Reset value
I2CDR
Reset value
0
EVF
0
0
ADD10
0
0
FM/SM
0
ADD7
0
FR1
0
MSB
0
0
CC6
0
ADD6
0
FR0
1
0
PE
0
TRA
0
0
CC5
0
ADD5
0
0
0
4
ENGC
0
BUSY
0
AF
0
CC4
0
ADD4
0
START
0
BTF
0
STOPF
0
CC3
0
ADD3
0
0 0
ACK
0
ADSL
0
ARLO
0
CC2
0
ADD2
0
ADD9
0
0
3
0
2
0
1 0
STOP
0
M/SL
0
BERR
0
CC1
0
ADD1
0
ADD8
0
ITE
0
SB
0
GCAL
0
CC0
0
ADD0
0
0
0
LSB
0
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17 Controller area network (CAN)
Controller area network (CAN)
17.1 Introduction
This peripheral is designed to support serial data exchanges using a multimaster contention based priority scheme as described in CAN specification Rev. 2.0 part A. It can also be connected to a 2.0 B network without problems, since extended frames are checked for correctness and acknowledged accordingly although such frames cannot be transmitted nor received. The same applies to overload frames which are recognized but never initiated.
Figure 70.
CAN block diagram
ST7 Internal Bus
ST7 Interface
RX
TX
TX/RX
Buffer 1
10 bytes
TX/RX
Buffer 2
10 bytes
TX/RX
Buffer 3
10 bytes
ID
Filter 0
4 bytes
ID
Filter 1
4 bytes
BTL BCDL
EML
SHREG
CAN 2.0B passive Core
CRC
ICR
ISR
CSR
TECR
RECR
PSR
BRPR
BTR
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Controller area network (CAN) ST72521xx-Auto
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Support of CAN specification 2.0A and 2.0B passive
3 prioritized 10-byte Transmit/Receive message buffers
2 programmable global 12-bit message acceptance filters
Programmable baud rates up to 1 Mbit/s
Buffer flip-flopping capability in transmission
Maskable interrupts for transmit, receive (one per buffer), error and wake-up
Automatic low-power mode after 20 recessive bits or on demand (standby mode)
Interrupt-driven wake-up from standby mode upon reception of dominant pulse
Optional dominant pulse transmission on leaving standby mode
Automatic message queuing for transmission upon writing of data byte 7
Programmable loop-back mode for self-test operation
Advanced error detection and diagnosis functions
Software-efficient buffer mapping at a unique address space
Scalable architecture
Note:
A summary of all the CAN frame formats is given in
for reference. It covers only the standard frame format since the extended one is only acknowledged.
A message begins with a start bit called Start Of Frame (SOF). This bit is followed by the arbitration field which contains the 11-bit identifier (ID) and the Remote Transmission
Request bit (RTR). The RTR bit indicates whether it is a data frame or a remote request frame. A remote request frame does not have any data byte.
The control field contains the Identifier Extension bit (IDE), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes
(DLC). The data field ranges from zero to eight bytes and is followed by the Cyclic
Redundancy Check (CRC) used as a frame integrity check for detecting bit errors.
The acknowledgement (ACK) field comprises the ACK slot and the ACK delimiter. The bit in the ACK slot is placed on the bus by the transmitter as a recessive bit (logical 1). It is overwritten as a dominant bit (logical 0) by those receivers which have at this time received the data correctly. In this way, the transmitting node can be assured that at least one receiver has correctly received its message.
Messages are acknowledged by the receivers regardless of the outcome of the acceptance test.
The end of the message is indicated by the End Of Frame (EOF). The intermission field defines the minimum number of bit periods separating consecutive messages. If there is no subsequent bus access by any station, the bus remains idle.
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●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
The CAN controller contains the following functional blocks (refer to
):
● ST7 interface: buffering of the ST7 internal bus and address decoding of the CAN registers
● TX/RX buffers: three 10-byte buffers for transmission and reception of maximum length messages
ID filters: two 12-bit compare and don’t care masks for message acceptance filtering
PSR: page selection register (see memory map)
BRPR: clock divider for different data rates
BTR: bit timing register
ICR: interrupt control register
ISR: interrupt status register
CSR: general purpose control/status register
TECR: transmit error counter register
RECR: receive error counter register
BTL: bit timing logic providing programmable bit sampling and bit clock generation for synchronization of the controller
BCDL: bit coding logic generating a NRZ-coded datastream with stuff bits.
SHREG: 8-bit shift register for serialization of data to be transmitted and parallelization of received data
CRC: 15-bit CRC calculator and checker
EML: error detection and management logic
CAN core: CAN 2.0B passive protocol controller
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Controller area network (CAN)
Figure 71.
CAN frames
ST72521xx-Auto
Inter-Frame Space or Overload Frame
Inter-Frame Space Data Frame
44 + 8 * N
Arbitration Field
12
ID
Control Field
6
Data Field
8 * N
DLC
CRC Field
16
CRC
Ack Field
2
7
EOF
Inter-Frame Space
Arbitration Field
12
ID
Control Field
6
DLC
Remote Frame
44
CRC Field
16
CRC
Inter-Frame Space or Overload Frame
Ack Field
2
7
End Of Frame
Data Frame or
Remote Frame Error Frame
Error Flag
6
Flag Echo
< 6
Error Delimiter
8
Inter-Frame Space or Overload Frame
Any Frame Inter-Frame Space
Intermission
3
Suspend
Transmission
8
Bus Idle
Data Frame or
Remote Frame
End Of Frame or
Error Delimiter or
Overload Delimiter Overload Frame
Inter-Frame Space or Error Frame
Overload Flag
6
Overload Delimiter
8
Notes:
• 0 <= N <= 8
• SOF = Start Of Frame
• ID = Identifier
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
• DLC = Data Length Code
• CRC = Cyclic Redundancy Code
• Error flag: 6 dominant bits if node is error active else 6 recessive bits.
• Suspend transmission: applies to error passive nodes only.
• EOF = End of Frame
• ACK = Acknowledge bit
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ST72521xx-Auto Controller area network (CAN)
Note:
The CAN core unit assumes one of the seven states described below.
Standby
Standby mode is entered either on a chip reset or on resetting the RUN bit in the
Control/Status Register (CSR). Any on-going transmission or reception operation is not interrupted and completes normally before the Bit Time Logic and the clock prescaler are turned off for minimum power consumption. This state is signalled by the RUN bit being read-back as 0.
Once in standby, the only event monitored is the reception of a dominant bit which causes a wake-up interrupt if the SCIE bit of the Interrupt Control Register (ICR) is set.
The Standby mode is left by setting the RUN bit. If the WKPS bit is set in the CSR register, then the controller passes through WAKE-UP, otherwise it enters RESYNC directly.
It is important to note that the wake-up mechanism is software-driven and therefore carries a significant time overhead. All messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored.
Standby mode is not entered on resetting the RUN bit in the Control/Status register (CSR) if the CANRX pin is shorted to GND.
Wake-up
The CAN bus line is forced to dominant for one bit time signalling the wake-up condition to all other bus members.
Figure 72.
CAN controller state diagram
RESET
RUN & WKPS
STANDBY
RUN RUN & WKPS WAKE-UP
RESYNC
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF) & 128 * 11 Recessive bits
RUN
IDLE
Write to DATA7 |
TX Error & NRTX
TRANSMISSION
TX OK RX OK
Arbitration lost
Start of Frame
RECEPTION
TX Error
ERROR
BOFF
RX Error
BOFF
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Controller area network (CAN)
Note:
ST72521xx-Auto
Resync
The resynchronization mode is used to find the correct entry point for starting transmission or reception after the node has gone asynchronous either by going into the Standby or busoff states.
Resynchronization is achieved when 128 sequences of 11 recessive bits have been monitored unless the node is not bus-off and the FSYN bit in the CSR register is set in which case a single sequence of 11 recessive bits needs to be monitored.
Idle
The CAN controller looks for one of the following events: The RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7 register of the currently active page is written to.
Transmission
Once the LOCK bit of a Buffer Control/Status Register (BCSRx) has been set and read back as such, a transmit job can be submitted by writing to the DATA7 register. The message with the highest priority will be transmitted as soon as the CAN bus becomes idle. Among those messages with a pending transmission request, the highest priority is given to Buffer 3, then
2 and 1. If the transmission fails due to a lost arbitration or to an error while the NRTX bit of the CSR register is reset, then a new transmission attempt is performed. This goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by setting the NRTX bit or if the node ever enters bus-off or if a higher priority message becomes pending. The RDY bit in the BCSRx register, which was set since the job was submitted, gets reset. When a transmission is in progress, the BUSY bit in the BCSRx register is set. If it ends successfully then the TXIF bit in the Interrupt Status Register (ISR) is set, otherwise the TEIF bit is set. An interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
Setting the SRTE bit of the CSR register allows transmitted messages to be simultaneously received when they pass the acceptance filtering. This is particularly useful for checking the integrity of the communication path.
Reception
Once the CAN controller has synchronized itself onto the bus activity, it is ready for reception of new messages. The identifier of every incoming message is compared to the acceptance filters. If the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. This buffer will be the first one - order is 1 to 3 - that has the LOCK and RDY bits of its BCSRx register reset.
● When no such buffer exists then an overrun interrupt is generated if the ORIE bit of the
ICR register has been set. In this case the identifier of the last message is made available in the Last Identifier Register (LIDHR and LIDLR) at least until it is overwritten by a new identifier picked-up from the bus.
● When a buffer does exist, the accepted message gets written into it, the ACC bit in the
BCSRx register gets the number of the matching filter, the RDY and RXIF bits get set and an interrupt is generated if the RXIE bit in the ISR register is set.
Up to three messages can be automatically received without intervention from the CPU because each buffer has its own set of status bits, greatly reducing the reactiveness requirements in the processing of the receive interrupts.
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Error
The error management as described in the CAN protocol is completely handled by hardware using two error counters which are incremented or decremented according to the error condition. Both of them may be read by the application to determine the stability of the network. Moreover, as one of the node status bits (EPSV or BOFF of the CSR register) changes, an interrupt is generated if the SCIE bit is set in the ICR Register. Refer to
.
Figure 73.
CAN error state diagram
When TECR or RECR > 127, the EPSV bit is set
ERROR ACTIVE
ERROR PASSIVE
When 128 * 11 recessive bits occur:
- the BOFF bit is cleared
- the TECR register is cleared
- the RECR register is cleared
When TECR and RECR < 128, the EPSV bit is cleared
When TECR > 255, the BOFF bit is set and the EPSV bit is cleared
BUS OFF
17.3.4 Bit timing logic
The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on following edges.
Explaining its operation is simplified when the nominal bit time is divided into segments as follows:
●
●
Synchronization segment (SYNC_SEG) : A bit change is expected to lie within this time segment. It has a fixed length of one time quanta (1 x t
CAN
).
Bit segment 1 (BS1) : Defines the location of the sample point. It includes the
PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network.
● Bit segment 2 (BS2) : Defines the location of the transmit point. It represents the
PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts.
● Resynchronization Jump Width (RJW) : Defines an upper boundary to the amount of lengthening or shortening of the bit segments. It is programmable between 1 and 4 time quanta.
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Controller area network (CAN) ST72521xx-Auto
To guarantee the correct behavior of the CAN controller, SYNC_SEG + BS1 + BS2 must be greater than or equal to 5 time quanta.
The CAN controller resynchronizes on recessive to dominant edges only.
For a detailed description of the CAN resynchronization mechanism and other bit timing configuration constraints, please refer to the Bosch CAN standard 2.0.
As a safeguard against programming errors, the configuration of the Bit Timing Register
(BTR) is only possible while the device is in Standby mode.
Figure 74.
Bit timing
SYNC_SEG
1 x t
CAN
NOMINAL BIT TIME
BIT SEGMENT 1 (BS1) t
BS1
SAMPLE POINT
BIT SEGMENT 2 (BS2) t
BS2
TRANSMIT POINT
The CAN registers are organized as 6 general purpose registers plus 5 pages of 16 registers spanning the same address space and primarily used for message and filter storage. The page actually selected is defined by the content of the Page Selection
Register.
17.4.1 General purpose registers
Interrupt status register (ISR)
ISR
7
RXIF3
RC
6
RXIF2
RC
5
RXIF1
RC
4
TXIF
RC
3
SCIF
RC
2
ORIF
RC
1
Reset value: 00h
0
TEIF
RC
EPND
RO
2
Table 91.
ISR register description
Bit Name Function
7 RXIF3
Receive Interrupt Flag for Buffer 3
Set by hardware to signal that a new error-free message is available in buffer 3.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
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ST72521xx-Auto Controller area network (CAN)
Table 91.
ISR register description (continued)
Bit Name Function
6 RXIF2
Receive Interrupt Flag for Buffer 2
Set by hardware to signal that a new error-free message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
5 RXIF1
Receive Interrupt Flag for Buffer 1
Set by hardware to signal that a new error-free message is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
4 TXIF
3 SCIF
Transmit Interrupt Flag
Set by hardware to signal that the highest priority message queued for transmission has been successfully transmitted.
Cleared by software.
Status Change Interrupt Flag
Set by hardware to signal the reception of a dominant bit while in standby mode. In
Cleared by software.
2 ORIF
Overrun Interrupt Flag
Set by hardware to signal that a message could not be stored because no receive buffer was available.
Cleared by software.
1 TEIF
Transmit Error Interrupt Flag
Set by hardware to signal that an error occurred during the transmission of the highest priority message queued for transmission.
Cleared by software.
0 EPND
Error Interrupt Pending
Set by hardware when at least one of the three error interrupt flags SCIF, ORIF or
TEIF is set.
Reset by hardware when all error interrupt flags have been cleared.
Caution: Interrupt flags are reset by writing a ‘0’ to the corresponding bit position. The appropriate way consists in writing an immediate mask or the one’s complement of the register content initially read by the interrupt handler. Bit manipulation instruction BRES should never be used due to its read-modify-write nature.
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Controller area network (CAN) ST72521xx-Auto
Interrupt control register (ICR)
ICR
7
Reserved
-
6
ESCI
RSC
5
RXIE
RSC
4
TXIE
RSC
3
SCIE
RSC
2
ORIE
RSC
1
Reset value: 00h
0
TEIE
RSC
Reserved
-
Table 92.
ICR register description
Bit Name Function
7 Reserved; must be kept at ‘0’
6 ESCI
Extended Status Change Interrupt
Set by software to specify that SCIF is to be set on receive errors also.
Cleared by software to set SCIF only on status changes and wake-up but not on all receive errors.
5 RXIE
Receive Interrupt Enable
Set by software to enable an interrupt request whenever a message has been received free of errors.
Cleared by software to disable receive interrupt requests.
4 TXIE
Transmit Interrupt Enable
Set by software to enable an interrupt request whenever a message has been successfully transmitted.
Cleared by software to disable transmit interrupt requests.
3 SCIE
Status Change Interrupt Enable
Set by software to enable an interrupt request whenever the node’s status changes in run mode or whenever a dominant pulse is received in standby mode.
Cleared by software to disable status change interrupt requests.
2 ORIE
Overrun Interrupt Enable
Set by software to enable an interrupt request whenever a message should be stored and no receive buffer is available.
Cleared by software to disable overrun interrupt requests.
1 TEIE
Transmit Error Interrupt Enable
Set by software to enable an interrupt whenever an error has been detected during transmission of a message.
Cleared by software to disable transmit error interrupts.
0 Reserved; must be kept at ‘0’
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ST72521xx-Auto Controller area network (CAN)
Control/Status register (CSR)
CSR
7
Reserved
-
6
BOFF
RO
5
EPSV
RO
4
SRTE
RSC
3
NRTX
RSC
2
FSYN
RSC
1
Reset value: 00h
0
WKPS
RSC
RUN
RSC
Table 93.
CSR register description
Bit Name Function
7 Reserved; must be kept at ‘0’
6 BOFF
Bus-Off State
Set by hardware to indicate that the node is in bus-off state, that is, the Transmit Error
Counter exceeds 255.
Reset by hardware to indicate that the node is involved in bus activities.
5 EPSV
Error Passive State
Set by hardware to indicate that the node is error passive.
Reset by hardware to indicate that the node is either error active (BOFF = 0) or busoff.
4 SRTE
Simultaneous Receive/Transmit Enable
Set by software to enable simultaneous transmission and reception of a message passing the acceptance filtering. Allows to check the integrity of the communication path.
Reset by software to discard all messages transmitted by the node. Allows remote and data frames to share the same identifier.
3 NRTX
No Retransmission
Set by software to disable the retransmission of unsuccessful messages. It does not stop transmission in case of Arbitration Lost.
Cleared by software to enable retransmission of messages until success is met.
2 FSYN
Fast Synchronization
Set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 recessive bits in a row.
Cleared by software to enable the standard resynchronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits.
1 WKPS
Wake-up Pulse
Set by software to generate a dominant pulse when leaving standby mode.
Cleared by software for no dominant wake-up pulse.
0 RUN
CAN Enable
Set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11 recessive bits if FSYN is set.
Cleared by software to request a switch to the standby or low-power mode as soon as any on-going transfer is complete. Read-back as 1 in the meantime to enable proper signalling of the standby state. The CPU clock may therefore be safely switched OFF whenever RUN is read as 0.
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Controller area network (CAN)
Note:
Note:
ST72521xx-Auto
Baud rate prescaler register (BRPR)
BRPR
7 6
RJW[1:0]
R/W_Standby mode
5 4 3 2
BRP[5:0]
R/W_Standby mode
1
Reset value: 00h
0
Table 94.
BRPR register description
Bit Name Function
7:6 RJW[1:0]
Resynchronization Jump Width
These bits determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization.
t
RJW
= t
CAN
* (RJW + 1)
5:0 BRP[5:0]
Baud rate prescaler
These bits determine the CAN system clock cycle time or time quanta which is used to build up the individual bit timing.
t
CAN
= t
CPU
* (BRP + 1)
Where t
CPU
= time period of the CPU clock.
The resulting baud rate can be computed by the formula:
BR = t
CPU
BRP + 1
1
BS1 + BS2 + 3
Writing to this register is allowed only in Standby mode to prevent any accidental CAN protocol violation through programming errors.
Bit timing register (BTR)
BTR
7
Reserved
-
6 5
BS2[2:0]
R/W_Standby mode
4 3 2 1
Reset value: 23h
0
BS1[3:0]
R/W_Standby mode
Table 95.
BTR register description
Bit Name Function
7 Reserved; must be kept at ‘0’
6:4 BS2[2:0]
3:0 BS1[3:0]
Bit Segment 2
These bits determine the length of Bit Segment 2.
t
BS2
= t
CAN
* (BS2 + 1)
Bit Segment 1
These bits determine the length of Bit Segment 1.
t
BS1
= t
CAN
* (BS1 + 1)
Writing to this register is allowed only in Standby mode to prevent any accidental CAN protocol violation through programming errors.
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ST72521xx-Auto Controller area network (CAN)
Page selection register (PSR)
PSR
7 6 5
Reserved
-
4 3 2 1
Reset value: 00h
0
PAGE[2:0]
R/W
Table 96.
PSR register description
Bit Name Function
7:3 Reserved; must be kept at ‘0’
2:0 PAGE[2:0]
Page Selection
These bits determine which buffer or filter page is mapped at addresses 0010h to
001Fh.
000:Page title = Diagnosis
001:Page title = Buffer 1
010:Page title = Buffer 2
011:Page title = Buffer 3
100:Page title = Filters
101:Page title = Reserved
110:Page title = Reserved
111:Page title = Reserved
Last identifier high register (LIDHR)
LIDHR
7 6 5 4 3 2
Reset value: Undefined
1 0
LID[10:3]
R/W
Table 97.
LIDHR register description
Bit Name Function
7:0 LID[10:3]
Last Identifier (MSB)
These are the most significant 8 bits of the last Identifier read on the CAN bus.
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Controller area network (CAN) ST72521xx-Auto
Last identifier low register (LIDLR)
LIDLR
7 6
LID[2:0]
R/W
5 4
LRTR
R/W
3 2
Reset value: Undefined
1 0
LDLC[3:0]
R/W
Table 98.
LIDLR register description
Bit Name Function
7:5
4
LID[2:0]
LRTR
Last Identifier (LSB)
These are the least significant 3 bits of the last Identifier read on the CAN bus.
Last Remote Transmission Request
This is the last Remote Transmission Request bit read on the CAN bus.
3:0 LDLC[3:0]
Last Data Length Code
This is the last Data Length Code read on the CAN bus.
Transmit error counter register (TECR)
TECR
7 6 5 4 3 2 1
Reset value: 00h
0
TEC[7:0]
RO
Table 99.
TECR register description
Bit Name Function
7:0 TEC[7:0]
Transmit Error Counter
This is the least significant byte of the 9-bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during transmission, this counter is incremented by 8. It is decremented by 1 after every successful transmission. When the counter value exceeds 127, the CAN controller enters the error passive state. When a value of 256 is reached, the CAN controller is disconnected from the bus.
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ST72521xx-Auto Controller area network (CAN)
Receive error counter register (RECR)
RECR
7 6 5 4 3 2 1
Reset value: 00h
0
REC[7:0]
RO
Table 100.
RECR register description
Bit Name Function
7:0 REC[7:0]
Receive Error Counter
This is the Receive Error Counter implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the
CAN standard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive state.
Identifier high registers (IDHRx)
IDHRx
7 6 5 4 3 2
Reset value: Undefined
1 0
ID[10:3]
R/W
Table 101.
IDHRx register description
Bit Name
7:0 ID[10:3]
Function
Message Identifier (MSB)
These are the most significant 8 bits of the 11-bit message identifier. The identifier acts as the message’s name, used for bus access arbitration and acceptance filtering.
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Controller area network (CAN) ST72521xx-Auto
Identifier low registers (IDLRx)
IDLRx
7 6
ID[2:0]
R/W
5 4
RTR
R/W
3 2
Reset value: Undefined
1 0
DLC[3:0]
R/W
Table 102.
IDLRx register description
Bit Name Function
7:5
4
ID[2:0]
RTR
Message Identifier (LSB)
These are the least significant 3 bits of the 11-bit message identifier.
Remote Transmission Request
This bit is set to indicate a remote frame and reset to indicate a data frame.
3:0 DLC[3:0]
Data Length Code
It gives the number of bytes in the data field of the message. The valid range is 0 to 8.
Data registers (DATA0-7x)
DATA0-7x
7 6 5 4 3 2
Reset value: Undefined
1 0
DATA[7:0]
R/W
Table 103.
DATA0-7x register description
Bit Name Function
7:0 DATA[7:0]
Message Data
DATA[7:0] is a message data byte. Up to eight such bytes may be part of a message. Writing to byte DATA7 initiates a transmit request and should always be done even when DATA7 is not part of the message.
190/276 Doc ID 17660 Rev 1
ST72521xx-Auto Controller area network (CAN)
Buffer control/status registers (BCSRx)
BCSRx
7 6
Reserved
-
5 4 3
ACC
RO
2
RDY
RC
1
Reset value: 00h
0
BUSY
RO
LOCK
RSC
Table 104.
BCSRx register description
Bit Name
7:4
3
2
1
0
-
ACC
RDY
BUSY
LOCK
Function
Reserved; must be kept at ‘0’
Acceptance Code
Set by hardware with the message identifier of the highest priority filter which accepted the message stored in the buffer.
0: Match for Filter/Mask0. Possible match for Filter/Mask1.
1: No match for Filter/Mask0 and match for Filter/Mask1.
Reset by hardware when either RDY or RXIF is reset.
Message Ready
Set by hardware to signal that a new error-free message is available (LOCK = 0) or that a transmission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release the buffer and to clear the corresponding RXIF bit in the Interrupt Status Register.
Cleared by hardware when LOCK = 1 to indicate that the transmission request has been serviced or cancelled.
Busy Buffer
Set by hardware when the buffer is being filled (LOCK = 0) or emptied (LOCK = 1) and reset after the 2nd intermission bit.
Reset by hardware when the buffer is not accessed by the CAN core for transmission nor reception purposes.
Lock Buffer
Set by software to lock a buffer. No more message can be received into the buffer thus preserving its content and making it available for transmission.
Cleared by software to make the buffer available for reception. Cancels any pending transmission request.
Cleared by hardware once a message has been successfully transmitted provided the early transmit interrupt mode is on. Left untouched otherwise.
Note that in order to prevent any message corruption or loss of context, LOCK cannot be set nor reset while BUSY is set. Trying to do so will result in LOCK not changing state.
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Controller area network (CAN) ST72521xx-Auto
Filter high registers (FHRx)
FHRx
7 6 5 4 3 2
Reset value: Undefined
1 0
FIL[11:4]
R/W
Table 105.
FHRx register description
Bit Name Function
7:0 FIL[11:4]
Acceptance Filter
These are the most significant 8 bits of a 12-bit message filter. The acceptance filter is compared bit by bit with the identifier and the RTR bit of the incoming message. If there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer.
Filter low registers (FLRx)
FLRx
7 6
FIL[3:0]
R/W
5 4 3 2
Reset value: Undefined
1 0
Reserved
-
Table 106.
FLRx register description
Bit Name
7:4 FIL[3:0]
3:0 -
Function
Acceptance Filter
These are the least significant 4 bits of a 12-bit message filter.
Reserved; must be kept at ‘0’
Mask high registers (MHRx)
MHRx
7 6 5 4
MSK[11:4]
R/W
3 2
Reset value: Undefined
1 0
Table 107.
MHRx register description
Bit Name Function
7:0 MSK[11:4]
Acceptance Mask
These are the most significant 8 bits of a 12-bit message mask. The acceptance mask defines which bits of the acceptance filter should match the identifier and the RTR bit of the incoming message.
MSK[i] = 0: Don’t care
MSK[i] = 1: Match required
192/276 Doc ID 17660 Rev 1
ST72521xx-Auto Controller area network (CAN)
Mask low registers (MLRx)
MLRx
7 6
MSK[3:0]
R/W
5 4 3 2
Reset value: Undefined
1 0
Reserved
-
Table 108.
MLRx register description
Bit Name Function
7:4 MSK[3:0]
Acceptance Mask (LSB)
These are the least significant 4 bits of a 12-bit message mask.
3:0 Reserved; must be kept at ‘0’
Figure 75.
CAN register map
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
Interrupt Status
Interrupt Control
Control/Status
Baud Rate Prescaler
Bit Timing
Page Selection
6Fh
Paged Reg1
Paged Reg1
Paged Reg0
Paged Reg1
Paged Reg2
Paged Reg2
Paged Reg3
Paged Reg3 Paged Reg4
Paged Reg3
Paged Reg5
Paged Reg4
Paged Reg5
Paged Reg5 Paged Reg6
Paged Reg7
Paged Reg6
Paged Reg8
Paged Reg7
Paged Reg9
Paged Reg9
Paged Reg10
Paged Reg9
Paged Reg11
Paged Reg11 Paged Reg10
Paged Reg11
Paged Reg11 Paged Reg12
Paged Reg13
Paged Reg14 Paged Reg12
Paged Reg13
Paged Reg13
Paged Reg15
Paged Reg15
Paged Reg15
Paged Reg15
Doc ID 17660 Rev 1 193/276
Controller area network (CAN)
Figure 76.
Page maps
64h
65h
66h
67h
68h
69h
6Ah
60h
61h
62h
63h
6Bh
6Ch
6Dh
6Eh
6Fh
PAGE 0
LIDHR
LIDLR
Reserved
TECR
RECR
Diagnosis
Reserved
BCSR1
Buffer 1
PAGE 1
IDHR1
IDLR1
DATA01
DATA11
DATA21
DATA31
DATA41
DATA51
DATA61
DATA71
PAGE 2
IDHR2
IDLR2
DATA02
DATA12
DATA22
DATA32
DATA42
DATA52
DATA62
DATA72
Reserved
BCSR2
Buffer 2
ST72521xx-Auto
PAGE 3
IDHR3
IDLR3
DATA03
DATA13
DATA23
DATA33
DATA43
DATA53
DATA63
DATA73
Reserved
PAGE 4
FHR0
FLR0
MHR0
MLR0
FHR1
FLR1
MHR1
MLR1
Reserved
BCSR3
Buffer 3 Acceptance Filters
194/276 Doc ID 17660 Rev 1
ST72521xx-Auto Controller area network (CAN)
Table 109.
CAN register map and reset values
Address
(Hex.)
Page
Register label
7 6
5A
5B
5C
5D
5E
5F
60
60, 64
0
4
CANISR
Reset value
CANICR
Reset value
CANCSR
Reset value
CANBRPR
Reset value
CANBTR
Reset value
CANPSR
Reset value
CANLIDHR
Reset value
1 to 3
CANIDHRx
Reset value
CANFHRx
Reset value
61
0
CANLIDLR
Reset value
1 to 3
CANIDLRx
Reset value
61, 65
63, 67
4
4
CANFLRx
Reset value
62 to 69 1 to 3
62, 66 4
CANDRx
Reset value
CANMHRx
Reset value
CANMLRx
Reset value
6E
6F
0
CANTECR
Reset value
CANRECR
Reset value
1 to 3
CANBCSRx
Reset value
RXIF3
0
0
0
RJW1
0
0
MSB x
MSK11 x
MSK3 x
MSB
0
MSB
0
LID2 x
ID2 x
FIL3 x
0
LID10 x
ID10 x
FIL11 x
0 x
MSK10 x
MSK2 x
0
0
0
RXIF2
0
ESCI
0
BOFF
0
RJW0
0
BS22
0
LID1 x
ID1 x
FIL2 x
0
LID9 x
ID9 x
FIL10 x
5
RXIF1
0
RXIE
0
EPSV
0
BRP5
0
BS21
1 x
MSK9 x
MSK1 x
0
0
0
LID0 x
ID0 x
FIL1 x
0
LID8 x
ID8 x
FIL9 x
4 3 2 1 0
LRTR x
RTR x
FIL0 x
0
LID7 x
ID7 x
FIL8 x
TXIF
0
TXIE
0
SRTE
0
BRP4
0
BS20
0
SCIF
0
SCIE
0
NRTX
0
BRP3
0
BS13
0
0
LID6 x
ID6 x
FIL7 x
LDLC3 x
DLC3 x
BS12
0
PAGE2
0
LID5 x
ID5 x
FIL6 x
LDLC2 x
DLC2 x
ORIF
0
ORIE
0
FSYN
0
BRP2
0
BS10
1
PAGE0
0
LID3 x
ID3 x
FIL4 x
LDLC0 x
DLC0 x
EPND
0
ETX
0
RUN
0
BRP0
0
BS11
1
PAGE1
0
LID4 x
ID4 x
FIL5 x
LDLC1 x
DLC1 x
TEIF
0
TEIE
0
WKPS
0
BRP1
0
0 0 0 x
MSK8 x
MSK0 x x
MSK7 x
0 x
MSK6 x
0 x
MSK5 x
0
0
LSB x
MSK4 x
0
0
0
0
0
ACC
0
0
0
RDY
0
0
0
BUSY
0
0
LSB
0
LSB
0
LOCK
0
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Controller area network (CAN)
17.5 List of CAN cell limitations
ST72521xx-Auto
Symptom
Start of Frame (SOF) bit is omitted if transmission is requested in the last Intermission bit.
Details
The IUT is requested to start transmission immediately after the completion of the previous transmission. The LT also starts its transmission and asserts the SOF bit just after the 3 rd
Intermission bit. The IUT also starts transmission but omits the SOF bit. The IUT wins the arbitration and continues the transmission. The frame is sent correctly.
Impact on the application
As this effect only occurs when the IUT detects a SOF bit on the CAN bus, the fact that it omits its own SOF bit has no impact on the communication.
17.5.2 CPU write access (more than one cycle) corrupts CAN frame
Symptoms
For CAN received messages the identifier high byte or last data byte can be corrupted.
For CAN transmitted messages the 2nd data byte can be corrupted.
Details
The CAN transmit and receive buffers are implemented as dual ported RAM. During the reception of a CAN frame the CAN core writes the received identifier and the data byte-bybyte in the corresponding buffer.
IF the CAN bit timing configuration is t
BS2
< 5 time quanta
AND
IF concurrently with the pCAN, the CPU executes a write access to the dual ported RAM using an instruction with more than one cycle access, e.g. CLR, BSET, BRES
THEN the access conflict can lead to the corruption described in the symptoms paragraph above.
Impact on the application
Several CAN frames with erroneous data or identifier will be received/transmitted.
Software workaround
Program t
BS2
> 4 time quanta or, when accessing the receive or transmit buffers, do not use the critical instructions which are:
BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC, SLL, SRL, RRC, SRA, SWAP.
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ST72521xx-Auto Controller area network (CAN)
17.5.3 Unexpected message transmission
Symptom
The previous message received by pCAN, even if this message did not pass the receive filter, will be retransmitted by pCAN with a correct identifier and DLC but with corrupted data.
The data bytes will be a copy of the identifier bytes IDHR and IDLR in the following repetitive pattern:
DATA_0 = IDHR
DATA_1 = IDLR
DATA_2 = IDHR
DATA_3 = IDLR etc.
DATA_7 = IDLR
If no message has been received before the problem occurs then identifier byte values are random but the data bytes are in the same repetitive pattern.
Details
The buffers of the pCAN cell are configurable as receive or transmit buffers. By default, all buffers are configured in reception. To use a buffer to transmit a CAN message the application has to reserve this buffer for transmission by setting the LOCK bit in the BCSR register. So the buffer is then locked for any further reception and reserved for transmission.
Once a transmission has been requested by a write access to data byte 7 of the buffer the application might need to abort this transmission request. To do so, the application can reset the LOCK bit in the BCSR register.
If the message is pending (RDY bit set) but not currently being transmitted, then clearing the
LOCK bit will abort it immediately.
If the message is pending (RDY bit set) and currently being transmitted then the message will not be interrupted but the CAN core will wait until the end of this transmission attempt.
Then software must clear the LOCK bit again to abort the transmission.
An unexpected transmission can occur:
IF the application resets the LOCK bit
WHILE the CAN core is preparing the transmission
(a)
AND there is no other transmission pending in another buffer
THEN the LOCK bit is reset but the transmission is not stopped. Instead the content of the page 0 buffer will be transmitted.
Impact on the application
pCAN will echo some messages sent by other nodes. Identifier and DLC will be correct but data are corrupted as described previously.
a.
The preparation lasts two bit times just before SOF; this is the critical window during which the LOCK bit must not be reset by the application.
Doc ID 17660 Rev 1 197/276
Controller area network (CAN) ST72521xx-Auto
Software workaround - devices with hardware fix (ST72F521 rev “R”)
To implement a transmission abort under safe conditions, the LOCK bit must not be reset during the critical window (2 bit times). A new function has been implemented in the MCU allowing the application to synchronize the reset of the LOCK bit (abort request) with the reset of the TXRQST bit (internal signal) in the pCAN core.
The synchronization is done using the WKPS bit in the CANCSR register, the function of this bit has been modified and no more Wake-up Pulse (dominant bit) is sent on the CAN_TX signal when the WKPS bit is set. This means the functionality described in the datasheet is
no longer applicable (see Section 17.5.4: WKPS functionality ).
To abort the transmission, the application first sets the WKPS bit and polls it until it is set.
The maximum time needed to set this bit is two CAN bit times. Once the application has read the WKPS bit as one, it can reset the LOCK bit to stop the current transmission.
The abort is completed when the LOCK bit is read back as zero by the application. Once the abort has been completed, the application must reset the WKPS bit to be able to transmit again. Of course the transmit buffer must be in LOCK state as usual before any transmission attempt.
The “C” code sequence below shows the software workaround using the WKPS bit.
CANCSR |= WKPS;// Set WKPS bit while(!(CANCSR & WKPS) );// Wait until WKPS bit is set while( CANBCSR & LOCK )// Wait until abort has been confirmed
{
CANBCSR &= ~LOCK;
}
CANCSR &= ~WKPS; // Allow transmission again
CANBCSR |= LOCK; //Alloc buffer for next transmission
Software workaround - devices without hardware fix
To implement a transmission abort under safe conditions, any reset of the LOCK bit during the critical window (2 bit times) must be avoided. Two different cases have to be considered, either the pCAN enters standby mode after the abort, or the abort is performed and pCAN keeps running.
Abort followed by Standby mode (RUN = 0)
In this case, aborting the pending transmissions can safely be done by first entering
Standby mode and then releasing the transmit buffers. Standby mode is entered by resetting the RUN bit in the CSR register and once the current transmission attempt, even if it fails due to error or lost arbitration, has been performed, pCAN enters Standby mode (RUN = 0).
Once in Standby mode the application can abort all pending transmissions by resetting the corresponding LOCK bit.
Abort while staying in RUN mode (RUN = 1)
Contrary to the STANDBY case described previously, in the RUN case the application has to handle the error or arbitration lost conditions. In case of transmission errors, causing the frame to be transmitted again and again, the application must set the NRTX bit in the CSR register. This will cause pCAN to abort the transmission at the end of the current attempt.
In case of arbitration lost, setting the NRTX bit does not abort the transmission, therefore the application must reset the LOCK bit to abort the transmission. To avoid resetting the LOCK bit during the critical time window, leading to the problem described at the start of this
198/276 Doc ID 17660 Rev 1
ST72521xx-Auto Controller area network (CAN) section, the application must monitor the BUSY bit in the BCSR register and reset the LOCK bit just after the falling edge of the BUSY bit. The time between the falling edge of the BUSY bit and the SOF of the next transmission attempt is in any case long enough to guarantee that the LOCK bit is reset before the critical time window.
The “C” code sequence below shows the software workaround for both the error and arbitration lost cases.
_asm("SIM\n"); // Mask interrupts
CANCSR |= NRTX;// Set non automatic retransmission bit while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set
(CANBCSR & RDY) ); // or transmission done while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge) if( CANBCSR & RDY )
{ // transmission still pending -> must be aborted
CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safely while( CANBCSR & RDY );// Wait for unlock confirmed
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n");
} else
{ // No more abort required as RDY bit already reset
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n"); // Enable interrupts
}
Doc ID 17660 Rev 1 199/276
Controller area network (CAN)
Figure 77.
Workaround flowchart
Application Requests an Abort
YES
MASK INT
READY == 1
SET NRTX
NO
YES
BUSY == 0
AND
READY == 1
YES
NO
BUSY == 0
NO
NO
YES
READY == 1
RESET LOCK
ST72521xx-Auto
NO
READY == 1
YES
SET LOCK
RESET NRTX
ENABLE INT
Abort Done
The figures below show the abort behavior in the four possible cases.
Figure 78.
Abort and successful transmission
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
In this case the abort request performed during the transmission has no effect, as the first transmission is successful.
200/276 Doc ID 17660 Rev 1
ST72521xx-Auto Controller area network (CAN)
Figure 79.
Abort and transmission delayed by busy CAN bus
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
In this case the NRTX bit is set to abort the transmission after the first attempt. As the first attempt is successful the READY and BUSY bits are reset by pCAN and the transmit buffer becomes empty. An abort is no longer required.
Figure 80.
Abort and error during transmission
Error
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
In this case NRTX (abort request) is set before the error, thus pCAN resets READY and
BUSY after the error (the first attempt). The abort has been successful and the transmit buffer is empty.
Figure 81.
Abort and arbitration lost
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
In this case the NRTX bit is set but has no effect, as the previous transmission attempt failed due to an arbitration lost. The application waits for the falling edge of BUSY bit and checks that READY is still set. This is the case, this means pCAN has lost the arbitration and LOCK bit can be safely reset. Abort is immediate and pCAN resets the READY and BUSY bits.
Timing considerations
As no interrupt signals that an abort has been successful, the application has to wait until the transmit buffer is empty (transmission has been aborted or transmitted successfully).
This time can vary depending on the case in which the abort is performed (arbitration lost, error or successful transmission). To show the impact of the software workaround on this
timing behavior Figure 82 and Figure 83
compare the reference behavior (worst case when abort is done by LOCK only) with the behavior when NRTX, BUSY and LOCK bits are used.
Doc ID 17660 Rev 1 201/276
Controller area network (CAN) ST72521xx-Auto
Figure 82.
Abort by LOCK only - reference behavior
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
The worst case is when the abort request is done when the transmission has just started. In this case the LOCK bit cannot be reset as long as the BUSY bit is set, this means until the end of the frame. So the application will wait for READY to be reset during the whole frame and in this case the worst case will be the longest frame the application is expected to transmit.
Figure 83.
Abort with the software workaround - by NRTX, BUSY and LOCK
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
Using the software workaround the worst case occurs in the arbitration lost case. If the abort is requested just after pCAN has lost the arbitration then the application has to wait for the next falling edge of the BUSY bit before the LOCK bit can be reset. If the next arbitration is won by pCAN then the BUSY bit will be reset by the end of the successful transmission. The longest time the application has to wait in this case is the time of the longest message expected on the bus (minus identifier) plus the longest message expected to be transmitted by the application. This roughly double the time the application may have to wait before the abort sequence is performed.
Due to a fix implemented to solve the “Unexpected Message Transmission” issue (see
Section 17.5.3: Unexpected message transmission ) the WKPS functionality has been
modified as follows in Flash ST72F521 devices:
Table 110.
WKPS functionality modifications
Device Modification
Flash ST72F521 Rev R
WKPS bit does not generate a wake-up pulse. It is used to synchronize the reset of the LOCK bit (see Software workaround - devices with hardware fix (ST72F521 rev “R”) on page 198 ).
ROM ST72521 All revisions WKPS bit functions according to the datasheet description.
202/276 Doc ID 17660 Rev 1
ST72521xx-Auto Controller area network (CAN)
17.5.5 Bus-off state not entered
Symptom
pCAN does not enter bus-off state under certain conditions. This is fixed in Flash version of
ST72F521 starting from silicon Rev R and in ROM version ST72521B starting from silicon
Rev Y.
Details
According to the CAN standard, pCAN is expected to enter bus-off state when TEC
(Transmit Error Counter) is greater than 255.
However, if REC (Receive Error Counter) is greater than 127 (Error Passive State) pCAN does not enter bus-off and the BOFF bit of the CSR register is not set. To enter bus-off, REC must decrease to a value lower than 128; this is the case with any correct reception even if the message is filtered out.
As bus-off state is not entered and pCAN still attempts to transmit its message, after the overflow the TEC register continues to increment as long as transmission errors occur.
Impact on the application
The application will not stop attempting to transmit CAN messages, even when the bus-off conditions have been reached, until the transmission has been successful or the value of
REC becomes lower than 128. However the application will not disturb the communication of the other nodes on the CAN network as pCAN is in Error Passive State.
Figure 84.
CAN error state diagram showing “BUSOFF not entered” limitation
When TECR or RECR > 127, the EPSV bit is set
ERROR ACTIVE
ERROR PASSIVE
When 128 * 11 recessive bits occur:
- the BOFF bit is cleared
- the TECR register is cleared
- the RECR register is cleared
When TECR and RECR < 128, the EPSV bit is cleared
When TECR > 255 and RECR < 128 the BOFF bit
is set and the EPSV bit is cleared
BUS OFF
Doc ID 17660 Rev 1 203/276
Controller area network (CAN) ST72521xx-Auto
Workaround
The bus-off entry works correctly in almost all cases, only when REC is greater than 127 a bus-off will not be recognized by pCAN. Therefore the pCAN bus-off signalling (BOFF) is still used but it needs to be complemented by monitoring TEC by software.
To detect the bus-off condition by software the application has to monitor the value of the
TEC register periodically. An overflow signals a bus-off condition. When a bus-off condition has been detected the application must execute the following sequence to recover from busoff properly: The application stops pCAN by clearing the RUN bit in the CANCSR register, resets all pending transmission by clearing the LOCK bit in the BCSR register and starts it again by setting the RUN bit.
To detect the bus-off condition properly, the TEC monitoring period must be lower than the time between two overflows. As the problem only occurs when pCAN is in Error Passive
State (REC > 127) pCAN will continuously try to send a SOF followed by an Error Passive
Flag and a Suspend Transmission. This leads to 26 (1 + 6 + 8 + 3 + 8) bit times. Each time
TEC is incremented by 8, hence to reach 256 the sequence must be executed 32 times.
Under these conditions the shortest sequence leading to a TEC overflow lasts 832 bit times.
Depending on the baudrate, the application will have to adapt the monitoring period (for example, at 500kbps the period must be less than 1600µs).
The ‘C’ code below shows an implementation example of the monitoring sequence. This code is called periodically as described above.
To detect the overflow, the test condition must take into account that TEC might also have been decremented due to a successful transmission. So an overflow condition is detected:
IF the current TEC value is lower than the previous TEC value
AND the difference is greater than the number of possible successful transmissions during the monitoring period.
In the example above, one message can be sent, therefore one is added to CANTECR.
*
***********************************************/
/* INITIALIZATION
/************************************************/ unsigned char TECReg=0; //Previous value of TEC unsigned char BusOffFlag=0; //Set to one if bus-off
/************************************************/
/* BUS-OFF MONITORING SEQUENCE
/************************************************/ if( (CANCSR & BOFF) || ( CANTECR+1 < TECReg) )
{
BusOffFlag = 1;
} else
{
TECReg = CANTECR;
}
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ST72521xx-Auto
18 10-bit A/D converter (ADC)
10-bit A/D converter (ADC)
18.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is controlled through a control/status register.
●
●
●
●
●
●
10-bit conversion
Up to 16 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in
Figure 85.
ADC block diagram f
CPU DIV 4
DIV 2
0
1 f
ADC
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR
4
AIN0
AIN1
AINx
ANALOG
MUX
ANALOG TO DIGITAL
CONVERTER
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
ADCDRL 0 0 0 0 0 0 D1 D0
Doc ID 17660 Rev 1 205/276
10-bit A/D converter (ADC) ST72521xx-Auto
The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.
If the input voltage (V
AIN
) is greater than V
AREF
(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).
If the input voltage (V
AIN
) is lower than V
SSA
(low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Section 20:
.
R
AIN
is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allotted time.
18.3.1 A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
Chapter 9: I/O ports . Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register:
● Select the CS[3:0] bits to assign the analog channel to convert.
18.3.2 Starting the conversion
Note:
In the ADCCSR register:
● Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
●
The EOC bit is set by hardware.
The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1.
Poll the EOC bit.
2. Read the ADCDRL register.
3. Read the ADCDRH register. This clears EOC automatically.
The data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result.
To read only 8 bits, perform the following steps:
1.
Poll the EOC bit.
2. Read the ADCDRH register. This clears EOC automatically.
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ST72521xx-Auto 10-bit A/D converter (ADC)
18.3.3 Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.
18.4 Low power modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.
Table 111.
Effect of low power modes on ADC
Mode Effect
Wait
Halt
No effect on A/D converter
A/D converter disabled.
After wake-up from Halt mode, the A/D converter requires a stabilization time t
STAB
(see
Section 20: Electrical characteristics
) before accurate conversions can be performed.
18.5 Interrupts
None.
18.6.1 Control/status register (ADCCSR)
ADCCSR
7
EOC
RO
6
SPEED
RW
5
ADON
RW
4
Reserved
-
3 2
Reset value: 0000 0000 (00h)
1 0
CH[3:0]
RW
Table 112.
ADCCSR register description
Bit Name Function
7 EOC
End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
6 SPEED
ADC clock selection
This bit is set and cleared by software.
0: f
ADC
= f
CPU
/4
1: f
ADC
= f
CPU
/2
Doc ID 17660 Rev 1 207/276
10-bit A/D converter (ADC) ST72521xx-Auto
Table 112.
ADCCSR register description (continued)
Bit Name Function
5 ADON
A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
4 Reserved. Must be kept cleared
3:0 CH[3:0]
Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
0000: Channel pin = AIN0
0001: Channel pin = AIN1
0010: Channel pin = AIN2
0011: Channel pin = AIN3
0100: Channel pin = AIN4
0101: Channel pin = AIN5
0110: Channel pin = AIN6
0111: Channel pin = AIN7
1000: Channel pin = AIN8
1001: Channel pin = AIN9
1010: Channel pin = AIN10
1011: Channel pin = AIN11
1100: Channel pin = AIN12
1101: Channel pin = AIN13
1110: Channel pin = AIN14
1111: Channel pin = AIN15
Note: The number of channels is device dependent. Refer to the device pinout description.
ADCDRH
7 6 5 4 3
Table 113.
ADCDRH register description
Bit Name
7:0 D[9:2] MSB of Converted Analog Value
D[9:2]
RO
Function
2
Reset value: 0000 0000 (00h)
1 0
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ST72521xx-Auto 10-bit A/D converter (ADC)
ADCDRL
7 6 5
Reserved
-
4 3
Table 114.
ADCDRL register description
Bit Name
7:2 Reserved. Forced by hardware to 0.
1:0 D[1:0] LSB of Converted Analog Value
Function
2
Reset value: 0000 0000 (00h)
1 0
D[1:0]
RO
Table 115.
ADC register map and reset values
Address
(Hex.)
Register label
7 6 5
0070h
0071h
0072h
ADCCSR
Reset value
ADCDRH
Reset value
ADCDRL
Reset value
EOC
0
D9
0
0
SPEED
0
ADON
0
D8
0
D7
0
0 0
4
0
0
D6
0
3
CH3
0
D5
0
2
CH2
0
D4
0
0 0
1
CH1
0
D3
0
D1
0
0
CH0
0
D2
0
D0
0
Doc ID 17660 Rev 1 209/276
Instruction set ST72521xx-Auto
19.1 CPU addressing modes
The CPU features 17 different addressing modes which can be classified in seven main groups as listed in the following table:
Table 116.
Addressing modes
Group
Inherent
Immediate
Direct
Indexed
Indirect
Relative
Bit operation
NOP
LD A,#$55
LD A,$55
LD A,($55,X)
LD A,([$55],X)
JRNE loop
BSET byte,#5
Example
The CPU instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be divided in two submodes called long and short:
● Long addressing mode is more powerful because it can use the full 64 Kbyte address space; however, it uses more bytes and more CPU cycles.
● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP).
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 117.
CPU addressing mode overview
Mode Syntax Destination
Pointer address
(Hex.)
Inherent
Immediate
Short
Long
Direct
Direct
No Offset Direct
Short Direct
Long Direct
Short
Long
Short
Indirect
Indirect
Indexed
Indexed
Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w]
Indirect Indexed ld A,([$10],X)
00..FF
0000..FFFF
00..FF
00..1FE
0000..FFFF
00..FF
0000..FFFF
00..1FE
00..FF
00..FF
00..FF
Pointer size
(Hex.)
Length
(bytes) byte word byte
+ 0
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
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ST72521xx-Auto Instruction set
Table 117.
CPU addressing mode overview (continued)
Mode Syntax Destination
Pointer address
(Hex.)
Bit
Bit
Bit
Bit
Long
Relative
Relative
Indirect Indexed ld A,([$10.w],X) 0000..FFFF
Direct
Indirect jrne loop jrne [$10]
PC+/-127
PC+/-127
Direct
Indirect bset $10,#7 bset [$10],#7
00..FF
00..FF
Direct Relative btjt $10,#7,skip 00..FF
Indirect Relative btjt [$10],#7,skip 00..FF
00..FF
00..FF
00..FF
00..FF
Pointer size
(Hex.) word
Length
(bytes) byte byte byte
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
19.1.1 Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Table 118.
Inherent instructions
Instruction
NOP
TRAP
WFI
HALT
RET
IRET
SIM
RIM
SCF
RCF
RSP
LD
CLR
PUSH/POP
INC/DEC
TNZ
CPL, NEG
MUL
SLL, SRL, SRA, RLC, RRC
SWAP
Function
No operation
S/W Interrupt
Wait For Interrupt (Low Power Mode)
Halt Oscillator (Lowest Power Mode)
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
Reset Carry Flag
Reset Stack Pointer
Load
Clear
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Shift and Rotate Operations
Swap Nibbles
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Instruction set ST72521xx-Auto
19.1.2 Immediate
Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte contains the operand value.
Table 119.
Immediate instructions
Instruction
LD
CP
BCP
AND, OR, XOR
ADC, ADD, SUB, SBC
Load
Compare
Bit Compare
Logical Operations
Arithmetic Operations
Function
19.1.3 Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
19.1.4 Indexed (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.
The indexed addressing mode consists of three submodes:
Indexed (no offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed (short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
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The required data byte to do the operation is found by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
19.1.6 Indirect indexed (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
Table 120.
Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes
Type Instruction Function
LD
CP
AND, OR, XOR
Long and short instructions
ADC, ADD, SUB, SBC
BCP
Load
Compare
Logical operations
Arithmetic Additions/Subtractions operations
Bit Compare
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Instruction set ST72521xx-Auto
Table 120.
Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes (continued)
Type Instruction Function
Short instructions only
CLR
INC, DEC
TNZ
Clear
Increment/Decrement
Test Negative or Zero
CPL, NEG
BSET, BRES
1 or 2 Complement
Bit Operations
BTJT, BTJF Bit Test and Jump Operations
SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations
SWAP
CALL, JP
Swap Nibbles
Call or Jump subroutine
19.1.7 Relative (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Table 121.
Available relative direct/indirect instructions
Instruction
JRxx
CALLR
Conditional Jump
Call Relative
Function
The relative addressing mode consists of two submodes:
Relative (direct)
The offset is following the opcode.
Relative (indirect)
The offset is defined in memory, which address follows the opcode.
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The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table:
Table 122.
Instruction groups
Group
Load and Transfer
Stack operation
Increment/Decrement
Compare and Tests
LD CLR
PUSH POP RSP
INC DEC
CP TNZ BCP
Instructions
Doc ID 17660 Rev 1
ST72521xx-Auto Instruction set
Table 122.
Instruction groups (continued)
Group
Logical operations
Bit Operation
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
Unconditional Jump or Call
Conditional Branch
Interruption management
Condition Code Flag modification
Instructions
AND OR
BSET BRES
BTJT BTJF
ADC
SLL
JRA
JRxx
XOR CPL NEG
ADD SUB SBC MUL
SRL SRA RLC RRC SWAP SLA
JRT JRF JP CALL CALLR NOP RET
TRAP WFI HALT IRET
SIM RIM SCF RCF
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.
The whole instruction becomes:
PC - 2 End of previous instruction
PC - 1
PC
PC + 1
Prebyte
Opcode
Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92
PIY 91
Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
Replace an instruction using X indirect indexed addressing mode by a Y one.
Doc ID 17660 Rev 1 215/276
Instruction set
Table 123.
Instruction set overview
Mnemo Description Function/Example
ADC
ADD
AND
Add with Carry
Addition
Logical And
BCP Bit compare A, Memory
BRES Bit Reset
BSET Bit Set
BTJF Jump if bit is false (0)
BTJT Jump if bit is true (1)
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear
CP
CPL
DEC
Arithmetic Compare
One Complement
Decrement
HALT Halt
IRET Interrupt routine return
INC Increment
JP
JRA
JRT
JRF
JRIH
JRIL
Absolute Jump
Jump relative always
Jump relative
Never jump
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
JRH Jump if H = 1
JRNH Jump if H = 0
JRM Jump if I1:0 = 11
JRNM Jump if I1:0 <> 11
JRMI Jump if N = 1 (minus)
JRPL Jump if N = 0 (plus)
JREQ Jump if Z = 1 (equal)
JRNE Jump if Z = 0 (not equal)
JRC Jump if C = 1
JRNC Jump if C = 0
JRULT Jump if C = 1
JRUGE Jump if C = 0
A = A + M + C
A = A + M
A = A . M tst (A . M) bres Byte, #3 bset Byte, #3 M btjf Byte, #3, Jmp1 M
A
M btjt Byte, #3, Jmp1 M
A
A
A tst(Reg - M)
A = FFH-A dec Y
Pop CC, A, X, PC inc X jp [TBL.w] jrf *
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
H = 0 ?
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
C = 0 ?
Unsigned <
Jmp if unsigned >=
Dst reg, M reg reg, M reg, M reg, M
M
M
M
M
M
Src
ST72521xx-Auto
I1 H I0 N Z C
H
H
N Z
N Z
C
N Z C
N Z
0 1
N Z C
N Z 1
N Z
1 0
I1 H I0 N Z C
N Z
C
C
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ST72521xx-Auto Instruction set
Table 123.
Instruction set overview (continued)
Mnemo Description Function/Example
JRUGT Jump if (C + Z = 0)
JRULE Jump if (C + Z = 1)
LD Load
MUL
NEG
NOP
OR
Multiply
Negate (2's compl)
No Operation
OR operation
Unsigned >
Unsigned <= dst <= src
X,A = X * A neg $10
POP Pop from the Stack
A = A + M pop reg pop CC push Y
C = 0
RSP
SBC
SCF
SIM
SLA
SLL
PUSH Push onto the Stack
RCF Reset carry flag
RET Subroutine Return
RIM
RLC
RRC
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
Disable Interrupts
Shift left Arithmetic
Shift left Logic
SRL
SRA
SUB
Shift right Logic
Shift right Arithmetic
Subtraction
SWAP SWAP nibbles
TNZ Test for Neg & Zero
TRAP S/W trap
WFI
XOR
Wait for Interrupt
Exclusive OR A = A XOR M A
Dst reg, M M, reg
A, X, Y X, Y, A reg, M
A reg
CC
M
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0 reg, M reg, M
A
0 => A => C
A7 => A => C
A = A - M reg, M reg, M reg, M reg, M
A
A7-A4 <=> A3-A0 reg, M tnz lbl1
S/W interrupt
Src
M
M
M reg, CC
M
M
M
I1 H I0 N Z C
I1 H I0 N Z C
1
1
1
1
0
0
1
1
0
N Z
0
N Z C
N Z
N Z C
N Z C
N Z C
1
N Z C
N Z C
0 Z C
N Z C
N Z C
N Z
N Z
N Z
0
Doc ID 17660 Rev 1 217/276
Electrical characteristics ST72521xx-Auto
Unless otherwise specified, all voltages are referred to V
SS
.
20.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A selected temperature range).
= 25°C and T
A
= T
Amax
(given by the
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3
).
Unless otherwise specified, typical data is based on T
A are given only as design guidelines and are not tested.
= 25°C, V
DD
= 5V. The typical values
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
The loading conditions used for pin parameter measurement are shown in Figure 86 .
Figure 86.
Pin loading conditions
ST7 PIN
C
L
20.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in
.
Figure 87.
Pin input voltage
ST7 PIN
V
IN
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20.2 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 124.
Voltage characteristics
Symbol Ratings Maximum value Unit
V
DD
- V
SS
V
PP
- V
SS
V
ESD(HBM)
V
ESD(MM)
Supply voltage
Programming voltage
Input voltage on true open-drain pin
|V
V
IN
(1)
SSA
- V
SSx
|
Input voltage on any other pin
|
V
DDx
| and |
V
SSx
| Variations between different digital power pins
Variations between digital and analog ground pins
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
V
See
SS
V
SS
6.5
13
- 0.3 to 6.5
- 0.3 to V
DD
50
50
+ 0.3
V mV
1.
Directly connecting the RESET and I/O pins to V generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k
for RESET,
10k
DD
or V
SS could damage the device if an unintentional internal reset is
for I/Os). For the same reason, unused I/O pins must not be directly tied to V
DD
or V
SS
.
Doc ID 17660 Rev 1 219/276
Electrical characteristics ST72521xx-Auto
Table 125.
Current characteristics
Symbol
I
VDD
I
VSS
Ratings
Total current into V
DD
power lines (source)
(1)
Total current out of V
SS
ground lines (sink)
(1)
Output current sunk by any standard I/O and control pin
I
IO
(2)
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Maximum value Unit
150
25
50
- 25 mA
Injected current on V
PP
pin
Injected current on RESET pin
± 5
± 5 mA
I
INJ(PIN)
(3)(4)
Injected current on OSC1 and OSC2 pins ± 5
Injected current on PC6 pin (Flash devices only) + 5
I
INJ(PIN)
(3)
Injected current on any other pin
(5)(6)
Total injected current (sum of all I/O and control pins)
(5)
± 5
± 25
1.
All power (V
DD
) and ground (V
SS
) lines must always be connected to the external supply.
2.
Directly connecting the RESET and I/O pins to V
DD
or V
SS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k
for RESET, 10k
for I/Os). For the same reason, unused I/O pins must not be directly tied to V
DD
or V
SS
.
3.
I
INJ(PIN)
must never be exceeded. This is implicitly ensured if V cannot be respected, the injection current must be limited externally to the I
INJ(PIN) injection is induced by V
IN
> V
DD
IN
maximum is respected. If V
while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V
IN
IN
< V
SS
IN
maximum
value. A positive
. For true open-drain
maximum must always be respected.
4.
Negative injection may disturb the analog performance of the device. See Note 1
in Table 157: ADC accuracy on page 252
.
5.
When several inputs are submitted to a current injection, the maximum
I
INJ(PIN)
is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with
I
INJ(PIN)
maximum current injection on four I/O port pins of the device.
6.
True open-drain I/O port pins do not accept positive injection.
Table 126.
Thermal characteristics
Symbol Ratings
T
STG
T
J
Value Unit
Storage temperature range -65 to +150 °C
Maximum junction temperature (see
Section 21.1: Thermal characteristics on page 256 )
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20.3.1 General operating conditions
Table 127.
General operating conditions
Symbol Parameter f
CPU
V
DD
Internal clock frequency
Standard voltage range (except Flash
Write/Erase)
Operating voltage for Flash Write/Erase
Note:
Conditions Min
0
3.8
Max Unit
8 MHz
5.5
V
T
A
Ambient temperature range
V
PP
= 11.4 to 12.6V
4.5
A suffix version
B suffix version
C suffix version
-40
5.5
85
105
125
Some temperature ranges are only available with a specific package and memory size.
Refer to
Section 22: Device configuration and ordering information on page 257 .
°C
Figure 88.
f
CPU
max versus V
DD f
CPU
[MHz]
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
6
4
2
1
0
3.5
3.8
4.0
4.5
SUPPLY VOLTAGE [V]
5.5
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS
OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA)
Doc ID 17660 Rev 1 221/276
Electrical characteristics ST72521xx-Auto
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
.
Table 128.
Operating conditions with low voltage detector (LVD)
Symbol Parameter Conditions
V
V
IT+(LVD)
IT-(LVD)
Reset release threshold
(V
DD
rise)
Reset generation threshold
(V
DD
fall)
VD level = High in option byte
VD level = Med. in option byte
(2)
VD level = Low in option byte
(2)
VD level = High in option byte
VD level = Med. in option byte
(2)
VD level = Low in option byte
(2)
Min
4.0
(1)
3.55
(1)
2.95
(1)
3.8
3.35
(1)
2.8
(1)
Typ
4.2
3.75
3.15
4.0
3.55
3.0
Max
4.5
4.0
(1)
3.35
(1)
4.25
(1)
3.75
(1)
3.15
(1)
Unit
V
V hys(LVD)
LVD voltage threshold hysteresis t
Vt
POR g(VDD)
V
DD
rise time
(2)(3)
V
DD
glitches filtered (not detected) by LVD
(4)
V
IT+(LVD)
-V
IT-(LVD)
LVD enabled 6µs/V
200
100ms/V
40 mV
1.
Data based on characterization results, tested in production for ROM devices only
2.
Data based on characterization results, not tested in production
3.
When Vt
POR
V
IT+(LVD)
is faster than 100µs/V, the Reset signal is released after a delay of maximum 42µs after V
threshold.
DD
crosses the
4.
If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below
3.8V, device operation is not guaranteed.
ns
20.3.3 Auxiliary voltage detector (AVD) thresholds
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
.
Table 129.
Auxiliary voltage detector (AVD) thresholds
Symbol Parameter Conditions Min
V
V
IT+(AVD)
IT-(AVD)
1
0
0 AVDF flag toggle threshold
(V
DD rise)
1 AVDF flag toggle threshold
(V
DD
fall)
VD level = High in option byte 4.4
(1)
VD level = Med. in option byte 3.95
(1)
VD level = Low in option byte
VD level = High in option byte
3.4
(1)
4.2
(1)
VD level = Med. in option byte 3.75
(1)
VD level = Low in option byte 3.2
(1)
V hys(AVD)
V
IT-
AVD voltage threshold hysteresis V
IT+(AVD)
-V
IT-(AVD)
Voltage drop between AVD flag set and LVD reset activated
V
IT-(AVD)
-V
IT-(LVD)
1.
Data based on characterization results, tested in production for ROM devices only
Typ Max
4.6
4.15
4.9
(1)
4.4
(1)
3.6
3.8
(1)
4.4
4.65
(1)
4.0
3.4
4.2
(1)
3.6
(1)
200
Unit
V mV
450
222/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
20.3.4 External voltage detector (EVD) thresholds
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
.
Table 130.
External voltage detector (EVD) thresholds
Symbol Parameter
V
IT+(EVD)
V
IT-(EVD)
V hys(EVD)
1
0 AVDF flag toggle threshold (V
DD
0
1 AVDF flag toggle threshold (V
DD
EVD voltage threshold hysteresis rise
(1)
fall)
(1)
1.
Data based on characterization results, not tested in production
Conditions
V
IT+(EVD)
-V
IT-(EVD)
Min Typ Max Unit
1.15
1.26
1.35
1.1
1.2
1.3
200
V mV
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Electrical characteristics ST72521xx-Auto
20.4 Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode, for which the clock is stopped).
Table 131.
Current consumption
Symbol Parameter Conditions
Typ
Flash devices
Max
(1)
Typ
ROM devices
Max
(1)
Unit
I
DD
Supply current in
Run mode
(2)
Supply current in
Slow mode
(2)
Supply current in
Wait mode
(2)
Supply current in
Slow Wait mode
(2) f
OSC f
OSC f
OSC f
OSC
= 2MHz, f
CPU
= 4 MHz, f
CPU
= 1 MHz
= 2 MHz
= 8 MHz, f
CPU
= 16 MHz, f
CPU
= 4 MHz
= 8 MHz f
OSC f
OSC f
OSC f
OSC
= 2 MHz, f
CPU
= 62.5 kHz
= 4 MHz, f
CPU
= 8 MHz, f
CPU
= 16 MHz, f
CPU
= 125 kHz
= 250 kHz
= 500 kHz f
OSC f
OSC f
OSC f
OSC
= 2 MHz, f
CPU
= 4 MHz, f
CPU
= 8 MHz, f
CPU
= 16 MHz, f
CPU
= 1 MHz
= 2 MHz
= 4 MHz
= 8 MHz f
OSC f
OSC f
OSC f
OSC
= 2 MHz, f
CPU
= 4 MHz, f
CPU
= 62.5 kHz
= 125 kHz
= 8 MHz, f
CPU
= 16 MHz, f
CPU
= 250 kHz
= 500 kHz
-40°C < T
A
< +85°C
1.3
2.0
3.6
7.1
600
700
800
1100
1.0
1.5
2.5
4.5
580
650
770
1050
3.0
5.0
8.0
15.0
2700
3000
3600
4000
3.0
4.0
5.0
7.0
1200
1300
1800
2000
1.3
2.0
3.6
7.1
600
700
800
1100
1.0
1.5
2.5
4.5
70
100
200
350
2.0
3.0
5.0
10.0
1800
2100
2400
3000
1.3
2.0
3.3
6.0
200
300
600
1200 mA
µA mA
µA
I
DD
Supply current in
Halt mode
(3)
Supply current in
Active Halt mode
(4)
-40°C < T
A
< +125°C f
OSC f
OSC f
OSC f
OSC
= 2 MHz
= 4 MHz
= 8 MHz
= 16 MHz
<1
<1
80
160
325
650
10
50
No max. guaranteed
<1
<1
15
30
60
120
10
50
25
50
100
200
µA
µA
1.
Data based on characterization results, tested in production at V
DD
max. and f
CPU
max.
2.
Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is
50%.
- All I/O pins in input mode with a static value at V
DD
- All peripherals in reset state.
or V
SS
(no load)
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In Slow and Slow Wait mode, f
CPU
is based on f
OSC
divided by 32.
- To obtain the total current consumption of the device, add the clock source (
) and the peripheral power
).
3.
All I/O pins in push-pull 0 mode (when applicable) with a static value at V
DD characterization results, tested in production at V
DD
max. and f
CPU
max.
or VSS (no load), LVD disabled. Data based on
4.
Data based on characterization results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at V
DD
or V
SS
(no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total current consumption of the device, add the clock source consumption (
).
224/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
Power consumption vs f
CPU
: Flash devices
Figure 89.
Typical I
DD
in Run mode
7
6
5
4
9
8
3
2
1
0
8MHz
4MHz
2MHz
1MHz
3.2
3.6
4 4.4
Vdd (V)
4.8
5.2
5.5
Figure 90.
Typical I
DD
in Slow mode
1.20
1.00
0.80
0.60
0.40
0.20
0.00
500kHz
250kHz
125kHz
62.5kHz
3.2
3.6
4 4.4
Vdd (V)
4.8
5.2
5.5
Figure 91.
Typical I
DD
in Wait mode
6
5
4
3
2
1
0
8MHz
4MHz
2MHz
1MHz
3.2
3.6
4 4.4
Vdd (V)
4.8
5.2
5.5
Doc ID 17660 Rev 1 225/276
Electrical characteristics
Figure 92.
Typical I
DD
in Slow Wait mode
0.60
0.40
0.20
0.00
1.20
1.00
0.80
500kHz
250kHz
125kHz
62.5kHz
3.2
3.6
4 4.4
Vdd (V)
4.8
5.2
5.5
ST72521xx-Auto
20.4.2 Supply and clock managers
The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must be added (except for Halt mode).
Table 132.
Oscillators, PLL and LVD current consumption
Symbol Parameter Conditions Typ Max Unit
I
DD(RCINT)
Supply current of internal RC oscillator
I
DD(RES)
Supply current of resonator oscillator
(1)(2)
625
I
DD(PLL)
I
DD(LVD)
PLL supply current
LVD supply current
V
DD
= 5V
360
150 300
1.
Data based on characterization results done with the external components specified in Section 20.5.3
, not tested in production
2.
As the oscillator is based on a current source, the consumption does not depend on the voltage.
µA
226/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
Measured on LQFP64 generic board T
A
= 25°C, f
CPU
= 4 MHz.
Table 133.
On-chip peripherals current consumption
Symbol Parameter Conditions Typ Unit
I
I
I
DD(TIM)
I
DD(ART)
I
DD(SPI)
I
DD(SCI)
I
DD(I2C)
DD(ADC)
DD(CAN)
16-bit timer supply current
ART PWM supply current
SPI supply current
SCI supply current
I2C supply current
(3)
(4)
(5)
CAN supply current
(7)
(1)
(2)
ADC supply current when converting
(6)
V
V
V
DD
DD
DD
5.0V
5.0V
5.0V
V
DD
5.0V
V
DD
5.0V
V
DD
5.0V
50
75
400
175
400
400
µA
µA
µA
µA
µA
µA
1.
f
Data based on a differential I
DD
measurement between reset configuration (timer counter running at
CPU
/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.
2.
Data based on a differential I
DD
measurement between reset configuration (timer stopped) and timer counter enabled (only TCE bit set).
3.
Data based on a differential I
DD
measurement between reset configuration (SPI disabled) and a permanent
SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption.
4.
Data based on a differential I
SCI data transmit sequence.
DD
measurement between SCI low power state (SCID = 1) and a permanent
5.
Data based on a differential I
DD
measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100 kHz (data sent equal to 55h). This measurement includes the pad toggling consumption (27k ohm external pull-up on clock and data lines).
6.
Data based on a differential I conversions.
DD
measurement between reset configuration and continuous A/D
7.
Data based on a differential I
DD
measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.
Doc ID 17660 Rev 1 227/276
Electrical characteristics
20.5 Clock and timing characteristics
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
.
ST72521xx-Auto
Table 134.
General timings
Symbol Parameter Conditions Min Typ
(1)
Max Unit t c(INST)
Instruction cycle time f
CPU
= 8 MHz
2
250
3
375
12
1500 t
CPU ns t v(IT) t
Interrupt reaction time
(2) v(IT)
=
t c(INST)
+ 10 f
CPU
= 8 MHz
10
1.25
22
2.75
1.
Data based on typical application software.
2.
Time measured between interrupt event and interrupt vector fetch.
t needed to finish the current instruction execution.
c(INST)
is the number of t
CPU
cycles t
CPU
µs
228/276
Table 135.
External clock source
Symbol Parameter Conditions Min Typ Max Unit
V
OSC1H
V
OSC1L t w(OSC1H) t w(OSC1L) t r(OSC1) t f(OSC1)
I lkg
OSC1 input pin high level voltage
OSC1 input pin low level voltage
OSC1 high or low time
(1)
OSC1 rise or fall time
(1)
OSC1 input leakage current
V
SS
< V
IN
< V
DD
0.7xV
V
SS
5
DD
1.
Data based on design simulation and/or technology characteristics, not tested in production.
V
DD
0.3xV
DD
15
±1
Figure 93.
Typical application with an external clock source
V ns
µA
90%
V
OSC1H
10%
V
OSC1L t r(OSC1) t f(OSC1) t w(OSC1H) t w(OSC1L)
OSC2
EXTERNAL
CLOCK SOURCE
OSC1
Not connected internally f
OSC
I lkg
ST72XXX
Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
20.5.3 Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (such as frequency, package or accuracy).
Table 136.
Crystal and ceramic resonator oscillators
Symbol Parameter Conditions Min Typ Max Unit f
OSC
Oscillator frequency
(1)
MP: Medium power oscillator
MS: Medium speed oscillator
1
>2
>4
>8
20
-
2
4
8
16
MHz
40 k
R
C
C
F
L1
L2
Feedback resistor
(2)
Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R
S
)
(3)
R
R
R
R
S
S
S
S
= 200
= 200
= 200
= 100
-
LP oscillator
MP oscillator
MS oscillator
HS oscillator
22
22
18
15
-
-
56
46
33
33 pF i
2
OSC2 driving current V
DD
= 5V, V
IN
= V
SS
LP oscillator
MP oscillator
MS oscillator
HS oscillator
-
80
160
310
610
150
250
460
910
µA
1.
The oscillator selection can be optimized in terms of supply current using a high-quality resonator with small R
S
value. Refer to crystal/ceramic resonator manufacturer for more details.
2.
Data based on characterization results, not tested in production. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the microcontroller is used in tough humidity conditions.
3.
For C
L1
and C
L2 it is recommended to use high-quality ceramic capacitors in the 5pF to 25pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. C
L1
and C
L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1 included when sizing C capacitance).
L1
and C
L2
and C
L2
. PCB and MCU pin capacitance must be
(10pF can be used as a rough estimate of the combined pin and board
Figure 94.
Typical application with a crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS i
2 f
OSC
C
L1 OSC1
RESONATOR R
F
C
L2
OSC2
ST72XXX
Doc ID 17660 Rev 1 229/276
Electrical characteristics ST72521xx-Auto
Table 137.
OSCRANGE selection for typical resonators
Typical ceramic resonators
(1)
Supplier f
OSC
(MHz)
Reference
Recommended OSCRANGE option bit configuration
2 CSTCC2M00G56A-R0 MP mode
(2)
Murata
4
8
16
CSTCR4M00G55B-R0
CSTCE8M00G55A-R0
CSTCE16M0G53A-R0
MS mode
HS mode
1.
Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com.
2.
LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small
(> 0.8V).
Note:
Table 138.
RC oscillator characteristics
Symbol Parameter f
OSC(RCINT)
Internal RC oscillator frequency
)
Conditions
T
A
= 25°C, V
DD
= 5V
Min Typ Max Unit
2 3.5
5.6
MHz
Figure 95.
Typical f
OSC(RCINT)
versus T
A
4
3.8
3.6
3.4
3.2
3
-45 0 25
T
A
(°C)
Vdd = 5V
Vdd = 5.5V
70 130
To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between V
DD
and V
SS
230/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
Table 139.
PLL characteristics
Symbol Parameter Conditions Min Typ Max Unit f
OSC
PLL input frequency range 2 4 MHz
f
CPU
/f
CPU
Instantaneous PLL jitter
(1)
ROM device, f
OSC
= 4 MHz
Flash device, f
OSC
= 4 MHz
Flash device, f
OSC
= 2 MHz
0.7
2
1.0
2.5
2.5
4.0
%
1.
Data based on characterization results
The user must take the PLL jitter into account in the application (for example, in serial communication or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several CPU cycles. Therefore, the longer the period of the application signal, the less it is impacted by the PLL jitter.
shows the PLL jitter integrated on application signals in the range 125 kHz to
4 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
Figure 96.
Integrated PLL jitter versus signal frequency
(1)
+/-Jitter (%)
1.2
1
0.8
0.6
0.4
0.2
0
FLASH typ
ROM max
ROM typ
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency
1.
Measurement conditions: f
CPU
= 8 MHz
Doc ID 17660 Rev 1 231/276
Electrical characteristics ST72521xx-Auto
20.6.1 RAM and hardware registers
Table 140.
RAM supply voltage
Symbol Parameter Conditions Min Typ Max Unit
V
RM
Data retention mode
(1)
Halt mode (or RESET) 1.6
1.
Minimum V
DD
supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in hardware registers (only in Halt mode). Not tested in production.
V
Table 141.
Dual voltage HDFlash memory
Symbol Parameter Conditions Min
(1)
Typ Max
(1)
Unit f
CPU
V
PP
Operating frequency
Programming voltage
Supply current
(3)
(2)
Read mode
Write / Erase mode
4.5V < V
DD
< 5.5V
Run mode (f
CPU
= 4 MHz)
Write / Erase
0
1
11.4
0
8
8
12.6
3
MHz
V mA
I
DD
Power down mode / HALT 1 10
µA
I
PP
V
PP
current
(3)
Read (V
PP
= 12V)
Write / Erase
200
30 mA t
VPP
Internal V
PP
stabilization time
10 µs t
RET
N
RW
T
PROG
T
ERASE
Data retention
Write erase cycles
Programming or erasing temperature range
T
T
A
A
= 55°C
= 85°C
20
100
-40 25 85 years cycles
1.
Data based on characterization results, not tested in production
2.
V
PP
must be applied only during the programming or erasing operation and not permanently for reliability reasons.
3.
Data based on simulation results, not tested in production
°C
Warning: Do not connect 12V to V
PP
before V
DD
is powered on, as this may damage the device.
232/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
20.7 EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
20.7.1 Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
● ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
● FTB : A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100pF capacitor until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results given in
below are based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
●
●
●
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Doc ID 17660 Rev 1 233/276
Electrical characteristics ST72521xx-Auto
.
Table 142.
EMS test results
Symbol Parameter Conditions
V
FESD
V
FFTB
Flash device:
V
DD
5V, T
A
+25°C, f
OSC conforms to IEC 1000-4-2
8 MHz,
Voltage limits to be applied on any I/O pin to induce a functional disturbance
ROM device:
V
DD
5V, T
A
+25°C, f
OSC conforms to IEC 1000-4-2
8 MHz,
Fast transient voltage burst limits to be applied through 100pF on V
DD
and V
DD pins to induce a functional disturbance
Flash device:
V
DD
5V, T
A
+25°C, f
OSC conforms to IEC 1000-4-4
8 MHz,
Level/Class
4B
3B
3B
20.7.2 EMI (electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 143.
EMI emissions
Symbol Parameter
Conditions
V
DD
5V, T
A
+25°C, conforming to SAE J 1752/3
Monitored frequency band
Max vs [f
OSC
/f
CPU
]
(1)
8/4 MHz 16/8 MHz
Unit
S
EMI
Peak level LQFP64 14 x 14 package
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
15
20
0
2.5
15
27
5
3.0
dBµV
-
1.
Data based on characterization results, not tested in production.
234/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
20.7.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note AN1181.
Table 144.
ESD absolute maximum ratings
Symbol Ratings Conditions
V
V
ESD(HBM)
ESD(MM)
Electrostatic discharge voltage
(Human Body Model)
Electrostatic discharge voltage
(Machine Model)
T
A
= +25°C conforming to AEC-Q100-002
T
A
= +25°C conforming to AEC-Q100-003
1.
Data based on characterization results, not tested in production.
Class Max. value
(1)
Unit
H1C
M2
2000
200
Static latch-up (LU)
●
●
Two complementary static tests are required on six parts to assess the latch-up performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
V
Table 145.
Electrical sensitivities
Symbol Parameter
LU Static latch-up class
Conditions
T
T
A
A
T
A
+25°C
+85°C
+125°C conforming to JESD 78
Class
A
Doc ID 17660 Rev 1 235/276
Electrical characteristics
20.8 I/O port pin characteristics
ST72521xx-Auto
Subject to general operating conditions for V
DD,
f
OSC
, and T
A
unless otherwise specified.
Table 146.
I/O port pin general characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
V
IH
V hys
V
IL
V
IH
V hys
Input low level voltage
Input low level voltage
(1)
Input high level voltage
Input high level voltage
(1)
Schmitt trigger voltage hysteresis
(1)
(1)
Schmitt trigger voltage hysteresis
(2)
(2)
CMOS ports
TTL ports
0.7xV
2
DD
0.7
1
0.3xV
0.8
DD
V
V
Injected current on PC6 pin (Flash devices only)
0 +4
I
INJ(PIN)
(3)
Injected current on an I/O pin V
DD
= 5V ±4 mA
I
INJ(PIN)
(3)
Total injected current (sum of all I/O and control pins)
±25
I lkg
I
S
R
PU
C
IO
Input leakage current
Static current consumption
Weak pull-up equivalent resistor
(6)
V
V
SS
IN
< V
IN
= V
SS
< V
DD
Floating input mode
V
DD
(4)(5)
= 5V 50
400
120
±1
250
µA k
t f(IO)out t r(IO)out t w(IT)in
I/O pin capacitance
Output high to low level fall time
(1)
Output low to high level rise time
(1)
External interrupt pulse time
(7)
C
L
= 50pF
Between 10% and 90%
5
25
25 pF ns
1 t
CPU
1.
Data based on characterization results, not tested in production.
2.
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3.
When the current limitation is not possible, the V
IN
maximum must be respected, otherwise refer to I
INJ(PIN) positive injection is induced by V
IN
> V
DD
while a negative injection is induced by V
IN
for more details.
< V
SS
specification. A
. Refer to
4.
Static peak current value taken at a fixed V
IN in production. This value depends on V
DD
value, based on design simulation and technology characteristics, not tested and temperature values.
5.
The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current consumption may result. This can be avoided by keeping the input voltage of this pin close to V
DD
or V
SS
.
6.
The R
PU
pull-up equivalent resistor is based on a resistive transistor (corresponding I
PU current characteristics described in
7.
To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
236/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 97.
Unused I/O pins configured as input
V
DD
10k
10k
ST7XXX
UNUSED I/O PORT
UNUSED I/O PORT
ST7XXX
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
Electrical characteristics
Figure 98.
Typical I
PU
vs V
DD
with V
IN
= V
SS
90
80
70
60
50
40
30
20
10
0
2 2.5
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
3 3.5
4
Vdd(V)
4.5
5 5.5
6
20.8.2 Output driving current
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Table 147.
Output driving current
Symbol Parameter Conditions Min Max Unit
Output low level voltage for a standard I/O pin when 8 pins are sunk at same time
(see
I
IO
= +5mA
I
IO
= +2mA
1.2
0.5
V
V
OL
(1)
OH
(2)
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time
(see
and
)
Output high level voltage for an I/O pin when 4 pins are sourced at same time
(see
and
)
V
DD
= 5V
I
I
IO
= +20mA,
T
A
T
A
< 85°C
> 85°C
I
IO
= +8mA
I
IO
= -5mA,
T
A
T
A
IO
< 85°C
> 85°C
= -2mA
V
DD
V
DD
- 1.4
- 1.6
V
DD
- 0.7
1.3
1.5
0.6
1.
The I
IO
current sunk must always respect the absolute maximum rating specified in ports and control pins) must not exceed I
VSS
.
IO
(I/O
2.
The I
IO
current sourced must always respect the absolute maximum rating specified in Section 20.2.2
IO
(I/O ports and control pins) must not exceed I
VDD
. True open-drain I/O pins do not have V
OH
.
V
Doc ID 17660 Rev 1 237/276
Electrical characteristics ST72521xx-Auto
Figure 99.
Typical V
OL
at V
DD
= 5V (standard) Figure 100. Typical V
OL
at V
DD
= 5V (high-sink)
1.4
1
0.9
1.2
0.8
1
0.8
0.6
0.4
0.2
Ta=140°C "
Ta=95°C
Ta=25°C
Ta=-45°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ta= 140 °C
Ta= 95 °C
Ta= 25 °C
Ta= -45°C
0
0 0.005
Iio(A)
0.01
0.015
0 0.01
Iio(A)
0.02
0.03
Figure 101. Typical V
OH
at V
DD
= 5V
5.5
5
4.5
4
3.5
3
2.5
2
V dd= 5V 1 40°C m in
V dd= 5v 95°C m in
V dd= 5v 25°C m in
V dd= 5v -4 5°C m in
-0.01
-0.008 -0.006 -0.004 -0.002
Iio (A)
0
238/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 102. Typical V
OL
versus V
DD
(standard)
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
2 2.5
3 3.5
4
Vdd(V)
4.5
Ta= -4 5°C
Ta= 25°C
Ta= 95°C
Ta= 140°C
5 5.5
6
Electrical characteristics
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
2 2.5
3 3.5
4
Vdd(V)
4.5
Ta=-4 5°C
Ta=2 5°C
Ta=9 5°C
Ta=1 40°C
5 5.5
6
Figure 103. Typical V
OL
versus V
DD
(high-sink)
0 .6
0 .5
0 .4
0 .3
0 .2
0 .1
0
2
Ta= 14 0°C
Ta=9 5°C
Ta=2 5°C
Ta=-45 °C
2.5
3 3.5
4
Vdd (V )
4.5
5 5.5
6
0 .8
0 .6
0 .4
0 .2
0
2
1 .6
1 .4
1 .2
1
2.5
3
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
3.5
4
V dd(V )
4.5
5 5.5
6
Figure 104. Typical V
DD
- V
OH
versus V
DD
5.5
5
4.5
4
3.5
3
2.5
2
2 2.5
3 3.5
4
Vdd(V)
4.5
Ta= -45°C
Ta= 25°C
Ta= 95°C
Ta= 140°C
5 5.5
6
6
5
4
3
Ta= -45°C
Ta= 25°C
Ta= 95°C
Ta= 140°C
2
1
0
2 2.5
3 3.5
4
Vdd(V)
4.5
5 5.5
6
Doc ID 17660 Rev 1 239/276
Electrical characteristics
20.9 Control pin characteristics
ST72521xx-Auto
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Table 148.
Asynchronous RESET pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage
(1)
0.16xV
D
D
V
IH
Input high level voltage
(1)
0.85xV
D
D V
V hys
Schmitt trigger voltage hysteresis
(2)
Output low level voltage
(3)
2.5
t
V
OL
I
R
IO
ON w(RSTL)out
Input current on RESET pin
Weak pull-up equivalent resistor
Generated reset pulse duration
V
DD
= 5V, I
IO
= +2mA
Stretch applied on external pulse
Internal reset sources
20
0
20
0.2
2
30
30
0.5
120
42
(4)
42
(4) mA k
µs t h(RSTL)in t g(RSTL)in
External reset pulse hold time
Filtered glitch duration
(6)
(5)
2.5
200
1.
Data based on characterization results, not tested in production.
2.
Hysteresis voltage between Schmitt trigger switching levels.
3.
The I
IO
current sunk must always respect the absolute maximum rating specified in ports and control pins) must not exceed I
VSS
.
IO
(I/O
4.
Data guaranteed by design, not tested in production.
5.
To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below t h(RSTL)in
can be ignored.
6.
The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments.
ns
240/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 105. RESET pin protection when LVD is enabled
V
DD
EXTERNAL
RESET
Required Optional
(note 3)
0.01µF
1M
R
ON
Filter
PULSE
GENERATOR
Electrical characteristics
ST72XXX
INTERNAL
RESET
WATCHDOG
LVD RESET
Note: 1 The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the V
IL
maximum level specified in Section 20.9.1 on page 240
.
Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
INJ(RESET)
in Section 20.2.2 on page 220 .
2 When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise on the reset line.
3 In case a capacitive power supply is used, it is recommended to connect a 1M
pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power consumption of the MCU).
4 Tips when using the LVD:
A. Check that all recommendations related to reset circuit have been applied (see notes above).
B. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF +
1M
pull-down on the RESET pin.
C. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps A and B above are sufficient for a robust solution. Otherwise, replace 10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.
Doc ID 17660 Rev 1 241/276
Electrical characteristics
Figure 106. RESET pin protection when LVD is disabled
V
DD
USER
EXTERNAL
RESET
CIRCUIT
R
ON
Filter
0.01µF
Required
PULSE
GENERATOR
ST72521xx-Auto
ST72XXX
INTERNAL
RESET
WATCHDOG
Note: The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the V
IL
maximum level specified in Section 20.9.1 on page 240
.
Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
INJ(RESET)
in Section 20.2.2 on page 220 .
20.9.2 ICCSEL/V
PP
pin
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Table 149.
ICCSEL/V
PP
pin characteristics
Symbol Parameter Conditions Min Max
V
IL
V
IH
Input low level voltage
(1)
Input high level voltage
(1)
Flash versions
ROM versions
Flash versions
V
SS
V
SS
V
DD
-0.1
0.7xV
DD
0.2
0.3xV
12.6
ROM versions
I lkg
Input leakage current V
IN
= V
SS
1.
Data based on design simulation and/or technology characteristics, not tested in production.
V
DD
±1
DD
Unit
V
µA
242/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 107. Two typical applications with ICCSEL/V
PP
pin
(1)
Electrical characteristics
ICCSEL/V
PP
ST72XXX
PROGRAMMING
TOOL
10k
V
PP
ST72XXX
1.
When ICC mode is not required by the application, the ICCSEL/V
PP
pin must be tied to V
SS
.
20.10 Timer peripheral characteristics
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Refer to
Section 20.8: I/O port pin characteristics
for more details on the input/output alternate function characteristics (such as output compare, input capture, external clock, or
PWM output).
Table 150.
8-bit PWM-ART auto-reload timer characteristics
Symbol Parameter Conditions Min
1
125 t res(PWM)
PWM resolution time f
CPU
= 8 MHz f
EXT f
PWM
ART external clock frequency
PWM repetition rate
Res
PWM
PWM resolution
V
OS
PWM/DAC output step voltage
V
DD
= 5V,
Resolution = 8 bits
0
Table 151.
16-bit timer characteristics
Symbol Parameter t w(ICAP)in
Input capture pulse time
Conditions t res(PWM)
PWM resolution time f
CPU
= 8 MHz
Min
1
2
250 f
EXT f
PWM
Timer external clock frequency
PWM repetition rate
Res
PWM
PWM resolution
0
Typ
20
Typ
Max Unit t
CPU ns f
CPU
/2 MHz
8
Max Unit t
CPU t
CPU ns f
CPU
/4 MHz
16 bit mV bit
Doc ID 17660 Rev 1 243/276
Electrical characteristics
20.11 Communication interface characteristics
ST72521xx-Auto
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Refer to
Section 20.8: I/O port pin characteristics
for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Table 152.
SPI characteristics
Symbol Parameter Conditions Min Max
1/t f
SCK c(SCK)
SPI clock frequency
Master, f
CPU
= 8 MHz
Slave, f
CPU
= 8 MHz f
CPU
/128 = 0.0625
0 f
CPU
/4 = 2 f
CPU
/2 = 4 t r(SCK) t f(SCK) t su(SS)
(1) t h(SS)
(1) t t w(SCKH)
(1) w(SCKL)
(1) t t su(MI)
(1) su(SI)
(1) t t h(MI)
(1)
(1) h(SI) t a(SO)
(1) t dis(SO)
(1) t v(SO)
(1) t h(SO)
(1) t v(MO)
(1) t h(MO)
(1)
SPI clock rise and fall time
SS setup time
SS hold time
(2)
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge) t
CPU see I/O port pin description
+ 50
120
100
90
100
100
100
100
0
0
0
1.
Data based on design simulation and/or characterization results, not tested in production.
2.
Depends on f
CPU
. For example, if f
CPU
= 8 MHz, then t
CPU
= 1 / f
CPU
= 125 ns and t su(SS)
= 175 ns.
120
240
120
120
Unit
MHz ns t
CPU
244/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Figure 108. SPI slave timing diagram with CPHA = 0
(1)
SS
INPUT t su(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1 t a(SO)
MISO
OUTPUT See note 2 t su(SI) t c(SCK) t t w(SCKH) w(SCKL)
MSB OUT t h(SI) t v(SO)
BIT6 OUT
MOSI
INPUT
MSB IN BIT1 IN t h(SO) t r(SCK) t f(SCK)
Electrical characteristics
LSB IN t h(SS)
LSB OUT t dis(SO)
See note 2
1.
Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
Figure 109. SPI slave timing diagram with CPHA = 1
(1)
SS
INPUT t su(SS) t c(SCK) t h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO) t h(SO) t dis(SO)
MISO
OUTPUT
See note 2
HZ t su(SI)
MSB OUT t h(SI)
BIT6 OUT t r(SCK) t f(SCK)
LSB OUT
See note 2
MOSI
INPUT
MSB IN BIT1 IN LSB IN
1.
Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
Doc ID 17660 Rev 1 245/276
Electrical characteristics
Figure 110. SPI master timing diagram
(1)
SS
INPUT t c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1 t w(SCKH) t w(SCKL) t su(MI) t h(MI)
MISO
INPUT MSB IN BIT6 IN t v(MO) t r(SCK) t f(SCK)
LSB IN
ST72521xx-Auto t h(MO)
MOSI
OUTPUT
See note 2 MSB OUT BIT6 OUT LSB OUT See note 2
1.
Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
246/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
20.11.2 I
2
C - inter IC control interface
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Refer to
Section 20.8: I/O port pin characteristics
for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the requirements of the standard I2C communication protocol described in the following table.
Table 153.
I
2
C control interface characteristics
Symbol Parameter
Standard mode I
Min
(2)
Max
2
C
(2)
Fast mode I
2
C
(1)
Min
(2)
Max
(2)
Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
4.7
4.0
250
0
(3)
1000
300
1.3
0.6
100
0
(4)
20+0.1C
b
900
(3)
300
µs ns t h(STA) t su(STA) t su(STO) t w(STO:STA)
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
4.0
4.7
4.0
4.7
0.6
1.3
µs
C b
Capacitive load for each bus line 400 400 pF
1.
At 4 MHz f
CPU
260 kHz.
, maximum I
2
C speed (400 kHz) is not achievable. In this case, maximum I
2
C speed will be approximately
2.
Data based on standard I
2
C protocol requirement, not tested in production.
3.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal.
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
Doc ID 17660 Rev 1 247/276
Electrical characteristics ST72521xx-Auto
Figure 111. Typical application with I
2
C BUS and timing diagram
(1)
4.7k
V
DD
4.7k
V
DD
I
2
C BUS
100
100
SDAI
SCLI
ST72XXX
START t su(STA)
REPEATED START t w(STO:STA)
START
SDA t f(SDA) t r(SDA) t su(SDA) t h(SDA)
STOP
SCK t h(STA) t w(SCKH) t w(SCKL) t r(SCK) t f(SCK) t su(STO)
1.
Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
The following table provides the values to be written in the I2CCCR register to obtain the required I
2
C SCL line frequency.
Table 154.
SCL frequency table f
SCL
(kHz)
400
300
200
100
50
20
I2CCCR value f
CPU
= 4 MHz f
CPU
= 8 MHz
V
DD
= 4.1V
V
DD
= 5V V
DD
= 4.1V
V
DD
= 5V
R
P
= 3.3k
R
P
= 4.7k
R
P
= 3.3k
R
P
= 4.7k
R
P
= 3.3k
R
P
= 4.7k
R
P
= 3.3k
R
P
= 4.7k
Not achievable 83h
85h Not achievable
83h
10h
24h
5Fh
8Ah
24h
89h
23h
4Ch
FFh
24h
8Ah
23h
Note:
Legend:
R
P
= External pull-up resistance f
SCL
= I
2
C speed
- For speeds around 200 kHz, the achieved speed can have a
±
5% tolerance.
- For other speed ranges, the achieved speed can have a
±
2% tolerance.
The above variations depend on the accuracy of the external components used.
248/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
20.11.3 CAN - Controller area network interface
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Refer to
for more details on the input/output alternate function characteristics (CANTX and CANRX).
Table 155.
CAN characteristics
Symbol Parameter Conditions t p(RX:TX)
CAN controller propagation time
(1)
1.
Data based on simulation results, not tested in production
Min Typ Max Unit
60 ns
20.12 10-bit ADC characteristics
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Table 156.
10-bit ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
V f t t
ADC
AREF
V
R
C f
C
I
AIN lkg
AIN
AIN
AIN
ADC
ADC
ADC
ADC clock frequency
Analog reference voltage
Conversion voltage range
0.7*V
DD
< V
AREF
< V
DD
Positive input leakage current for analog input
(1)
External input impedance
(2)
External capacitor on analog input
Variation frequency of analog input signal
Internal sample and hold capacitor
Conversion time (Sample + Hold) f
CPU f
ADC
= 8 MHz, speed = 0,
= 2 MHz
No. of sample capacitor loading cycles
No. of hold conversion cycles
-40°C < T
A
< 85°C range
Other T
A ranges
V
0.4
3.8
SSA
12
7.5
4
2
V
DD
V
AREF
±250
±1
See
and
11
1.
Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted analog value is recommended.
2.
Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k
). Data based on characterization results, not tested in production.
MHz
1/f
V nA
µA k
pF
Hz pF
µs
ADC
Doc ID 17660 Rev 1 249/276
Electrical characteristics ST72521xx-Auto
Figure 112. R
AIN
C
AIN
maximum versus f
= 0pF
(1)
ADC
with Figure 113. Recommended C values
(1)
AIN and R
AIN
45
40
35
30
25
20
15
10
5
0
2 MHz
1 MHz
1000
100
10
1
Cain 10 nF
Cain 22 nF
Cain 47 nF
0.1
0 10 30
C
PARASITIC
(pF)
70 0.01
0.1
f
AIN
(KHz)
1 10
1.
C
PARASITIC
represents the capacitance of the PCB
(dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high C
PARASITIC
value will downgrade conversion accuracy. To remedy this, f
ADC should be reduced.
1.
This graph shows that, depending on the input signal variation (f
AIN
), C
AIN
can be increased for stabilization time and decreased to allow the use of a larger serial resistor (R
AIN)
.
Figure 114. Typical A/D converter application
R
AIN AINx
V
DD
V
T
0.6V
ST72XXX
V
AIN
C
AIN
V
T
0.6V
2k
max
10-bit A/D conversion
I lkg
C
ADC
12pF
20.12.1 Analog power supply and reference pins
Depending on the MCU pin count, the package may feature separate V
AREF
and V
SSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion.
Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see
Section 20.12.2: General PCB design guidelines ).
250/276 Doc ID 17660 Rev 1
ST72521xx-Auto Electrical characteristics
To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals.
●
●
Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB.
Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing
0.1µF and optionally, if needed 10pF capacitors as close as possible to the ST7 power
supply pins and a 1 to 10µF capacitor close to the power source (see Figure 115 ).
●
●
The analog and digital power supplies should be connected in a star network. Do not use a resistor, as V
AREF is used as a reference voltage by the A/D converter and resistance would cause a voltage drop and a loss of accuracy.
any
Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted.
Figure 115. Power supply filtering
V
DD
POWER
SUPPLY
SOURCE
1 to 10µF
+
ST7
DIGITAL NOISE
FILTERING
EXTERNAL
NOISE
FILTERING
0.1µF V
V
SS
0.1µF V
AREF
V
DD
SSA
ST72XXX
Doc ID 17660 Rev 1 251/276
Electrical characteristics ST72521xx-Auto
Conditions: V
DD
= 5V
(1)
Table 157.
ADC accuracy
Symbol Parameter
(1)
Conditions Typ Max
(2)
Unit
|E
T
| Total unadjusted error
|E
O
| Offset error
|E
G
| Gain error
|E
D
| Differential linearity error
|E
L
| Integral linearity error
CPU in run mode @ f
ADC
2 MHz
3
2
0.5
1
4
3
3
2
LSB
1.
ADC Accuracy versus Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input. The effect of negative injection current on robust pins is specified in
.
Any positive injection current within the limits specified for I
INJ(PIN) affect the ADC accuracy.
and
I
INJ(PIN)
in
does not
2.
Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C to 125°C (± 3
distribution limits).
Figure 116. ADC error classification
Digital Result ADCDR
1023
1022
1021
1LSB
IDEAL
=
V
AREF
–
1024
V
E
T
7
6
5
4
3
2
1
E
O
0
V
SSA
1 2
1 LSB
E
IDEAL
L
3 4 5 6 7
(2)
E
D
(3)
(1)
E
G
1021 1022 1023 1024
V
AREF
Legend:
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
E
O
= Offset Error: deviation between the first actual transition and the first ideal one.
E
G
= Gain Error: deviation between the last ideal transition and the last actual one.
E
D
= Differential Linearity Error: maximum deviation between actual steps and the ideal one.
E
L
= Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
V in
(LSB
IDEAL
)
252/276 Doc ID 17660 Rev 1
ST72521xx-Auto Package characteristics
Figure 117. 80-pin low profile quad flat package outline
D
D1
E1 E
A1 b
A
A2 e
L1
L
Table 158.
80-pin low profile quad flat package mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ
C
D
D1
E
A
A1
A2 b
E1 e
L
L1
0.050
1.350
0.220
1.400
0.320
0.090
0.200
16.000
14.000
16.000
14.000
0°
0.450
0.650
3.5°
0.600
1.000
1.600
0.150
1.450
0.380
7°
0.750
0.0020
0.0531
0.0087
0.0035
0°
0.0177
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
0.0551
0.0126
0.6299
0.5512
0.6299
0.5512
0.0256
3.5°
0.0236
0.0394
c
Max
0.0630
0.0059
0.0571
0.0150
0.0079
7°
0.0295
Doc ID 17660 Rev 1 253/276
Package characteristics ST72521xx-Auto
Figure 118. 64-pin (14x14) low profile quad flat package outline
D
D1
A1
A
A2 b e
E1 E
L1
L
c
Table 159.
64-pin (14x14) low profile quad flat package mechanical data mm inches
(1)
Dimension
Min Typ Max Min Typ b c
D
D1
A
A1
A2
E
E1 e
L
L1
0.050
1.350
0.300
0.090
1.600
0.150
1.450
1.400
0.370
0.450
0.200
16.000
14.000
16.000
14.000
0°
0.800
3.5°
0.450
0.600
1.000
7°
0.750
0.0020
0.0531
0.0118
0.0035
0°
0.0177
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
0.0551
0.0146
0.6299
0.5512
0.6299
0.5512
0.0315
3.5°
0.0236
0.0394
Max
0.0630
0.0059
0.0571
0.0177
0.0079
7°
0.0295
254/276 Doc ID 17660 Rev 1
ST72521xx-Auto Package characteristics
Figure 119. 64-pin (10x10) low profile quad flat package outline
D
D1
E1 E b
A1
A
A2 e
L1
L
c
Table 160.
64-pin (10x10) low profile quad flat package mechanical data mm inches
(1)
Dimension
Min Typ Max Min Typ
A
A1
A2 b c
D
D1
E
E1 e
L
L1
0.050
1.350
0.170
1.400
0.220
1.600
0.150
1.450
0.270
0.0020
0.0531
0.0067
0.090
0.200
12.000
10.000
0.0035
12.000
10.000
0.500
0°
0.450
3.5°
0.600
1.000
7°
0.750
0°
0.0177
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
0.0551
0.0087
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
0.0236
0.0394
Max
0.0630
0.0059
0.0571
0.0106
0.0079
7°
0.0295
Doc ID 17660 Rev 1 255/276
Package characteristics ST72521xx-Auto
Table 161.
Thermal characteristics
Symbol Ratings Value Unit
R thJA
P
D
T
Jmax
Package thermal resistance (junction to ambient)
LQFP80 14x14
LQFP64 14x14
LQFP64 10x10
Power dissipation
(1)
Maximum junction temperature
(2)
55
47
50
500
150
°C/W mW
°C
1.
The maximum power dissipation is obtained from the formula P of an application can be defined by the user with the formula: P internal power (I application.
DD x V
DD
) and P
PORT
D
= (T
D
= P
J
-T
INT
A
) / R
+ P thJA
PORT
. The power dissipation
where P
INT
is the chip
is the port power dissipation depending on the ports used in the
2.
The maximum chip-junction temperature is based on technology characteristics.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
21.3 Packaging for automatic handling
The devices can be supplied in trays or with tape and reel conditioning.
Tape and reel conditioning can be ordered with pin 1 left-oriented or right-oriented when
facing the tape sprocket holes as shown in Figure 120 .
Figure 120. Pin 1 orientation in tape and reel conditioning
Left orientation Right orientation (EIA 481-C compliant)
Pin 1 Pin 1
See also Section Figure 121.: ST72F521xxx-Auto Flash commercial product structure on page 260
and
Figure 122: ST72P521xxx-Auto FastROM commercial product structure on page 262
.
256/276 Doc ID 17660 Rev 1
ST72521xx-Auto
22
Device configuration and ordering information
Device configuration and ordering information
Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM).
ST72521B-Auto devices are ROM versions. ST72P521-Auto devices are Factory Advanced
Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash devices. Flash devices are shipped to customers with a default content, whereas
ROM/FASTROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the option bytes while the ROM/FASTROM devices are factory-configured.
Detailed device configuration and ordering information is presented in the following
and Section 22.2: ROM device ordering information and transfer of customer code
.
Table 162.
Flash option bytes
Static option byte 0 Static option byte 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
WDG VD OSCTYPE
Res Res
HALT SW 1 0 1
Default value:
1 1 1 0 0 1 1 1
(1)
1 1
1.
Depends on device type as defined in Table 165: Package selection (OPT7) on page 259
0
0
2
1
OSCRANGE
1
1
0
1 1
The option bytes allow the hardware configuration of the microcontroller to be selected.
They have no address in the memory map and can be accessed only in programming mode
(for example, using a standard ST7 programming tool). The default content of the Flash is fixed to FFh. To program the Flash devices directly using ICP, Flash devices are shipped to customers with the internal RC clock source enabled. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list).
Table 163.
Option byte 0 bit description
Bit Name
OPT7 WDG HALT
Function
Watchdog and Halt mode
This option bit determines if a RESET is generated when entering
Halt mode while the Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Doc ID 17660 Rev 1 257/276
Device configuration and ordering information ST72521xx-Auto
Table 163.
Option byte 0 bit description (continued)
Bit Name Function
OPT6
OPT5
OPT4:3
OPT2
OPT1
OPT0
WDG SW
-
VD[1:0]
-
PKG0
FMP_R
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Reserved, must be kept at default value.
Voltage detection
These option bits enable the voltage detection block (LVD and AVD) with a selected threshold for the LVD and AVD (EVD + AVD).
00: Selected LVD = Highest threshold (V
DD
~4V)
01: Selected LVD = Medium threshold (V
DD
~3.5V)
10: Selected LVD = Lowest threshold (V
DD
~3V)
11: LVD and AVD off
Caution : If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed. For details on the AVD and LVD threshold levels refer to
Section 20.3.2: Operating conditions with low voltage detector (LVD)
.
Reserved, must be kept at default value.
Package selection bit 0
This option bit is used to select the package (see
Table 165: Package selection (OPT7)
).
Flash memory readout protection
Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first, after which the device can be reprogrammed. Refer to
Section 4.3.1: Readout protection on page 33 and the
ST7 Flash Programming Reference Manual for more details.
Note: Readout protection is not supported if LVD is enabled.
0: Readout protection enabled
1: Readout protection disabled
Table 164.
Option byte 1 bit description
Bit Name
OPT7
OPT6
PKG1
RSTC
Function
Package selection bit 1
This option bit, with the PKG0 bit, selects the package (see
RESET clock cycle selection
This option bit selects the number of CPU cycles applied during the
RESET phase and when exiting Halt mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
258/276 Doc ID 17660 Rev 1
ST72521xx-Auto
Note:
Device configuration and ordering information
Table 164.
Option byte 1 bit description (continued)
Bit Name Function
OPT5:4
OPT0
OSCTYPE[1:0]
PLLOFF
Oscillator type
These option bits select the ST7 main clock source type.
00: Clock source = Resonator oscillator
01: Reserved
10: Clock source = Internal RC oscillator
11: Clock source = External source
OPT3:1 OSCRANGE[2:0]
Oscillator range
When the resonator oscillator type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. Otherwise, these bits are used to select the normal operating frequency range (see
Table 166: Oscillator frequency range selection (OPT3:1) ).
PLL activation
This option bit activates the PLL which allows multiplication by two of the main input clock frequency. The PLL must not be used with the internal RC oscillator or with external clock source. The PLL is guaranteed only with an input frequency between 2 and 4 MHz.
0: PLL x2 enabled
1: PLL x2 disabled
Caution : The PLL can be enabled only if the “OSCRANGE” (OPT3:1) bits are configured to “MP - 2~4 MHz”. Otherwise, the device functionality is not guaranteed.
Table 165.
Package selection (OPT7)
Version Selected package
M
(A)R
LQFP80
LQFP64
PKG1
1
1
PKG0
1
0
On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
Table 166.
Oscillator frequency range selection (OPT3:1)
OSCRANGE
Typical frequency range
2 1
LP
MP
MS
HS
1~2 MHz
2~4 MHz
4~8 MHz
8~16 MHz
0
0
0
0
0
0
1
1
0
0
1
0
1
Doc ID 17660 Rev 1 259/276
Device configuration and ordering information ST72521xx-Auto
The following
serves as a guide for ordering.
Figure 121. ST72F521xxx-Auto Flash commercial product structure
Example: ST72 F 521 R 9 T A X S
Product class
ST72 microcontroller
Family type
F = Flash
Sub-family type
521 = 521 sub-family
Pin count
AR = 64 pins 10 x 10 mm
R = 64 pins 14 x 14 mm
M = 80 pins 14 x 14 mm
Program memory size
6 = 32 Kbytes
9 = 60 Kbytes
Package type
T = LQFP
Temperature range
A = -40 °C to 85 °C
C = -40 °C to 125 °C
Tape and Reel conditioning options (left blank if Tray)
TR or R = Pin 1 left-oriented
TX or X = Pin 1 right-oriented (EIA 481-C compliant)
ECOPACK/Fab code
Blank or E = Lead-free ECOPACK
®
Phoenix Fab
S = Lead-free ECOPACK
®
Catania Fab
1.
For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com
or contact the ST Sales Office nearest to you.
260/276 Doc ID 17660 Rev 1
ST72521xx-Auto Device configuration and ordering information
22.2 ROM device ordering information and transfer of customer code
Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh.
Complete the appended ST72521-Auto Microcontroller FASTROM/ROM Option List on page 264 to communicate the selected options to STMicroelectronics and check for regular updates of the option list on the ST website or ask your ST representative.
Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred.
The following
and
serve as guides for ordering. The
STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Caution: The Readout Protection binary value is inverted between ROM and Flash products. The option byte checksum will differ between ROM and Flash.
Doc ID 17660 Rev 1 261/276
Device configuration and ordering information ST72521xx-Auto
Figure 122. ST72P521xxx-Auto FastROM commercial product structure
Example: ST72 P 521 T A /xxx X S
Product class
ST72 microcontroller
Family type
P = FastROM
Sub-family type
521= 521 sub-family
Package type
T = LQFP
Temperature range
A = -40 °C to 85 °C
C = -40 °C to 125 °C
Code name
Defined by
STMicroelectronics.
Denotes ROM code, pinout and program memory size.
Tape and Reel conditioning options (left blank if Tray)
TR or R = Pin 1 left-oriented
TX or X = Pin 1 right-oriented (EIA 481-C compliant)
ECOPACK/Fab code
Blank or E = Lead-free ECOPACK
®
Phoenix Fab
S = Lead-free ECOPACK
®
Catania Fab
262/276 Doc ID 17660 Rev 1
ST72521xx-Auto Device configuration and ordering information
Figure 123. ST72521xxx-Auto ROM commercial product structure
Example: ST72 521 T A /xxx X S
Product class
ST72 microcontroller
521 = 521sub-family
Package type
T = LQFP
Temperature range
A = -40 °C to 85 °C
C = -40 °C to 125 °C
Code name
Defined by
STMicroelectronics.
Denotes ROM code, pinout and program memory size.
Tape and Reel conditioning options (left blank if Tray)
TR or R = Pin 1 left-oriented
TX or X = Pin 1 right-oriented (EIA 481-C compliant)
ECOPACK/Fab code
Blank or E = Lead-free ECOPACK
®
Phoenix Fab
S = Lead-free ECOPACK
®
Catania Fab
Doc ID 17660 Rev 1 263/276
Device configuration and ordering information ST72521xx-Auto
ST72521-Auto Microcontroller FASTROM/ROM Option List
(Last update: July 2010)
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The FASTROM/ROM code name is assigned by STMicroelectronics.
FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
------------------------------------------------------------------------------------------------------------------------------------------------------
FASTROM DEVICE: 60K 32K
------------------------------------------------------------------------------------------------------------------------------------------------------
LQFP80 14x14:
LQFP64 14x14:
LQFP64 10x10:
[ ] ST72P521(M9)T
[ ] ST72P521(R9)T
[ ] ST72P521(AR9)T
[ ] ST72P521(R9)T
[ ] ST72P521(AR9)T
-------------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------------
ROM DEVICE: 60K 32K
-------------------------------------------------------------------------------------------------------------------------------------------------------
LQFP80 14x14: [ ] ST72521B(M9)T
LQFP64 14x14:
LQFP64 10x10:
[ ] ST72521B(R9)T
[ ] ST72521B(AR9)T
[ ] ST72521B(R9)T
[ ] ST72521B(AR9)T
-------------------------------------------------------------------------------------------------------------------------------------------------------
Conditioning (check only one option):
[ ] Tape & Reel
Temperature range : [ ] A (-40° to +85°C)
[ ] C (-40° to +125°C)
[ ] Tray
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 characters max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock Source Selection: [ ] Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal RC
[ ] External Clock (sets MP Medium Power resonator in Option Byte)
PLL
(1)(2)
[ ] Disabled [ ] Enabled
[ ] Med.threshold
LVD Reset
Reset Delay
[ ] Disabled
[ ] 256 Cycles
[ ] High threshold
[ ] 4096 Cycles
[ ] Low threshold
Watchdog Selection [ ] Software Activation [ ] Hardware Activation
Halt when Watchdog on [ ] Reset [ ] No reset
Readout Protection [ ] Disabled [ ] Enabled
Date . . . . . . . . . . . . . . . . . Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1: PLL must be disabled if internal RC Network is selected.
Note 2: The PLL can be enabled only if the resonator is configured to “Medium Power: 2~4 MHz”.
CAUTION: The Readout Protection binary value is inverted between ROM and Flash products. The option byte checksum will differ between ROM and Flash.
Please download the latest version of this option list from www.st.com.
264/276 Doc ID 17660 Rev 1
ST72521xx-Auto Device configuration and ordering information
22.3.1 Introduction
Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers.
ST offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing ST7 applications. Starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. ST evaluation boards are open-design, embedded systems, which are developed and documented to serve as references for your application design. They include sample application software to help you demonstrate, learn about and implement your ST7’s features.
22.3.3 Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to
16 Kbytes of code.
The range of hardware tools includes cost effective ST7-DVP3 series emulators. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface.
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board.
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 socket boards which provide all the sockets required for programming any of the devices in a specific ST7 subfamily on a platform that can be used with any tool with incircuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.
For additional ordering codes for spare parts, accessories and tools available for the ST7
(including from third party manufacturers), refer to the online product selector at www.st.com/mcu.
Doc ID 17660 Rev 1 265/276
Device configuration and ordering information ST72521xx-Auto
Table 167.
STMicroelectronics development tools
Emulation Programming
Supported products
ST7 DVP3 series
Emulator Connection kit
ST7 EMU3 series
Emulator
Active probe and T.E.B.
ICC socket board
ST72521M,
ST72F521M
ST72521R,
ST72F521R
ST72521AR,
ST72F521AR
ST7MDT20-
DVP3
ST7MDT20-
T80/DVP
ST7MDT20-
T64/DVP
ST7MDT20-
T6A/DVP
1.
Add suffix /EU, /UK, /US for the power supply of your region.
ST7MDT20M-
EMU3
Table 168.
Suggested list of socket types
Device
Socket
(supplied with ST7MDT20M-EMU3)
LQFP80 14 X 14
LQFP64 14 x14
LQFP64 10 x10
YAMAICHI IC149-080-*51-*5
CAB 3303262
YAMAICHI IC149-064-*75-*5
ST7MDT20M-
TEB
ST7SB20M/xx
(1)
Emulator adapter
(supplied with ST7MDT20M-EMU3)
YAMAICHI ICP-080-7
CAB 3303351
YAMAICHI ICP-064-6
22.3.5 Socket and emulator adapter information
Note:
For information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in
.
Before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device.
For footprint and other mechanical information about these sockets and adapters, refer to the manufacturer’s datasheet.
Related documentation
ST7 Visual Develop Software Key Debugging Features (AN 978)
ST7 Visual Develop for ST7 Cosmic C toolset users (AN 1938)
ST7 Visual Develop for ST7 Metroworks C toolset users (AN 1939)
ST7 Visual Develop for ST7 Assembler Linker toolset users (AN 1940)
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23.1 All Flash and ROM devices
23.1.1 External RC option
The external RC clock source option described in previous datasheet revisions is no longer supported and has been removed from this specification.
23.1.2 Safe connection of OSC1/OSC2 pins
The OSC1 and/or OSC2 pins must not be left unconnected, otherwise the ST7 main oscillator may start and, in this configuration, could generate an f
OSC
clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state.
Refer to
Section 6.4: Multi-oscillator (MO) on page 41 .
23.1.3 Reset pin protection with LVD enabled
As mentioned in Note 2
below Figure 105: RESET pin protection when LVD is enabled on page 241
, when the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line.
If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt controller does not recognize the source of the interrupt and, by default, passes the RESET vector address to the CPU.
Workaround
To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.
23.1.5 External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either DDR and OR. Any input signal edge during this period will not be detected and will not generate an interrupt.
This case can typically occur if the application refreshes the port configuration registers at intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after writing to the PxOR or PxDDR registers. If there is a level change (depending on the sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction with three extra PUSH instructions before executing the interrupt routine (this is to make the call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical 1 cycle duration and the interrupt has been missed. This may lead to occurrence of same interrupt twice (one hardware and another with software call).
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To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is changed to level '0' inside the interrupt routine. When a level change is detected, the semaphore status is checked. If it is ‘1’, it means that the last interrupt has been missed. In this case, the interrupt routine is invoked with the call instruction.
There is another possible case, that is, if PxOR or PxDDR are written to with global interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’ when the level change is detected. Detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. If it is ‘1’, it means that the last interrupt was missed and the interrupt routine is invoked with the call instruction.
To implement the workaround, the following software sequence is to be followed for writing into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt sensitivity. The software sequence is given for both cases (global interrupts disabled / global interrupts enabled):
Case 1: Writing to PxOR or PxDDR with global interrupts enabled:
LD A,#01
LD sema,A
; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A
; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A
; Write to PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A
; store the level after writing to PxOR/PxDDR
LD A,X
; check for falling edge cp A,#02 jrne OUT
TNZ Y jrne OUT
LD A,sema
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; check the semaphore status if edge is detected
CP A,#01 jrne OUT call call_routine
; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with global interrupts disabled:
SIM
; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A
; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A
; Write into PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A
; store the level after writing to PxOR/PxDDR
LD A,X
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; check for falling edge cp A,#$02 jrne OUT
TNZ Y jrne OUT
LD A,#$01
LD sema,A
; set the semaphore to '1' if edge is detected
RIM
; reset the interrupt mask
LD A,sema
; check the semaphore status
CP A,#$01 jrne OUT call call_routine
; call the interrupt routine
RIM
OUT:
RIM
JP while_loop
.call_routine
; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
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23.1.6 Clearing active interrupts outside interrupt routine
Note:
When an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur.
Clearing the related interrupt mask will not generate an unwanted reset.
Concurrent interrupt context
The symptom does not occur when the interrupts are handled normally, that is, when:
●
●
●
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following sequence:
Perform SIM and RIM operation before and after resetting an active interrupt request.
Example:
SIM
Reset interrupt flag
RIM
Nested interrupt context
The symptom does not occur when the interrupts are handled normally, that is, when:
●
●
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine with higher or identical priority level
● The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following sequence:
PUSH CC
SIM
Reset interrupt flag
POP CC
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23.1.7 SCI wrong break duration
Description
●
●
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
20 bits instead of 10 bits if M = 0
22 bits instead of 11 bits if M = 1
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generating one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit frequency of 19200 baud (f occurrence is around 1%.
CPU
= 8 MHz and SCIBRR = 0xC9), the wrong break duration
Workaround
If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts.
●
●
●
●
The exact sequence is:
Disable interrupts
Reset and Set TE (IDLE request)
Set and Reset SBK (Break Request)
Re-enable interrupts
23.1.8 16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on the OLVL1 and OLVL2 settings.
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If the 16-bit timer is disabled at the same time the output compare event occurs, the output compare flag then gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If the output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the timer, then the timer interrupts.
● Perform the following to disable the timer:
– TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
●
– TACSR | or TBCSR | = 0x40; // Disable the timer
Perform the following to enable the timer again:
– TACSR & or TBCSR & = ~0x40; // Enable the timer
– TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
23.1.10 CAN cell limitations
Table 169.
CAN cell limitations
Limitation
(1)
Flash
Omitted SOF bit
CPU write access (more than one cycle) corrupts CAN frame
Unexpected Message transmission
Bus Off State not entered
WKPS functionality
1.
For details see Section 17.5: List of CAN cell limitations on page 196
2.
Software workaround possible using modified WKPS bit.
3.
Limitation present on ROM Rev W and Rev Z. Not present in Flash and ROM Rev Y.
4.
Functionality modified for Unexpected Message Transmission workaround in Flash.
Legend: x = limitation present x x x
(2)
ROM x x x
(3) x
(4)
23.1.11 I
2
C multimaster
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C master after the START bit is set in the I2CCR register and before the START condition is generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a restart and Slave address to re-initiate communication.
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23.2 All Flash devices
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The internal RC can only be used if LVD is enabled.
23.2.2 I/O behavior during ICC mode entry sequence
Symptom
In 80-pin devices (Flash), both ports G and H are forced to output push-pull during ICC mode entry sequence. 80-pin ROM devices are not impacted by this issue.
Details
To enable programming of all Flash sectors, the device must leave USER mode and be configured in ICC mode. Once in ICC mode, the ICC protocol enables an ST7 microcontroller to communicate with an external controller (such as a PC). ICC mode is entered by applying 39 pulses on the ICCDATA signal during reset. To enter ICC mode, the device goes through other modes, some modes are critical because the I/Os PG[7:0] and
PH[7:0] are forced to output push-pull.
Impact on the application
The PG and PH I/O ports are forced to output push-pull during three pulses on ICCDATA. In certain circumstances, this behavior can lead to a short-circuit between the I/O signals and
V
DD
, V
SS
or an output signal of another application component.
In addition, switching these I/Os to output mode can cause the application to leave reset state, disturbing the ICC communication and preventing the user from programming the
Flash.
The LVD is not supported if readout protection is enabled.
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Table 170.
Document revision history
Date Revision
12-Jul-2010 1 Initial release
Changes
Revision history
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