PWM auto-reload timer (ART)
Figure 39.
External event detector example (3 counts) f
EXT
= f
COUNTER
ARTARR = FDh
COUNTER
FDh
OVF
FEh FFh FDh FEh FFh FDh
ST72521xx-Auto
INTERRUPT
IF OIE = 1
ARTCSR READ
INTERRUPT
IF OIE = 1
ARTCSR READ t
Note:
Note:
This mode allows the measurement of external signal pulse widths through ARTICRx registers.
Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture
Control/Status register (ARTICCSR).
These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register.
The read only input capture registers (ARTICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register).
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
After a capture detection, data transfer in the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled
(CIEx bit set). This means that the ARTICRx register has to be read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload counter cycle time (1/f
COUNTER
).
During Halt mode, if both the input capture and the external clock are enabled, the ARTICRx register value is not guaranteed if the input capture pin and the external clock change simultaneously.
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