Central processing unit (CPU)
5.3.5
ST72521xx-Auto
Table 7.
Bit Name
Arithmetic management bits
(continued)
Function
1
0
Z
C
Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Table 8.
Bit Name
Interrupt management bits
5
3
I1
I0
Function
Interrupt Software Priority 1
The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority 0
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 9.
Interrupt software priority selection
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Level
Low
High
I1
1
0
0
1
I0
0
1
0
1
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.
See
Chapter 7: Interrupts on page 52 for more details.
Stack pointer (SP) register
7
SP
15 14 13 12 11 10
0 0 0 0 0 0
9
0
8 7 6 5 4 3
Reset value: 01 FFh
2 1 0
1 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
RW RW RW RW RW RW RW RW
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Note:
Central processing unit (CPU)
The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see
Figure 8
).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a reset stack pointer instruction (RSP), the stack pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by an LD instruction.
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. The other registers are then stored in the next locations as shown in
Figure 8 .
● When an interrupt is received, the SP is decremented and the context is pushed on the stack.
● On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 8.
Stack manipulation example
CALL
Subroutine
Interrupt
Event
PUSH Y
@ 0100h
POP Y IRET RET or RSP
SP
SP
@ 01FFh
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
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