STMicroelectronics LSM6DSOP Datasheet

SCL

SDA

SPI 4-wire interface serial data output (SDO)

I²C least significant bit of the device address (SA0)

Connect to VDDIO or GND

Programmable interrupt

Power supply for I/O pins

0 V supply

Power supply

Leave unconnected

Leave unconnected

(3)

Leave unconnected

I²C / SPI mode selection

(1: SPI idle mode / I²C communication enabled;

0: SPI communication mode / I²C disabled)

I²C serial clock (SCL)

SPI serial port clock (SPC)

I²C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

1. INT must be set to '0' or left unconnected during power-on.

2. Recommended 100 nF filter capacitor.

3. Leave pin electrically unconnected and soldered to PCB.

Pin connections

The LSM6DSOP offers an I²C slave interface or SPI (3- and 4-wire) serial interface.

Figure 4. LSM6DSOP connections

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Module specifications

4 Module specifications

4.1 Mechanical characteristics

@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.

Symbol Parameter

Table 3. Mechanical characteristics

Test conditions Min.

LA_FS

Linear acceleration measurement range

G_FS

Angular rate measurement range

LA_So

G_So

Linear acceleration sensitivity

Angular rate sensitivity

FS = ±2 g

FS = ±4 g

FS = ±8 g

FS = ±16 g

FS = ±125 dps

FS = ±250 dps

FS = ±500 dps

FS = ±1000 dps

FS = ±2000 dps from -40° to +85° C LA_SoDr

G_SoDr

Linear acceleration sensitivity change vs. temperature

(3)

Angular rate sensitivity change vs. temperature

Angular rate zero-rate level

High-performance mode (HPM)

LA_TyOff

Linear acceleration zerog level offset accuracy

(4)

G_TyOff

(4)

Advanced power cycling mode (APC)

LA_TyOff

Linear acceleration zerog level offset accuracy

(4)

G_TyOff

Angular rate zero-rate level

(4)

from -40° to +85° C

Typ.

(1)

±2000

0.061

0.122

0.244

0.488

4.375

8.75

17.50

±2

±4

±8

±16

±125

±250

±500

±1000

±0.01

±0.007

Max.

LSM6DSOP

Unit g dps m g /LSB mdps/LSB

%/°C

%/°C m g dps m g dps

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LSM6DSOP

Symbol

Table 3. Mechanical characteristics (continued)

Parameter

LA_OffDr

G_OffDr

APC

RMS

(6)

RMS

Linear acceleration zerog level

change vs. temperature

Angular rate typical zero-rate level change vs. temperature

Rate noise density in highperformance mode

(5)

Gyroscope RMS noise in APC mode

Acceleration noise density in high-performance mode

(7)

Acceleration RMS noise in normal/low-power mode

(8)(9)

Acceleration RMS noise

in ultra-low-power mode

(8)(9)

Acceleration RMS noise in advanced power cycling mode

Test conditions

FS = ±2 g

Min.

Typ.

(1)

±0.1

±0.015

3.8

1.8

5.5

LA_ODR

Linear acceleration output data rate

G_ODR Angular rate output data rate

1.6

(10)

12.5

104

208

416

833

1666

3332

6664

12.5

104

208

416

833

1666

3332

6664

Vst

Linear acceleration self-test output change

(11)(12)(13)

Angular rate self-test output change

(14)(15)

FS = ±250 dps

FS = ±2000 dps

Top Operating temperature range

1. Typical specifications are not guaranteed.

2. Sensitivity values after factory calibration test and trimming.

150

-40

Module specifications

Max.

Unit m g/ °C dps/°C mdps/√Hz mdps

μ g /√Hz

1700

700

+85 m g (RMS)

Hz m g dps dps

°C

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Module specifications LSM6DSOP

3. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production.

4. Values after factory calibration test and trimming.

5. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.

6. For further information, please contact your local ST sales office or your distributor.

7. Accelerometer noise density in high-performance mode is independent of the ODR.

8. Accelerometer RMS noise in normal/low-power/ultra-low-power mode is independent of the ODR.

9. Noise RMS related to BW = ODR/2.

10. This ODR is available when the accelerometer is in low-power mode.

11. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes.

12. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of:

OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 m g at ±2 g full scale.

13. Accelerometer self-test limits are full-scale independent.

14. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes.

15. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of:

OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.

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LSM6DSOP Module specifications

4.2 Electrical characteristics

@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.

Symbol Parameter

Table 4. Electrical characteristics

Test conditions

Min.

Typ.

(1)

Max.

Unit

Vdd

IddAPC

LA_IddHP

Supply voltage

Vdd_IO Power supply for I/O

IddHP

Gyroscope and accelerometer current consumption in high-performance mode

Gyroscope and accelerometer current consumption in advanced power cycling mode

(2)

Accelerometer current consumption in high-performance mode

1.71

1.62

1.8

0.55

245

170

3.6

V mA

μA

LA_IddLP

LA_IddULP

Accelerometer current consumption in low-power mode

Accelerometer current consumption in ultra-low-power mode

ODR = 52 Hz

ODR = 1.6 Hz

ODR = 52 Hz

ODR = 1.6 Hz

ODR = 26 Hz

4.5

9.5

4.4

μA

IddPD

Ton

Gyroscope and accelerometer current consumption during powerdown

Turn-on time

35 70

μA ms

Digital high-level input voltage

0.7 *

VDD_IO

Digital low-level input voltage

0.3 *

VDD_IO

High-level output voltage I

= 4 mA

(3)

VDD_IO -

0.2

Top

Low-level output voltage

Operating temperature range

= 4 mA

the range of sensitivities of a large number of sensors (see Table 3 ).

-40

0.2

+85

1. T ypical specifications are not guaranteed.

2. Data based on characterization results.

3. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pin in order to guarantee the correct digital output voltage levels V

and V

°C

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Module specifications

4.3 Temperature sensor characteristics

@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.

LSM6DSOP

Symbol

TODR

Toff

(2)

Table 5. Temperature sensor characteristics

Parameter

Temperature refresh rate

Temperature offset

(3)

TSen

TST

Temperature sensitivity

Temperature stabilization time

(4)

T_ADC_res Temperature ADC resolution

Top Operating temperature range

Test condition Min.

Typ.

(1)

-15

-40

256

Max.

+15

500

LSB/°C

+85

1. Typical specifications are not guaranteed.

2. When the accelerometer is in Low-Power mode or Ultra-Low-Power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR.

3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.

4. Time from power ON to valid data based on characterization data.

Unit

°C

μs bit

°C

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LSM6DSOP Module specifications

4.4

4.4.1

Communication interface characteristics

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Symbol

Table 6. SPI slave timing values (in mode 3)

Value

(1)

Parameter

Min Max

Unit t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)

SPI clock cycle

SPI clock frequency

CS setup time

CS hold time

SDI input setup time

SDI input hold time

SDO valid output time

SDO output hold time

SDO output disable time

100

50 ns

MHz ns

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production

Figure 5. SPI slave timing diagram (in mode 3)

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

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Module specifications LSM6DSOP

4.4.2 I ² C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Symbol Parameter

Table 7. I ² C slave timing values

I²C standard mode

(1)

Min Max f

(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

START condition hold time

4.7

4.0

250

100

3.45

t su(SR)

Repeated START condition setup time

STOP condition setup time

4.7

t su(SP)

4 t w(SP:SR)

Bus free time between STOP and START condition

4.7

1. Data based on standard I²C protocol requirement, not tested in production.

Figure 6. I ² C slave timing diagram

I²C fast mode

(1)

Min

1.3

0.6

Max

400

100

0.6

0.9

0.6

1.3

μs

Unit kHz

μs ns

μs

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Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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LSM6DSOP

4.5

Note:

Module specifications

Absolute maximum ratings

Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 8. Absolute maximum ratings

Ratings

Vdd

STG

Supply voltage

Storage temperature range

Acceleration g for 0.2 ms

ESD Electrostatic discharge protection (HBM)

Vin

Input voltage on any control pin

(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Maximum value

-0.3 to 4.8

-40 to +125

20,000

-0.3 to Vdd_IO +0.3

Supply voltage on any pin should never exceed 4.8 V.

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.

This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.

Unit

°C g kV

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Module specifications

4.6

4.6.1

4.6.2

Terminology

LSM6DSOP

Sensitivity

Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes

An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see

Table 3 ).

Zerog and zero-rate level

Linear acceleration zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zerog offset.

Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zerog level change vs. temperature” in

Table 3 . The zero-

g level tolerance

(TyOff) describes the standard deviation of the range of zerog levels of a group of sensors.

Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time (see

Table 3 ).

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5 Digital interfaces

5.1

5.1.1

Digital interfaces

I ² C/SPI interface

The registers embedded inside the LSM6DSOP may be accessed through both the I²C and

SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3.

The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the

CS line must be tied high (i.e connected to Vdd_IO).

Pin name

SCL/SPC

SDA/SDI/SDO

SDO/SA0

Table 9. Serial interface pin description

Pin description

SPI enable

I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;

0: SPI communication mode / I²C disabled)

I²C Serial Clock (SCL)

SPI Serial Port Clock (SPC)

I²C Serial Data (SDA)

SPI Serial Data Input (SDI)

3-wire Interface Serial Data Output (SDO)

SPI Serial Data Output (SDO)

I²C less significant bit of the device address

I ² C serial interface

The LSM6DSOP I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back.

The relevant I²C terminology is provided in the table below.

Term

Transmitter

Receiver

Master

Slave

Table 10. I ² C terminology

Description

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

The device addressed by the master

There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial

DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.

The I²C interface is implemented with fast mode (400 kHz) I ² C standards as well as with standard mode.

In order to disable the I²C block, (I2C_disable) = 1 must be written in

CTRL4_C (13h)

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Digital interfaces LSM6DSOP

Command

Read

Write

Read

Write

I

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The Slave ADdress (SAD) associated to the LSM6DSOP is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two different inertial modules to the same I²C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I²C embedded inside the LSM6DSOP behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.

The increment of the address is configured by the CTRL3_C (12h) (IF_INC).

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.

Table 11

explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

SAD[6:1]

110101

Table 11. SAD+Read/Write patterns

SAD[0] = SA0 R/W

SAD+R/W

11010101 (D5h)

11010100 (D4h)

11010111 (D7h)

11010110 (D6h)

Master

Slave

Table 12. Transfer when master is writing one byte to slave

SAD + W SUB DATA

SAK SAK SAK

Master

Slave

Table 13. Transfer when master is writing multiple bytes to slave

SAD + W SUB DATA DATA

SAK SAK SAK SAK

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LSM6DSOP Digital interfaces

Master

Table 14. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA

DAT

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No

Master Acknowledge.

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Digital interfaces

5.1.2 SPI bus interface

LSM6DSOP

The LSM6DSOP SPI is a bus slave. The SPI allows writing and reading the registers of the device.

The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .

Figure 7. Read and write protocol (in mode 3)

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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When the

CTRL3_C (12h)

(IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the

CTRL3_C (12h)

(IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

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LSM6DSOP Digital interfaces

SPI read

Figure 8. SPI read protocol (in mode 3)

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The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).

bit 16-...

: data DO(...-8). Further data in multiple byte reads.

Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3)

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Digital interfaces

SPI write

LSM6DSOP

Figure 10. SPI write protocol (in mode 3)

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The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1 -7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3)

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32/107 DocID032926 Rev 5

LSM6DSOP Digital interfaces

SPI read in 3-wire mode

A 3-wire mode is entered by setting the

CTRL3_C (12h)

(SIM) bit equal to ‘1’ (SPI serial interface mode selection).

Figure 12. SPI read protocol in 3-wire mode (in mode 3)

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The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

A multiple read command is also available in 3-wire mode.

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Functionality

6 Functionality

6.1

LSM6DSOP

Operating modes

In the LSM6DSOP, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.

The LSM6DSOP has three operating modes available:

 only accelerometer active and gyroscope in power-down

 only gyroscope active and accelerometer in power-down

 both accelerometer and gyroscope sensors active with independent ODR

The accelerometer is activated from power-down by writing ODR_XL[3:0] in

CTRL1_XL

(10h)

while the gyroscope is activated from power-down by writing ODR_G[3:0] in

CTRL2_G (11h)

. For combo-mode the ODRs are totally independent.

6.2

6.2.1

Accelerometer power modes

In the LSM6DSOP, the accelerometer can be configured in five different operating modes: power-down, ultra-low-power, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the XL_HM_MODE bit in

CTRL6_C (15h) .

If XL_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz).

To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Lowpower mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.

Accelerometer ultra-low-power mode

The LSM6DSOP can be configured in ultra-low-power (ULP) mode by setting the

XL_ULP_EN bit to 1 in

CTRL5_C (14h)

register. This mode can be used in accelerometeronly mode (gyroscope sensor must be configured in power-down mode) and for ODR_XL values between 1.6 Hz and 208 Hz.

When ULP mode is intended to be used, the bit XL_HM_MODE must be set to 0.

When ULP mode is switched ON/OFF, the accelerometer must be configured in powerdown condition.

The embedded functions based on accelerometer data (6D/4D, wake-up, activity/inactivity) and the FIFO batching functionality are still supported when ULP mode is enabled.

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LSM6DSOP

6.3

Functionality

Gyroscope power modes

In the LSM6DSOP, the gyroscope can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. The operating mode

selected depends on the value of the G_HM_MODE bit in CTRL7_G (16h)

. If G_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz).

To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Lowpower mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.

6.4 Block diagram of filters

Figure 13. Block diagram of filters

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6.4.1 Block diagrams of the accelerometer filters

In the LSM6DSOP, the filtering chain for the accelerometer part is composed of the following:

 Analog filter (anti-aliasing)

 Digital filter (LPF1)

 Composite filter

Details of the block diagram appear in the following figure.

Figure 14. Accelerometer chain

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Functionality LSM6DSOP

Figure 15. Accelerometer composite filter

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1. The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode. This value is equal to

700 Hz when the accelerometer is in low-power or normal mode.

36/107 DocID032926 Rev 5

LSM6DSOP

6.4.2 Block diagrams of the gyroscope filters

Figure 16. Gyroscope digital chain

Functionality

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The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on the selected gyroscope ODR, as indicated in the following table.

Table 16. Gyroscope LPF2 bandwidth selection

Gyroscope ODR [Hz] LPF2 cutoff [Hz]

12.5

104

208

417

833

1667

3333

6667

4.2

8.3

16.6

33.0

66.8

135.9

295.5

1108.1

1320.7

1441.8

DocID032926 Rev 5 37/107

107

Functionality

6.5

LSM6DSOP

FIFO

The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out from the FIFO.

The LSM6DSOP embeds 3 kbytes of data in FIFO (up to 9 kbytes with the compression feature enabled) to store the following data:

 Gyroscope

 Accelerometer

 Timestamp

 Temperature

Writing data in the FIFO can be configured to be triggered by the accelerometer / gyroscope data-ready signal

The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFO-dedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by the user. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.

The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO.

FIFO allows correct reconstruction of the timestamp information for each sensor stored in

FIFO. If a change in the ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device.

Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbytes data stored in FIFO and take advantage of interface communication length for

FIFO flushing and communication power consumption.

The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and

FIFO_CTRL2 (08h)

using the WTM[8:0] bits. To monitor the FIFO status, dedicated

registers ( FIFO_STATUS1 (3Ah) ,

INT_CTRL register description

) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT pin of these status events, the configuration can be set in

INT_CTRL (0Dh)

and

The FIFO buffer can be configured according to six different modes:

 Bypass mode

 FIFO mode

 Continuous mode

 Continuous-to-FIFO mode

 Bypass-to-continuous mode

 Bypass-to-FIFO mode

Each mode is selected by the FIFO_MODE_[2:0] bits in the

FIFO_CTRL4 (0Ah)

38/107 DocID032926 Rev 5

LSM6DSOP

6.5.1

6.5.2

6.5.3

6.5.4

Functionality

Bypass mode

In Bypass mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not operational

and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode.

FIFO mode

In FIFO mode (

FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 001) data from the output

channels are stored in the FIFO until it is full.

To reset FIFO content, Bypass mode should be selected by writing

FIFO_CTRL4

(0Ah)

(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO mode by writing

FIFO_CTRL4 (0Ah)

(FIFO_MODE_[2:0]) to '001'.

The FIFO buffer memorizes up to 9 kbytes of data (with compression enabled) but the depth of the FIFO can be resized by setting the WTM [8:0] bits in

FIFO_CTRL1 (07h)

and

FIFO_CTRL2 (08h) . If the STOP_ON_WTM bit in FIFO_CTRL2 (08h)

is set to '1', FIFO depth is limited up to the WTM [8:0] bits in

FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)

Continuous mode

Continuous mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous

FIFO update: as new data arrives, the older data is discarded.

A FIFO threshold flag

FIFO_STATUS2 (3Bh) (FIFO_WTM_IA) is asserted when the number

of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (07h)

and

FIFO_CTRL2

(08h)

(WTM [8:0]).

It is possible to route the FIFO_WTM_IA flag to FIFO_CTRL2 (08h)

to the INT pin by writing in register

INT_CTRL (0Dh)

(INT_FIFO_TH) = '1'.

A full-flag interrupt can be enabled,

INT_CTRL (0Dh) (INT_FIFO_FULL) = '1', in order to

indicate FIFO saturation and eventually read its content all at once.

If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag in

In Continuous-to-FIFO mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO

is asserted.

In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in

FIFO_STATUS1 (3Ah) and

FIFO_STATUS2

(3Bh)

(DIFF_FIFO_[9:0]).

Continuous-to-FIFO mode

behavior changes according to the trigger event detected in one of the following interrupt events:

 Wake-up

 D6D

When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.

When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.

DocID032926 Rev 5 39/107

107

Functionality

6.5.5

6.5.6

6.5.7

LSM6DSOP

Bypass-to-Continuous mode

In Bypass-to-Continuous mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = '100'), data

measurement storage inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).

FIFO behavior changes according to the trigger event detected in one of the following interrupt events:

 Wake-up

 D6D

Bypass-to-FIFO mode

In Bypass-to-FIFO mode (

FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = '111'), data

measurement storage inside FIFO operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).

FIFO behavior changes according to the trigger event detected in one of the following interrupt events:

 Wake-up

 D6D

FIFO reading procedure

The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes: one tag byte (

FIFO_DATA_OUT_TAG (78h) , in order to identify the

sensor, and 6 bytes of fixed data (FIFO_DATA_OUT registers from (79h) to (7Eh)).

The DIFF_FIFO_[9:0] field in the

FIFO_STATUS1 (3Ah) and

registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO.

In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The flag COUNTER_BDR_IA in

COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch) ). This allows triggering

alerts that the counter reaches a selectable threshold (CNT_BDR_TH_[10:0] field in

the reading of FIFO with the desired latency of one single sensor. The sensor is selectable

using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh) . As for the other

FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT pin by asserting

the corresponding bit (INT_CNT_BDR of INT_CTRL (0Dh) .

In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in

EMB_FUNC_EN_B (05h) (embedded functions registers bank) and the

FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h) . When compression is enabled, it is also

possible to force writing non-compressed data at a selectable rate using the

UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h) .

Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling the ODR_CHG_EN bit in

FIFO_CTRL2 (08h)

40/107 DocID032926 Rev 5

LSM6DSOP

7 Application hints

7.1 LSM6DSOP electrical connections

Figure 17. LSM6DSOP electrical connections

Application hints

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1. Leave pin electrically unconnected and soldered to PCB.

The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1,

C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device

(common design practice).

The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the I²C/SPI interface.

The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the I²C/SPI interface.

DocID032926 Rev 5 41/107

107

The procedure to correctly initialize the device is as follows:

INT: Leave unconnected or connect with external pull-down during power-on. Pull-up must be avoided on this pin.

2. Properly configure the device: a) SPI case: I2C_disable = 1 in

CTRL4_C (13h)

and DEVICE_CONF = 1 in

CTRL9_XL (18h) .

b) I²C case: I2C_disable = 0 (default) in

CTRL4_C (13h)

and DEVICE_CONF = 1 in

CTRL9_XL (18h)

Table 17. Internal pin status pin# Name

Pin function

SDO SPI 4-wire interface serial data output (SDO)

SA0 I²C least significant bit of the device address (SA0)

Pin status

Default: input without pull-up.

Pull-up is enabled if bit SDO_PU_EN = 1 in reg 02h.

RES Connect to VDDIO or GND

Default: input without pull-up.

Pull-up is enabled if bit PU_EN = 1 in reg 14h in pull-up configuration registers (see Note to enable pull-up).

Default: input without pull-up.

Pull-up is enabled if bit PU_EN = 1 in reg 14h in pull-up configuration registers (see Note to enable pull-up).

Default: input with pull-down

(1)

INT Programmable interrupt

VDDIO Power supply for I/O pins

GND 0 V supply

VDD

Power supply

Leave unconnected

I²C/SPI mode selection

(1:SPI idle mode / I²C communication enabled;

0: SPI communication mode / I²C disabled)

SCL

SDA

I²C / SPI serial port clock (SPC)

I²C (SDA) / SPI serial data input (SDI) /

3-wire interface serial data output (SDO)

1. INT must be set to '0' or left unconnected during power-on.

Default: output forced to ground

Default: input with pull-up

Default: input with pull-up.

Pull-up is disabled if bit I2C_disable = 1 in reg 13h and

DEVICE_CONF = 1 in reg 18h.

Default: input without pull-up

Note:

Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.

The procedure to enable the pull-up on pins 2 and 3 is as follows:

1. Write 40h in register at address 01h (enable access to

PU_CONFIG (14h) )

2. Write 08h in register at address 14h (enable the pull-up on pins 2 and 3)

3. Write 00h in register at address 01h (disable access to

PU_CONFIG (14h) )

Register mapping

8 Register mapping

LSM6DSOP

FUNC_CFG_ACCESS

PIN_CTRL

RESERVED

FIFO_CTRL1

FIFO_CTRL2

FIFO_CTRL3

FIFO_CTRL4

COUNTER_BDR_REG1

COUNTER_BDR_REG2

INT_CTRL

RESERVED

WHO_AM_I

CTRL1_XL

CTRL2_G

CTRL3_C

CTRL4_C

CTRL5_C

CTRL6_C

CTRL7_G

CTRL8_XL

CTRL9_XL

CTRL10_C

ALL_INT_SRC

WAKE_UP_SRC

RESERVED

D6D_SRC

STATUS_REG

RESERVED

OUT_TEMP_L

The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.

Name

Table 18. Registers address map

Register address

Type

Hex Binary

03-06

00000001

00000010

00000111

00001000

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

0001 0111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

Default

00000000

00111111

00000000

01101100

00000000

00000100

00000000

11100000

00000000 output output output output output

Comment

44/107 DocID032926 Rev 5

LSM6DSOP

Name

FIFO_STATUS1

FIFO_STATUS2

RESERVED

TIMESTAMP0

TIMESTAMP1

TIMESTAMP2

TIMESTAMP3

RESERVED

LIR_CONFIG

RESERVED

INT_CFG

THS_6D

RESERVED

WAKE_UP_THS

OUT_TEMP_H

OUTX_L_G

OUTX_H_G

OUTY_L_G

OUTY_H_G

OUTZ_L_G

OUTZ_H_G

OUTX_L_A

OUTX_H_A

OUTY_L_A

OUTY_H_A

OUTZ_L_A

OUTZ_H_A

RESERVED

EMB_FUNC_STATUS_

MAINPAGE

FSM_STATUS_A_

MAINPAGE

FSM_STATUS_B_

MAINPAGE

RESERVED

Table 18. Registers address map (continued)

Register address

Type

Hex Binary

Default

2E-34

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101 output output output output output output output output output output output output output

R 35 00110101 output

00110110

00110111 output output

44-55

38-39

3C-3F

00111010

00111011

01000000

01000001

01000010

01000011

01010110

01010111

01011000

01011001

01011010

01011011 output output output output output output

00000000

Register mapping

Comment

DocID032926 Rev 5 45/107

107

Register mapping

Name

WAKE_UP_DUR

RESERVED

MD1_CFG

RESERVED

INT_PD_CFG

INTERNAL_FREQ_FINE

RESERVED

X_OFS_USR

Y_OFS_USR

Z_OFS_USR

RESERVED

FIFO_DATA_OUT_TAG

FIFO_DATA_OUT_X_L

FIFO_DATA_OUT_X_H

FIFO_DATA_OUT_Y_L

FIFO_DATA_OUT_Y_H

FIFO_DATA_OUT_Z_L

FIFO_DATA_OUT_Z_H

Table 18. Registers address map (continued)

Register address

Type

Hex Binary

Default

00000000

76-77

5F-61

64-72

01011100

01011101

01011110

01100010

01100011

01110011

01110100

01110101

01111000

01111001

01111010

01111011

01111100

01111101

01111110

00000000

00000000 output

00000000

00000000 output output output output output output output

LSM6DSOP

Comment

46/107 DocID032926 Rev 5

LSM6DSOP

9 Register description

Register description

The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of

7 bits, are used to identify them and to write the data through the serial interface.

9.1

9.2

FUNC_CFG_ACCESS (01h)

Enable embedded functions register (r/w)

FUNC_CFG_

ACCESS

PU_REG_

ACCESS

Table 19. FUNC_CFG_ACCESS register

(1)

1. This bit must be set to '0' for the correct operation of the device.

Enable access to PU_CONFIG (14h)

Table 20. FUNC_CFG_ACCESS register description

Enable access to the embedded functions configuration registers

(1)

FUNC_CFG_ACCESS

Default value: 0

PU_REG_ACCESS

Default value: 0

1. Details concerning the embedded functions configuration registers are available in

Section Embedded functions register mapping and

Section 11: Embedded functions register description .

PIN_CTRL (02h)

SDO pin pull-up enable/disable register (r/w)

Table 21. PIN_CTRL register

(1)

SDO_

PU_EN

(2)

1. This bit must be set to '0' for the correct operation of the device.

2. This bit must be set to '1' for the correct operation of the device.

SDO_PU_EN

Table 22. PIN_CTRL register description

Enable pull-up on SDO pin

(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)

DocID032926 Rev 5 47/107

107

Register description

9.3 FIFO_CTRL1 (07h)

FIFO control register 1 (r/w)

WTM7

WTM[7:0]

LSM6DSOP

WTM6

Table 23. FIFO_CTRL1 register

WTM5 WTM4 WTM3 WTM2 WTM1 WTM0

Table 24. FIFO_CTRL1 register description

FIFO watermark threshold, in conjunction with WTM8 in

FIFO_CTRL2 (08h)

1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO

Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.

9.4 FIFO_CTRL2 (08h)

FIFO control register 2 (r/w)

Table 25. FIFO_CTRL2 register

STOP_ON

_WTM

FIFO_

COMPR_

RT_EN

(1)

ODRCHG

_EN

1: FIFO depth is limited to threshold level, defined in FIFO_CTRL1 (07h) and

1. This bit must be set to '0' for the correct operation of the device.

UNCOPTR

_RATE_1

UNCOPTR

_RATE_0

WTM8

STOP_ON_

WTM

Table 26. FIFO_CTRL2 register description

Sensing chain FIFO stop values memorization at threshold level

(0: FIFO depth is not limited (default);

FIFO_CTRL2 (08h) )

FIFO_COMPR_

RT_EN

(1)

Enables/Disables compression algorithm runtime

ODRCHG_EN Enables ODR CHANGE virtual sensor to be batched in FIFO

UNCOPTR_

RATE_[1:0]

WTM8

This field configures the compression algorithm to write non-compressed data at each rate.

(0: Non-compressed data writing is not forced;

1: Non-compressed data every 8 batch data rate;

2: Non-compressed data every 16 batch data rate;

3: Non-compressed data every 32 batch data rate)

FIFO watermark threshold, in conjunction with WTM_FIFO[7:0] in FIFO_CTRL1

(07h)

1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO

Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.

1. This bit is effective if the FIFO_COMPR_EN bit of

EMB_FUNC_EN_B (05h) is set to 1.

48/107 DocID032926 Rev 5

LSM6DSOP

9.5

Register description

FIFO_CTRL3 (09h)

FIFO control register 3 (r/w)

BDR_

GY_3

BDR_GY_[3:0]

BDR_XL_[3:0]

BDR_

GY_2

Table 27. FIFO_CTRL3 register

BDR_

GY_1

BDR_

GY_0

BDR_

XL_3

BDR_

XL_2

BDR_

XL_1

BDR_

XL_0

Table 28. FIFO_CTRL3 register description

Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data.

(0000: Gyro not batched in FIFO (default);

0001: 12.5 Hz;

0010: 26 Hz;

0011: 52 Hz;

0100: 104 Hz;

0101: 208 Hz;

0110: 417 Hz;

0111: 833 Hz;

1000: 1667 Hz;

1001: 3333 Hz;

1010: 6667 Hz;

1011: 6.5 Hz;

1100-1111: not allowed)

Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.

(0000: Accelerometer not batched in FIFO (default);

0001: 12.5 Hz;

0010: 26 Hz;

0011: 52 Hz;

0100: 104 Hz;

0101: 208 Hz;

0110: 417 Hz;

0111: 833 Hz;

1000: 1667 Hz;

1001: 3333 Hz;

1010: 6667 Hz;

1011: 1.6 Hz;

1100-1111: not allowed)

DocID032926 Rev 5 49/107

107

Register description

9.6 FIFO_CTRL4 (0Ah)

FIFO control register 4 (r/w)

LSM6DSOP

DEC_TS_

BATCH_1

DEC_TS_

BATCH_0

Table 29. FIFO_CTRL4 register

ODR_T_

BATCH_1

ODR_T_

BATCH_0

(1)

1. This bit must be set to '0' for the correct operation of the device.

FIFO_

MODE2

FIFO_

MODE1

FIFO_

MODE0

DEC_TS_

BATCH_[1:0]

ODR_T_

BATCH_[1:0]

FIFO_

MODE[2:0]

Table 30. FIFO_CTRL4 register description

Selects decimation for timestamp batching in FIFO. Writing rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.

(00: Timestamp not batched in FIFO (default);

01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];

10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];

11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])

Selects batching data rate (writing frequency in FIFO) for temperature data

(00: Temperature not batched in FIFO (default);

01: 1.6 Hz;

10: 12.5 Hz;

11: 52 Hz)

FIFO mode selection

(000: Bypass mode: FIFO disabled;

001: FIFO mode: stops collecting data when FIFO is full;

010: Reserved;

011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then

FIFO mode;

100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then

Continuous mode;

101: Reserved;

110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;

111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)

50/107 DocID032926 Rev 5

LSM6DSOP

9.7

Register description

COUNTER_BDR_REG1 (0Bh)

Counter batch data rate register 1 (r/w) dataready

_pulsed

RST_

COUNTER

_BDR

Table 31. COUNTER_BDR_REG1 register

TRIG_

COUNTER

_BDR

(1)

CNT_BDR

_TH_10

1. This bit must be set to '0' for the correct operation of the device.

CNT_BDR

_TH_9

CNT_BDR

_TH_8

dataready_pulsed

Table 32. COUNTER_BDR_REG1 register description

Enables pulsed data-ready mode

(0: Data-ready latched mode (returns to 0 only after an interface reading)

(default);

1: Data-ready pulsed mode (the data ready pulses are 75 μs long)

RST_

COUNTER_BDR

TRIG_

COUNTER_BDR

CNT_BDR_TH_

[10:8]

Resets the internal counter of batching events for a single sensor.

This bit is automatically reset to zero if it was set to ‘1’.

Selects the trigger for the internal counter of batching events between XL and gyro.

(0: XL batching event;

1: GYRO batching event)

In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch)

, sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the

COUNTER_BDR_IA flag in

In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh) , sets

is set to ‘1’.

9.8 COUNTER_BDR_REG2 (0Ch)

Counter batch data rate register 2 (r/w)

CNT_BDR

_TH_7

CNT_BDR

_TH_6

Table 33. COUNTER_BDR_REG2 register

CNT_BDR

_TH_5

CNT_BDR

_TH_4

CNT_BDR

_TH_3

CNT_BDR

_TH_2

CNT_BDR

_TH_1

CNT_BDR

_TH_0

CNT_BDR_

TH_[7:0]

Table 34. COUNTER_BDR_REG2 register description

the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in

FIFO_STATUS2 (3Bh) is set to ‘1’.

DocID032926 Rev 5 51/107

107

Register description

9.9 INT_CTRL (0Dh)

INT pin control register (r/w)

LSM6DSOP

DEN_

DRDY_ flag

DEN_DRDY_flag

INT_CNT_BDR

INT_FIFO_FULL

INT_FIFO_OVR

INT_FIFO_TH

INT_BOOT

INT_DRDY_G

INT_DRDY_XL

INT_CNT_

BDR

Table 35. INT_CTRL register

INT_

FIFO

_FULL

INT_

FIFO_

OVR

INT_

FIFO_TH

INT_

BOOT

INT_

DRDY_G

INT_

DRDY_XL

Table 36. INT_CTRL register description

Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT pin

Enables COUNTER_BDR_IA interrupt on INT

Enables FIFO full flag interrupt on INT pin.

Enables FIFO overrun interrupt on INT pin.

Enables FIFO threshold interrupt on INT pin.

Enables boot status on INT pin

Enables gyroscope data-ready interrupt on INT pin.

Enables accelerometer data-ready interrupt on INT pin.

9.10 WHO_AM_I (0Fh)

WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Ch.

0 1 1

Table 37. WhoAmI register

0 1 1 0 0

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LSM6DSOP Register description

9.11 CTRL1_XL (10h)

Accelerometer control register 1 (r/w)

Table 38. CTRL1_XL register

ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL

LPF2_XL_

1. This bit must be set to '0' for the correct operation of the device.

Table 39. CTRL1_XL register description

ODR_XL[3:0] Accelerometer ODR selection (see

Table )

FS[1:0]_XL Accelerometer full-scale selection (see

Table )

LPF2_XL_EN

Accelerometer high-resolution selection

(0: output from first stage digital filtering selected (default);

1: output from LPF2 second filtering stage selected)

(1)

ODR_

XL3

ODR_

XL2

ODR_

XL1

Table 40. Accelerometer ODR register setting

ODR_

XL0

ODR selection [Hz] when

XL_HM_MODE = 1 in

CTRL6_C (15h)

ODR selection [Hz] when

XL_HM_MODE = 0 in

CTRL6_C (15h)

0 x

Power-down

1.6 Hz (low power only)

12.5 Hz (low power)

26 Hz (low power)

52 Hz (low power)

104 Hz (normal mode)

208 Hz (normal mode)

416 Hz (high performance)

833 Hz (high performance)

1.66 kHz (high performance)

3.33 kHz (high performance)

6.66 kHz (high performance)

Not allowed

Power-down

12.5 Hz (high performance)

26 Hz (high performance)

52 Hz (high performance)

104 Hz (high performance)

208 Hz (high performance)

416 Hz (high performance)

833 Hz (high performance)

1.66 kHz (high performance)

3.33 kHz (high performance)

6.66 kHz (high performance)

Not allowed

FS[1:0]_XL

Table 41. Accelerometer full-scale selection

XL_FS_MODE = ‘0’

in CTRL8_XL (17h)

XL_FS_MODE = ‘1’ in

CTRL8_XL (17h)

00 (default)

±2 g

±16 g

±4 g

±8 g

±2 g

±4 g

±8 g

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107

Register description

9.12 CTRL2_G (11h)

Gyroscope control register 2 (r/w)

Table 42. CTRL2_G register

ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS1_G FS0_G

1. This bit must be set to '0' for the correct operation of the device.

ODR_G[3:0]

FS[1:0]_G

FS_125

Table 43. CTRL2_G register description

Gyroscope output data rate selection . Default value: 0000

(Refer to

Table )

Gyroscope chain full-scale selection

(00: ±250 dps;

01: ±500 dps;

10: ±1000 dps;

11: ±2000 dps)

Selects gyro chain full-scale ±125 dps

(0: FS selected through bits FS[1:0]_G;

1: FS set to ±125 dps)

FS_125

LSM6DSOP

(1)

Table 44. Gyroscope ODR configuration setting

ODR_G3 ODR_G2 ODR_G1 ODR_G0

ODR [Hz] when

G_HM_MODE = 1

in CTRL7_G (16h)

Power down

12.5 Hz (low power)

26 Hz (low power)

52 Hz (low power)

104 Hz (normal mode)

208 Hz (normal mode)

416 Hz (high performance)

833 Hz (high performance)

1.66 kHz (high performance)

3.33 kHz (high performance

6.66 kHz (high performance

Not available

ODR [Hz] when

G_HM_MODE = 0

in CTRL7_G (16h)

Power down

12.5 Hz (high performance)

26 Hz (high performance)

52 Hz (high performance)

104 Hz (high performance)

208 Hz (high performance)

416 Hz (high performance)

833 Hz (high performance)

1.66 kHz (high performance)

3.33 kHz (high performance)

6.66 kHz (high performance)

Not available

54/107 DocID032926 Rev 5

LSM6DSOP Register description

9.13 CTRL3_C (12h)

Control register 3 (r/w)

BOOT BDU

Table 45. CTRL3_C register

H_LACTIVE PP_OD SIM

1. This bit must be set to '0' for the correct operation of the device.

IF_INC

BOOT

BDU

H_LACTIVE

PP_OD

SIM

IF_INC

SW_RESET

(1)

SW_RESET

Table 46. CTRL3_C register description

Reboots memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

This bit is automatically cleared.

Block Data Update. Default value: 0

(0: continuous update;

1: output registers are not updated until MSB and LSB have been read)

Interrupt activation level. Default value: 0

(0: interrupt output pins active high; 1: interrupt output pins active low)

Push-pull/open-drain selection on INT pin. Default value: 0

(0: push-pull mode; 1: open-drain mode)

SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface)

Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI). Default value: 1

(0: disabled; 1: enabled)

Software reset. Default value: 0

(0: normal mode; 1: reset device)

This bit is automatically cleared.

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107

Register description LSM6DSOP

9.14 CTRL4_C (13h)

Control register 4 (r/w)

(1)

SLEEP_G 0

Table 47. CTRL4_C register

DRDY_

MASK

I2C_disable

1. This bit must be set to '0' for the correct operation of the device.

SLEEP_G

DRDY_MASK

I2C_disable

LPF1_SEL_G

LPF1_

SEL_G

(00: Self-test disabled; Other: refer to Table

Table 48. CTRL4_C register description

Enables gyroscope Sleep mode. Default value:0

(0: disabled; 1: enabled)

Enables data available

(0: disabled;

1: mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).

Disables I²C interface. Default value: 0

(0: SPI and I²C interfaces enabled (default); 1: I²C interface disabled)

Enables gyroscope digital LPF1; the bandwidth can be selected through

FTYPE [2:0] in

CTRL6_C (15h)

(0: disabled; 1: enabled)

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LSM6DSOP Register description

9.15 CTRL5_C (14h)

Control register 5 (r/w)

Table 49. CTRL5_C register

XL_ULP_EN ROUNDING1 ROUNDING0 0

(1)

ST1_G ST0_G

1. This bit must be set to '0' for the correct operation of the device.

ST1_XL ST0_XL

XL_ULP_EN

Table 50. CTRL5_C register description

Accelerometer ultra-low-power mode enable

(1)

. Default value: 0

(0: Ultra-low-power mode disabled; 1: Ultra-low-power mode enabled)

ROUNDING[1:0]

ST[1:0]_G

ST[1:0]_XL

Circular burst-mode (rounding) read from the output registers. Default value: 00

(00: no rounding;

01: accelerometer only;

10: gyroscope only;

11: gyroscope + accelerometer)

Angular rate sensor self-test enable. Default value: 00

)

Linear acceleration sensor self-test enable. Default value: 00

(00: Self-test disabled; Other: refer to Table

)

1. Further details about the accelerometer ultra-low-power mode are provided in Section

Accelerometer ultra-low-power mode .

ST1_G

Table 51. Angular rate sensor self-test mode selection

ST0_G Self-test mode

Normal mode

Positive sign self-test

Not allowed

Negative sign self-test

Table 52. Linear acceleration sensor self-test mode selection

ST1_XL ST0_XL Self-test mode

Normal mode

Positive sign self-test

Negative sign self-test

Not allowed

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107

Register description LSM6DSOP

9.16 CTRL6_C (15h)

Control register 6 (r/w)

(1)

Table 53. CTRL6_C register

XL_HM_MODE

USR_

OFF_W

FTYPE_2 FTYPE_1 FTYPE_0

1. This bit must be set to '0' for the correct operation of the device.

XL_HM_MODE

USR_OFF_W

Table 54. CTRL6_C register description

High-performance operating mode disable for accelerometer. Default value: 0

(0: high-performance operating mode enabled;

1: high-performance operating mode disabled)

Weight of XL user offset bits of registers

X_OFS_USR (73h)

, Y_OFS_USR (74h)

Z_OFS_USR (75h)

(0 = 2

-10 g /LSB;

1 = 2

-6 g /LSB)

Gyroscope's low-pass filter (LPF1) bandwidth selection

FTYPE[2:0]

FTYPE

[2:0]

100

101

110

111

000

001

010

011

12.5 Hz 26 Hz

4.2

4.1

3.9

8.3

7.8

6.7

8.3

Table 55. Gyroscope LPF1 bandwidth selection

52 Hz 104 Hz 208 Hz 416 Hz 833 Hz 1.67 kHz 3.33 kHz 6.67 kHz

16.7

16.8

13.4

9.7

16.6

33.0

31.0

19.0

11.5

33.0

62.4

43.2

23.1

12.2

67.0

136.6

130.5

120.3

137.1

86.7

48.0

24.6

12.4

239.2

192.4

154.2

281.8

96.6

49.4

25.0

12.5

304.2

220.7

166.6

453.2

99.6

49.8

25.1

12.5

328.5

229.6

170.1

559.2

335.5

232.0

171.1

609.0

58/107 DocID032926 Rev 5

LSM6DSOP Register description

9.17 CTRL7_G (16h)

Control register 7 (r/w)

Table 56. CTRL7_G register

G_HM_

MODE

HP_EN_G HPM1_G HPM0_G 0

(1)

USR_

OFF_ON

_ OUT

Figure 15: Accelerometer composite filter . Default value: 0

1. This bit must be set to '0' for the correct operation of the device.

G_HM_MODE

HP_EN_G

HPM_G[1:0]

USR_OFF_

ON_ OUT

Table 57. CTRL7_G register description

Disables high-performance operating mode for gyroscope. Default: 0

(0: high-performance operating mode enabled;

1: high-performance operating mode disabled)

Enables gyroscope digital high-pass filter. The filter is enabled only if the gyro is in HP mode. Default value: 0

(0: HPF disabled; 1: HPF enabled)

Gyroscope digital HP filter cutoff selection. Default: 00

(00: 16 mHz;

01: 65 mHz;

10: 260 mHz;

11: 1.04 Hz)

Enables accelerometer user offset correction block; it's valid for the low-pass path - see

(0: accelerometer user offset correction block bypassed;

1: accelerometer user offset correction block enabled)

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107

Register description LSM6DSOP

9.18 CTRL8_XL (17h)

Control register 8 (r/w)

HPCF_XL

Table 58. CTRL8_XL register

HPCF_XL

HP_REF_

MODE_XL

FASTSETTL

_MODE_XL

HP_SLOPE

_XL_EN

1. This bit must be set to '0' for the correct operation of the device.

(1)

LOW_PASS

_ON_6D

HPCF_XL_[2:0]

HP_REF_

MODE_XL

FASTSETTL

_MODE_XL

Table 59. CTRL8_XL register description

Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to

Table .

Enables accelerometer high-pass filter reference mode (valid for high-pass path -

HP_SLOPE_XL_EN bit must be ‘1’). Default value: 0

(0: disabled, 1: enabled

(1)

)

Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after writing this bit. Active only during device exit from power- down mode. Default value: 0

(0: disabled, 1: enabled)

HP_SLOPE_

XL_EN

Accelerometer slope filter / high-pass filter selection. Refer to Figure

LOW_PASS

_ON_6D

LPF2 on 6D function selection. Refer to

Figure . Default value: 0

(0: ODR/2 low-pass filtered data sent to 6D interrupt function;

1: LPF2 output data sent to 6D interrupt function)

1. When enabled, the first output data have to be discarded.

Filter type

Low pass

High pass

Table 60. Accelerometer bandwidth configurations

HP_SLOPE_

XL_EN

LPF2_XL_EN HPCF_XL_[2:0] Bandwidth

010

011

100

101

110

111

000

001

110

111

000

001

010

011

100

101

ODR/2

ODR/4

ODR/10

ODR/20

ODR/45

ODR/100

ODR/200

ODR/400

ODR/800

SLOPE (ODR/4)

ODR/10

ODR/20

ODR/45

ODR/100

ODR/200

ODR/400

ODR/800

60/107 DocID032926 Rev 5

LSM6DSOP

/3)

RXWSXW

Register description

Figure 18. Accelerometer block diagram

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/3)

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DocID032926 Rev 5 61/107

107

Register description LSM6DSOP

9.19 CTRL9_XL (18h)

Control register 9 (r/w)

(1)

Table 61. CTRL9_XL register

(2)

DEVICE_

CONF

1. This bit must be set to '1' for the correct operation of the device.

2. This bit must be set to '0' for the correct operation of the device.

DEVICE_CONF

Table 62. CTRL9_XL register description

Enables the proper device configuration. Default value: 0

It is recommended to always set this bit to 1 during device configuration.

(0: default; 1: enabled)

9.20 CTRL10_C (19h)

Control register 10 (r/w)

(1)

Table 63. CTRL10_C register

TIMESTAMP

_EN

1. This bit must be set to '0' for the correct operation of the device.

TIMESTAMP0 (40h), TIMESTAMP1 (41h),

TIMESTAMP_EN

Table 64. CTRL10_C register description

Enables timestamp counter. default value: 0

(0: disabled; 1: enabled)

The counter is readable in

TIMESTAMP2 (42h), and TIMESTAMP3 (43h) .

In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).

62/107 DocID032926 Rev 5

LSM6DSOP Register description

9.21 ALL_INT_SRC (1Ah)

Source register for all interrupts (r)

TIMESTAMP_

ENDCOUNT

Table 65. ALL_INT_SRC register

SLEEP_

CHANGE_IA

D6D_IA 0 0 WU_IA 0

Table 66. ALL_INT_SRC register description

TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms

SLEEP_CHANGE_IA

D6D_IA

Detects change event in activity/inactivity status. Default value: 0

(0: change status not detected; 1: change status detected)

Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0

(0: change in position not detected; 1: change in position detected)

WU_IA

Wake-up event status. Default value: 0

(0: event not detected, 1: event detected)

9.22 WAKE_UP_SRC (1Bh)

Wake-up interrupt source register (r)

SLEEP_

CHANGE_IA

Table 67. WAKE_UP_SRC register

SLEEP_

STATE

WU_IA X_WU Y_WU Z_WU

SLEEP_

CHANGE_IA

SLEEP_

STATE

WU_IA

X_WU

Y_WU

Z_WU

Table 68. WAKE_UP_SRC register description

Detects change event in activity/inactivity status. Default value: 0

(0: change status not detected; 1: change status detected)

Sleep status bit. Default value: 0

(0: Activity status; 1: Inactivity status)

Wakeup event detection status. Default value: 0

(0: wakeup event not detected; 1: wakeup event detected.)

Wakeup event detection status on X-axis. Default value: 0

(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)

Wakeup event detection status on Y-axis. Default value: 0

(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)

Wakeup event detection status on Z-axis. Default value: 0

(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)

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107

Register description LSM6DSOP

9.23 D6D_SRC (1Dh)

Portrait, landscape, face-up and face-down source register (r)

0 D6D_IA

Table 69. D6D_SRC register

ZH ZL YH YL XH XL

D6D_

Table 70. D6D_SRC register description

Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0

(0: change position not detected; 1: change position detected)

Z-axis high event (over threshold). Default value: 0

(0: event not detected; 1: event (over threshold) detected)

Z-axis low event (under threshold). Default value: 0

(0: event not detected; 1: event (under threshold) detected)

Y-axis high event (over threshold). Default value: 0

(0: event not detected; 1: event (over-threshold) detected)

Y-axis low event (under threshold). Default value: 0

(0: event not detected; 1: event (under threshold) detected)

X-axis high event (over threshold). Default value: 0

(0: event not detected; 1: event (over threshold) detected)

X-axis low event (under threshold). Default value: 0

(0: event not detected; 1: event (under threshold) detected)

9.24 STATUS_REG (1Eh)

Status register (r).

TDA

GDA

XLDA

0 0

Table 71. STATUS_REG register

0 0 TDA

Table 72. STATUS_REG register description

Temperature new data available. Default: 0

(0: no set of data is available at temperature sensor output;

1: a new set of data is available at temperature sensor output)

Gyroscope new data available. Default value: 0

(0: no set of data available at gyroscope output;

1: a new set of data is available at gyroscope output)

Accelerometer new data available. Default value: 0

(0: no set of data available at accelerometer output;

1: a new set of data is available at accelerometer output)

GDA XLDA

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LSM6DSOP Register description

9.25 OUT_TEMP_L (20h), OUT_TEMP_H (21h)

Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.

Temp7 Temp6

Table 73. OUT_TEMP_L register

Temp5 Temp4 Temp3 Temp2 Temp1

Temp15 Temp14

Table 74. OUT_TEMP_H register

Temp13 Temp12 Temp11 Temp10 Temp9

Temp[15:0]

Table 75. OUT_TEMP register description

Temperature sensor output data

The value is expressed as two’s complement sign extended on the MSB.

Temp0

Temp8

9.26 OUTX_L_G (22h) and OUTX_H_G (23h)

Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D[15:0]

D6 D5

Table 76. OUTX_L_G register

D4 D3 D2

D13

Table 77. OUTX_H_G register

D12 D11 D10 D14

Table 78. OUTX_H_G register description

Pitch axis (X) angular rate value

9.27 OUTY_L_G (24h) and OUTY_H_G (25h)

Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a

16-bit word in two’s complement.

D15

D[15:0]

D6 D5

Table 79. OUTY_L_G register

D4 D3 D2

D13

Table 80. OUTY_H_G register

D12 D11 D10 D14

Table 81. OUTY_H_G register description

Roll axis (Y) angular rate value

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107

Register description LSM6DSOP

9.28 OUTZ_L_G (26h) and OUTZ_H_G (27h)

Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D[15:0]

D6 D5

Table 82. OUTZ_L_G register

D4 D3 D2

D13

Table 83. OUTZ_H_G register

D12 D11 D10 D14

Table 84. OUTZ_H_G register description

Yaw axis (Z) angular rate value

9.29 OUTX_L_A (28h) and OUTX_H_A (29h)

Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D[15:0]

D6 D5

Table 85. OUTX_L_A register

D4 D3 D2

D13

Table 86. OUTX_H_A register

D12 D11 D10 D14

Table 87. OUTX_H_A register description

X-axis linear acceleration value.

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LSM6DSOP Register description

9.30 OUTY_L_A (2Ah) and OUTY_H_A (2Bh)

Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D[15:0]

D6 D5

Table 88. OUTY_L_A register

D4 D3 D2

D13

Table 89. OUTY_H_A register

D12 D11 D10 D14

Table 90. OUTY_H_A register description

Y-axis linear acceleration value

9.31 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)

Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D[15:0]

D6 D5

Table 91. OUTZ_L_A register

D4 D3 D2

D13

Table 92. OUTZ_H_A register

D12 D11 D10 D14

Table 93. OUTZ_H_A register description

Z-axis linear acceleration value

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Register description LSM6DSOP

9.32 EMB_FUNC_STATUS_MAINPAGE (35h)

Embedded function status register (r).

IS_FSM_LC 0

Table 94. EMB_FUNC_STATUS_MAINPAGE register

0 0 0 0 0

IS_FSM_LC

Table 95. EMB_FUNC_STATUS_MAINPAGE register description

Interrupt status bit for FSM long counter timeout interrupt event.

(1: interrupt detected; 0: no interrupt)

9.33 FSM_STATUS_A_MAINPAGE (36h)

Finite State Machine status register (r).

Table 96. FSM_STATUS_A_MAINPAGE register

IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1

IS_FSM8

IS_FSM7

IS_FSM6

IS_FSM5

IS_FSM4

IS_FSM3

IS_FSM2

IS_FSM1

Table 97. FSM_STATUS_A_MAINPAGE register description

Interrupt status bit for FSM8 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM7 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM6 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM5 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM4 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM3 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM2 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM1 interrupt event.

(1: interrupt detected; 0: no interrupt)

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LSM6DSOP Register description

9.34 FSM_STATUS_B_MAINPAGE (37h)

Finite State Machine status register (r).

Table 98. FSM_STATUS_B_MAINPAGE register

IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9

IS_FSM16

IS_FSM15

IS_FSM14

IS_FSM13

IS_FSM12

IS_FSM11

IS_FSM10

IS_FSM9

Table 99. FSM_STATUS_B_MAINPAGE register description

Interrupt status bit for FSM16 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM15 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM14 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM13 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM12 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM11 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM10 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM9 interrupt event.

(1: interrupt detected; 0: no interrupt)

9.35 FIFO_STATUS1 (3Ah)

FIFO status register 1 (r)

DIFF_

FIFO_7

DIFF_

FIFO_[7:0]

DIFF_

FIFO_6

Table 100. FIFO_STATUS1 register

DIFF_

FIFO_5

DIFF_

FIFO_4

DIFF_

FIFO_3

DIFF_

FIFO_2

Table 101. FIFO_STATUS1 register description

Number of unread sensor data (TAG + 6 bytes) stored in FIFO

DIFF_

FIFO_1

DIFF_

FIFO_0

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Register description LSM6DSOP

9.36 FIFO_STATUS2 (3Bh)

FIFO status register 2 (r)

FIFO_

WTM_IA

FIFO_

WTM_IA

FIFO_

OVR_IA

FIFO_

FULL_IA

COUNTER_

BDR_IA

FIFO_OVR_

LATCHED

DIFF_

FIFO_[9:8]

FIFO_

OVR_IA

Table 102. FIFO_STATUS2 register

FIFO_

FULL_IA

COUNTER

_BDR_IA

FIFO_OVR_

LATCHED

DIFF_

FIFO_9

DIFF_

FIFO_8

Table 103. FIFO_STATUS2 register description

FIFO watermark status. Default value: 0

(0: FIFO filling is lower than WTM;

1: FIFO filling is equal to or greater than WTM)

Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1

(07h) .

FIFO overrun status. Default value: 0

(0: FIFO is not completely filled; 1: FIFO is completely filled)

Smart FIFO full status. Default value: 0

(0: FIFO is not full; 1: FIFO will be full at the next ODR)

Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in

COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)

. Default value: 0

This bit is reset when these registers are read.

Latched FIFO overrun status. Default value: 0

This bit is reset when this register is read.

Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00

In conjunction with DIFF_FIFO[7:0] in

FIFO_STATUS1 (3Ah)

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LSM6DSOP Register description

9.37 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)

Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 μs.

D31 D30

Table 104. TIMESTAMP output registers

D29 D28 D27 D26 D25 D24

D23 D22 D21 D20 D19 D18 D17 D16

D15 D14 D13 D12 D11 D10 D9 D8

D[31:0]

D6 D5 D4 D3 D2

Table 105. TIMESTAMP output register description

Timestamp output registers: 1LSB = 25 μs

D1 D0

9.38 LIR_CONFIG (56h)

Activity/inactivity functions, configuration of filtering (r/w).

(1)

INT_CLR

_ON_

READ

Table 106. LIR_CONFIG register

SLEEP_

STATUS_

ON_INT

SLOPE_

FDS

1. This bit must be set to '0' for the correct operation of the device.

LIR

INT_CLR_ON_

READ

SLEEP_STATUS

_ON_INT

SLOPE_FDS

LIR

Table 107. LIR_CONFIG register description

This bit allows immediately clearing the latched interrupts of an event detection upon the read of the corresponding status register. It must be set to 1 together with LIR. Default value: 0

(0: latched interrupt signal cleared at the end of the ODR period;

1: latched interrupt signal immediately cleared)

Activity/inactivity interrupt mode configuration.

If the INT_SLEEP_CHANGE bit is enabled, drives the sleep status or sleep change on the INT pin. Default value: 0

(0: sleep change notification on INT pin; 1: sleep status reported on INT pin)

HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.

Default value: 0

(0: SLOPE filter applied; 1: HPF applied)

Latched Interrupt. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

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Register description LSM6DSOP

9.39 INT_CFG (58h)

Enables interrupt and inactivity functions (r/w).

INTERRUPTS_

ENABLE

INACT_

EN1

Table 108. INT_CFG register

INACT_

EN0

(1)

1. This bit must be set to '0' for the correct operation of the device.

INTERRUPTS_

ENABLE

Table 109. INT_CFG register description

Enable basic interrupts (6D/4D, wake-up, inactivity). Default value: 0

(0: interrupt disabled; 1: interrupt enabled)

INACT_EN[1:0]

Enable activity/inactivity (sleep) function. Default value: 00

(00: stationary/motion-only interrupts generated, XL and gyro do not change;

01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change;

10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode;

11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode)

9.40 THS_6D (59h)

Portrait/landscape position and 4D/6D function threshold register (r/w).

D4D_

SIXD_

THS1

SIXD_

THS0

Table 110. THS_6D register

(1)

1. This bit must be set to '0' for the correct operation of the device.

D4D_EN

SIXD_THS[1:0]

For details, refer to Table .

Table 111. THS_6D register description

4D orientation detection enable. Z-axis position detection is disabled.

Default value: 0

(0: disabled; 1: enabled)

Threshold for 4D/6D function. Default value: 00

SIXD_THS[1:0]

Table 112. Threshold for D4D/D6D function

Threshold value

80 degrees

70 degrees

60 degrees

50 degrees

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LSM6DSOP Register description

9.41 WAKE_UP_THS (5Bh)

Wake-up configuration (r/w)

Table 113. WAKE_UP_THS register

(1)

USR_OFF

_ON_WU

WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0

1. This bit must be set to '0' for the correct operation of the device.

USR_OFF_

ON_WU

WK_THS[5:0]

Table 114. WAKE_UP_THS register description

Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the wakeup function.

Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in

WAKE_UP_DUR (5Ch)

. Default value: 000000

9.42 WAKE_UP_DUR (5Ch)

Wakeup and sleep mode functions duration setting register (r/w)

(1)

WAKE_

DUR1

Table 115. WAKE_UP_DUR register

WAKE_

DUR0

WAKE_

THS_W

SLEEP_

DUR3

1. This bit must be set to '0' for the correct operation of the device.

SLEEP_

DUR2

SLEEP_

DUR1

SLEEP_

DUR0

WAKE_DUR[1:0]

WAKE_THS_W

SLEEP_DUR[3:0]

Table 116. WAKE_UP_DUR register description

Wake up duration event. Default: 00

1LSB = 1 ODR_time

Weight of 1 LSB of wakeup threshold. Default: 0

(0: 1 LSB = FS_XL / (2

);

) )

Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)

1 LSB = 512 ODR

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Register description

9.43 MD1_CFG (5Eh)

Functions routing on INT register (r/w)

Table 117. MD1_CFG register

INT_

SLEEP_

CHANGE

(1)

INT_WU 0

SLEEP_STATUS_ON_INT bit in LIR_CONFIG (56h) register.

1. This bit must be set to '0' for the correct operation of the device.

INT_6D

INT_EMB_

FUNC

INT_SLEEP_

CHANGE

(1)

INT_WU

INT_6D

INT_EMB_FUNC

Table 118. MD1_CFG register description

Routing of activity/inactivity recognition event on INT. Default: 0

(0: routing of activity/inactivity event on INT disabled;

1: routing of activity/inactivity event on INT enabled)

Routing of wakeup event on INT. Default value: 0

(0: routing of wakeup event on INT disabled;

1: routing of wakeup event on INT enabled)

Routing of 6D event on INT. Default value: 0

(0: routing of 6D event on INT disabled;

1: routing of 6D event on INT enabled)

Routing of embedded functions event on INT. Default value: 0

(0: routing of embedded functions event on INT disabled;

1: routing embedded functions event on INT enabled)

1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the

LSM6DSOP

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LSM6DSOP Register description

9.44 INT_PD_CFG (62h)

INT pull-down register (r/w)

(1)

Table 119. INT_PD_CFG register

weight depends on USR_OFF_W in CTRL6_C (15h) . The value must be in the

PD_DIS_

INT

1. This bit must be set to '0' for the correct operation of the device.

PD_DIS_INT

Table 120. INT_PD_CFG register description

This bit allows disabling the INT pull-down.

(0: Pull-down on INT enabled (pull-down is effectively connected only when no interrupts are routed to the INT pin);

1: Pull-down on INT disabled (pull-down not connected).

9.45 INTERNAL_FREQ_FINE (63h)

Internal frequency register (r)

FREQ_

FINE7

FREQ_

FINE6

Table 121. INTERNAL_FREQ_FINE register

FREQ_

FINE5

FREQ_

FINE4

FREQ_

FINE3

FREQ_

FINE2

FREQ_

FINE1

FREQ_

FINE0

FREQ_FINE[7:0]

Table 122. INTERNAL_FREQ_FINE register description

Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%. 8-bit format, 2's complement.

9.46 X_OFS_USR (73h)

Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis.

X_OFS_

USR_7

X_OFS_

USR_6

Table 123. X_OFS_USR register

X_OFS_

USR_5

X_OFS_

USR_4

X_OFS_

USR_3

X_OFS_

USR_2

X_OFS_

USR_1

X_OFS_

USR_0

X_OFS_USR_

[7:0]

Table 124. X_OFS_USR register description

Accelerometer X-axis user offset correction expressed in two’s complement,

range [-127 127].

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Register description LSM6DSOP

9.47 Y_OFS_USR (74h)

Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally subtracted from the acceleration value measured on the Y-axis.

Y_OFS_

USR_7

Y_OFS_

USR_[7:0]

Y_OFS_

USR_6

Table 125. Y_OFS_USR register

Y_OFS_

USR_5

Y_OFS_

USR_4

Y_OFS_

USR_3

Y_OFS_

USR_2

Y_OFS_

USR_1

Y_OFS_

USR_0

Table 126. Y_OFS_USR register description

Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on USR_OFF_W in

CTRL6_C (15h)

. The value must be in the range

[-127, +127].

9.48 Z_OFS_USR (75h)

Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis.

Z_OFS_

USR_7

Z_OFS_

USR_[7:0]

Z_OFS_

USR_6

Table 127. Z_OFS_USR register

Z_OFS_

USR_5

Z_OFS_

USR_4

Z_OFS_

USR_3

Z_OFS_

USR_2

Z_OFS_

USR_1

Z_OFS_

USR_0

Table 128. Z_OFS_USR register description

Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on USR_OFF_W in

CTRL6_C (15h)

. The value must be in the range

[-127, +127].

9.49 FIFO_DATA_OUT_TAG (78h)

FIFO tag register (r)

TAG_

SENSOR_

TAG_

SENSOR_

Table 129. FIFO_DATA_OUT_TAG register

TAG_

SENSOR_

TAG_

SENSOR_

TAG_

SENSOR_

TAG_CNT

TAG_

PARITY

Table 130. FIFO_DATA_OUT_TAG register description

TAG_SENSOR_[4:0]

FIFO tag: identifies the sensor in:

FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) ,

FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) , and

FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)

For details, refer to Table FIFO

TAG_CNT_[1:0]

TAG_PARITY

2-bit counter which identifies sensor time slot

Parity check of TAG content

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LSM6DSOP

TAG_SENSOR_[4:0]

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

Register description

Table 131. FIFO tag

Sensor name

Gyroscope NC

Accelerometer NC

Temperature

Timestamp

CFG_Change

Accelerometer NC_T_2

Accelerometer NC_T_1

Accelerometer 2xC

Accelerometer 3xC

Gyroscope NC_T_2

Gyroscope NC_T_1

Gyroscope 2xC

Gyroscope 3xC

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9.50 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H

(7Ah)

FIFO data output X (r)

D15

Table 132. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers

D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

Table 133. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description

D[15:0] FIFO X-axis output

9.51 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H

(7Ch)

FIFO data output Y (r)

D15

Table 134. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers

D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

Table 135. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description

D[15:0] FIFO Y-axis output

9.52 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H

(7Eh)

FIFO data output Z (r)

D15

Table 136. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers

D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

Table 137. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description

D[15:0] FIFO Z-axis output

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10

Embedded functions register mapping

Embedded functions register mapping

The table given below provides a list of the registers for the embedded functions available in the device and the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in

FUNC_CFG_ACCESS (01h) .

Name

Table 138. Register address map - embedded functions

Register address

Type Default

Hex Binary

00000001 PAGE_SEL

RESERVED

EMB_FUNC_EN_B

PAGE_ADDRESS

PAGE_VALUE

EMB_FUNC_INT

FSM_INT_A

FSM_INT_B

RESERVED

EMB_FUNC_STATUS

FSM_STATUS_A

FSM_STATUS_B

PAGE_RW

RESERVED

FSM_ENABLE_A

FSM_ENABLE_B

FSM_LONG_COUNTER_L r/w r/w

FSM_LONG_COUNTER_H r/w

FSM_LONG_COUNTER_CLEAR r/w

FSM_OUTS1

FSM_OUTS2

FSM_OUTS3

FSM_OUTS4 r r r r

FSM_OUTS5

FSM_OUTS6

FSM_OUTS7

FSM_OUTS8

FSM_OUTS9 r r r r r r r/w

r/w r r r/w

r/w r/w r/w r/w r/w

r/w

0E-10

18-44

00000010

00000100

00000101

00001000

00001001

00001010

00001011

00001100

00010010

00010011

00010100

00010111

01000110

01000111

01001000

01001001

01001010

01001100

01001101

01001110

01001111

01010000

01010001

01010010

01010011

01010100

00000000

00000000 output output output

00000000 output output output output output output output

00000000

00000000 output output

Comment

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Table 138. Register address map - embedded functions (continued)

Register address

Name Type Default

Hex Binary

FSM_OUTS10

FSM_OUTS11

FSM_OUTS12

FSM_OUTS13

FSM_OUTS14

FSM_OUTS15

FSM_OUTS16

RESERVED

EMB_FUNC_ODR_CFG_B

RESERVED

EMB_FUNC_INIT_B r r r r r r r

r/w

62-66

01010101

01010110

01010111

01011000

01011001

01011010

01011011

01011110

01011111

01100111 output output output output output output output

01001011

00000000

Comment

Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

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Embedded functions register description

Embedded functions register description

11.1 PAGE_SEL (02h)

Enable advanced features dedicated page (r/w)

Table 139. PAGE_SEL register

PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 PAGE_SEL0 0

(1)

1. This bit must be set to '0' for the correct operation of the device.

2. This bit must be set to '1' for the correct operation of the device.

PAGE_SEL[3:0]

Table 140. PAGE_SEL register description

Select the advanced features dedicated page

Default value: 0000

(2)

11.2 EMB_FUNC_EN_B (05h)

Embedded functions enable register (r/w)

(1)

Table 141. EMB_FUNC_EN_B register

FIFO_CO

MPR_EN

1. This bit must be set to '0' for the correct operation of the device.

1. This bit is effective if the FIFO_COMPR_RT_EN bit of FIFO_CTRL2 (08h) is set to 1.

Table 142. EMB_FUNC_EN_B register description

FIFO_COMPR_EN

(1)

Enable FIFO compression feature. Default value: 0

(0: FIFO compression feature disabled;

1: FIFO compression feature enabled)

FSM_EN

Enable Finite State Machine (FSM) feature. Default value: 0

(0: FSM feature disabled; 1: FSM feature enabled)

FSM_EN

11.3 PAGE_ADDRESS (08h)

Page address register (r/w)

PAGE_

ADDR7

PAGE_

ADDR6

Table 143. PAGE_ADDRESS register

PAGE_

ADDR5

PAGE_

ADDR4

PAGE_

ADDR3

PAGE_

ADDR2

PAGE_

ADDR1

PAGE_

ADDR0

PAGE_ADDR[7:0]

Table 144. PAGE_ADDRESS register description

After setting the bit PAGE_WRITE / PAGE_READ in register

PAGE_RW (17h)

, this register is used to set the address of the register to be written/read in the advanced features page selected through the bits PAGE_SEL[3:0] in register

PAGE_SEL (02h) .

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11.4 PAGE_VALUE (09h)

Page value register (r/w)

PAGE_

VALUE7

PAGE_

VALUE6

Table 145. PAGE_VALUE register

PAGE_

VALUE5

PAGE_

VALUE4

PAGE_

VALUE3

PAGE_

VALUE2

PAGE_

VALUE1

PAGE_

VALUE0

PAGE_VALUE[7:0]

Table 146. PAGE_VALUE register description

These bits are used to write (if the bit PAGE_WRITE = 1 in register PAGE_RW

(17h)

) or read (if the bit PAGE_READ = 1 in register

PAGE_RW (17h) ) the data

at the address PAGE_ADDR[7:0] of the selected advanced features page.

11.5 EMB_FUNC_INT (0Ah)

INT pin control register (r/w)

Each bit in this register enables a signal to be carried over INT. The pin's output will supply the OR combination of the selected signals.

Table 147. EMB_FUNC_INT register

INT_

FSM_

(1)

1. This bit must be set to '0' for the correct operation of the device.

MD1_CFG (5Eh) is set to 1.

INT_FSM_LC

(1)

Table 148. EMB_FUNC_INT register description

Routing of FSM long counter timeout interrupt event on INT. Default value: 0 (0: routing on INT disabled; 1: routing on INT enabled)

1. This bit is effective if the INT_EMB_FUNC bit of

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11.6 FSM_INT_A (0Bh)

INT pin control register (r/w).

Each bit in this register enables a signal to be carried over INT. The pin's output will supply the OR combination of the selected signals.

INT_

FSM8

INT_

FSM7

Table 149. FSM_INT_A register

INT_

FSM6

INT_

FSM5

INT_

FSM4

INT_

FSM3

INT_

FSM2

INT_FSM8

(1)

INT_FSM7

INT_FSM6

INT_FSM5

INT_FSM4

INT_FSM3

INT_FSM2

INT_FSM1

Table 150. FSM_INT_A register description

Routing of FSM8 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM7 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM6 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM5 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM4 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM3 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM2 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM1 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

1. This bit is effective if the INT_EMB_FUNC bit of

MD1_CFG (5Eh) is set to 1.

INT_

FSM1

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11.7 FSM_INT_B (0Ch)

INT pin control register (r/w).

Each bit in this register enables a signal to be carried over INT. The pin's output will supply the OR combination of the selected signals.

INT_

FSM16

INT_

FSM15

Table 151. FSM_INT_B register

INT_

FSM14

INT_

FSM13

INT_

FSM12

INT_

FSM11

INT_

FSM10

INT_FSM16

(1)

INT_FSM15

INT_FSM14

INT_FSM13

INT_FSM12

INT_FSM11

INT_FSM10

INT_FSM9

Table 152. FSM_INT_B register description

Routing of FSM16 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM15 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM14 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM13 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM12 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM11 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM10 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

Routing of FSM9 interrupt event on INT. Default value: 0

(0: routing on INT disabled; 1: routing on INT enabled)

1. This bit is effective if the INT_EMB_FUNC bit of

MD1_CFG (5Eh) is set to 1.

INT_

FSM9

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11.8 EMB_FUNC_STATUS (12h)

Embedded function status register (r).

IS_FSM_LC

Table 153. EMB_FUNC_STATUS register

0 0 0 0 0

Table 154. EMB_FUNC_STATUS register description

Interrupt status bit for FSM long counter timeout interrupt event.

(1: interrupt detected; 0: no interrupt)

11.9 FSM_STATUS_A (13h)

Finite State Machine status register (r).

Table 155. FSM_STATUS_A register

IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1

IS_FSM8

IS_FSM7

IS_FSM6

IS_FSM5

IS_FSM4

IS_FSM3

IS_FSM2

IS_FSM1

Table 156. FSM_STATUS_A register description

Interrupt status bit for FSM8 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM7 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM6 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM5 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM4 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM3 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM2 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM1 interrupt event.

(1: interrupt detected; 0: no interrupt)

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11.10 FSM_STATUS_B (14h)

Finite State Machine status register (r).

Table 157. FSM_STATUS_B register

IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9

IS_FSM16

IS_FSM15

IS_FSM14

IS_FSM13

IS_FSM12

IS_FSM11

IS_FSM10

IS_FSM9

Table 158. FSM_STATUS_B register description

Interrupt status bit for FSM16 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM15 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM14 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM13 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM12 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM11 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM10 interrupt event.

(1: interrupt detected; 0: no interrupt)

Interrupt status bit for FSM9 interrupt event.

(1: interrupt detected; 0: no interrupt)

11.11 PAGE_RW (17h)

Enable read and write mode of advanced features dedicated page (r/w)

EMB_

FUNC_LIR

PAGE_

WRITE

Table 159. PAGE_RW register

PAGE_

READ

(1)

1. This bit must be set to '0' for the correct operation of the device.

1. Page selected by PAGE_SEL[3:0] in PAGE_SEL (02h)

EMB_FUNC_LIR

PAGE_WRITE

PAGE_READ

Table 160. PAGE_RW register description

Latched Interrupt mode for Embedded Functions. Default value: 0

(0: Embedded Functions interrupt request not latched;

1: Embedded Functions interrupt request latched)

Enable writes to the selected advanced features dedicated page

(1)

Default value: 0

(1: enable; 0: disable)

Enable reads from the selected advanced features dedicated page

(1)

Default value: 0

(1: enable; 0: disable)

FSM_LONG_COUNTER_CLEAR (4Ah) register.

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11.12 FSM_ENABLE_A (46h)

FSM enable register (r/w).

Table 161. FSM_ENABLE_A register

FSM8_EN FSM7_EN FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN

FSM8_EN

FSM7_EN

FSM6_EN

FSM5_EN

FSM4_EN

FSM3_EN

FSM2_EN

FSM1_EN

Table 162. FSM_ENABLE_A register description

FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled)

FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled)

FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled)

FSM5 enable. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled)

FSM4 enable. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled)

FSM3 enable. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled)

FSM2 enable. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled)

FSM1 enable. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled)

11.13 FSM_ENABLE_B (47h)

FSM enable register (r/w).

Table 163. FSM_ENABLE_B register

FSM16_EN FSM15_EN FSM14_EN FSM13_EN FSM12_EN FSM11_EN FSM10_EN FSM9_EN

FSM16_EN

FSM15_EN

FSM14_EN

FSM13_EN

FSM12_EN

FSM11_EN

FSM10_EN

FSM9_EN

Table 164. FSM_ENABLE_B register description

FSM16 enable. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled)

FSM15 enable. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled)

FSM14 enable. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled)

FSM13 enable. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled)

FSM12 enable. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled)

FSM11 enable. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled)

FSM10 enable. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled)

FSM9 enable. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled)

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11.14 FSM_LONG_COUNTER_L (48h) and

FSM_LONG_COUNTER_H (49h)

FSM long counter status register (r/w).

Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit in

FSM_LC_

Table 165. FSM_LONG_COUNTER_L register

FSM_LC_

Table 166. FSM_LONG_COUNTER_L register description

FSM_LC_[7:0] Long counter current value (LSbyte). Default value: 00000000

FSM_LC_

Table 167. FSM_LONG_COUNTER_H register

FSM_LC_

Table 168. FSM_LONG_COUNTER_H register description

FSM_LC_[15:8] Long counter current value (MSbyte). Default value: 00000000

11.15 FSM_LONG_COUNTER_CLEAR (4Ah)

FSM long counter reset register (r/w).

(1)

Table 169. FSM_LONG_COUNTER_CLEAR register

FSM_LC_

CLEARED

1. This bit must be set to '0' for the correct operation of the device.

FSM_LC_

CLEAR

FSM_LC_

CLEARED

Table 170. FSM_LONG_COUNTER_CLEAR register description

This read-only bit is automatically set to 1 when the long counter reset is done.

Default value: 0

FSM_LC_CLEAR Clear FSM long counter value. Default value: 0

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11.16 FSM_OUTS1 (4Ch)

FSM1 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 171. FSM_OUTS1 register

P_Y N_Y P_Z N_Z

Table 172. FSM_OUTS1 register description

FSM1 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM1 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM1 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM1 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM1 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM1 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM1 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM1 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

11.17 FSM_OUTS2 (4Dh)

FSM2 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 173. FSM_OUTS2 register

P_Y N_Y P_Z N_Z

Table 174. FSM_OUTS2 register description

FSM2 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM2 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM2 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM2 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM2 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM2 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM2 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM2 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.18 FSM_OUTS3 (4Eh)

FSM3 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 175. FSM_OUTS3 register

P_Y N_Y P_Z N_Z

Table 176. FSM_OUTS3 register description

FSM3 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM3 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM3 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM3 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM3 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM3 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM3 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM3 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V

LSM6DSOP

N_V

11.19 FSM_OUTS4 (4Fh)

FSM4 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 177. FSM_OUTS4 register

P_Y N_Y P_Z N_Z

Table 178. FSM_OUTS4 register description

FSM4 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM4 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM4 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM4 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM4 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM4 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM4 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM4 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.20 FSM_OUTS5 (50h)

FSM5 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 179. FSM_OUTS5 register

P_Y N_Y P_Z N_Z

Table 180. FSM_OUTS5 register description

FSM5 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM5 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM5 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM5 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM5 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM5 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM5 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM5 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

11.21 FSM_OUTS6 (51h)

FSM6 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 181. FSM_OUTS6 register

P_Y N_Y P_Z N_Z

Table 182. FSM_OUTS6 register description

FSM6 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM6 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM6 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM6 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM6 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM6 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM6 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM6 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.22 FSM_OUTS7 (52h)

FSM7 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 183. FSM_OUTS7 register

P_Y N_Y P_Z N_Z

Table 184. FSM_OUTS7 register description

FSM7 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM7 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM7 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM7 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM7 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM7 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM7 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM7 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V

LSM6DSOP

N_V

11.23 FSM_OUTS8 (53h)

FSM8 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 185. FSM_OUTS8 register

P_Y N_Y P_Z N_Z

Table 186. FSM_OUTS8 register description

FSM8 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM8 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM8 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM8 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM8 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM8 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM8 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM8 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.24 FSM_OUTS9 (54h)

FSM9 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 187. FSM_OUTS9 register

P_Y N_Y P_Z N_Z

Table 188. FSM_OUTS9 register description

FSM9 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM9 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM9 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM9 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM9 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM9 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM9 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM9 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

11.25 FSM_OUTS10 (55h)

FSM10 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 189. FSM_OUTS10 register

P_Y N_Y P_Z N_Z

Table 190. FSM_OUTS10 register description

FSM10 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM10 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM10 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM10 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM10 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM10 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM10 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM10 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.26 FSM_OUTS11 (56h)

FSM11 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 191. FSM_OUTS11 register

P_Y N_Y P_Z N_Z

Table 192. FSM_OUTS11 register description

FSM11 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM11 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM11 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM11 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM11 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM11 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM11 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM11 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V

LSM6DSOP

N_V

11.27 FSM_OUTS12 (57h)

FSM12 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 193. FSM_OUTS12 register

P_Y N_Y P_Z N_Z

Table 194. FSM_OUTS12 register description

FSM12 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM12 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM12 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM12 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM12 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM12 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM12 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM12 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.28 FSM_OUTS13 (58h)

FSM13 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 195. FSM_OUTS13 register

P_Y N_Y P_Z N_Z

Table 196. FSM_OUTS13 register description

FSM13 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM13 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM13 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM13 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM13 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM13 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM13 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM13 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

11.29 FSM_OUTS14 (59h)

FSM14 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 197. FSM_OUTS14 register

P_Y N_Y P_Z N_Z

Table 198. FSM_OUTS14 register description

FSM14 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM14 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM14 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM14 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM14 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM14 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM14 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM14 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.30 FSM_OUTS15 (5Ah)

FSM15 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 199. FSM_OUTS15 register

P_Y N_Y P_Z N_Z

Table 200. FSM_OUTS15 register description

FSM15 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM15 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM15 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM15 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM15 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM15 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM15 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM15 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V

LSM6DSOP

N_V

11.31 FSM_OUTS16 (5Bh)

FSM16 output register (r).

P_X

N_X

P_Y

N_Y

P_Z

N_Z

P_V

N_V

N_X

Table 201. FSM_OUTS16 register

P_Y N_Y P_Z N_Z

Table 202. FSM_OUTS16 register description

FSM16 output: positive event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM16 output: negative event detected on the X-axis.

(0: event not detected; 1: event detected)

FSM16 output: positive event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM16 output: negative event detected on the Y-axis.

(0: event not detected; 1: event detected)

FSM16 output: positive event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM16 output: negative event detected on the Z-axis.

(0: event not detected; 1: event detected)

FSM16 output: positive event detected on the vector.

(0: event not detected; 1: event detected

FSM16 output: negative event detected on the vector.

(0: event not detected; 1: event detected)

P_V N_V

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11.32 EMB_FUNC_ODR_CFG_B (5Fh)

Finite State Machine output data rate configuration register (r/w).

(1)

(2)

Table 203. EMB_FUNC_ODR_CFG_B register

FSM_

ODR1

FSM_

ODR0

1. This bit must be set to '0' for the correct operation of the device.

2. This bit must be set to '1' for the correct operation of the device.

FSM_ODR[1:0]

Table 204. EMB_FUNC_ODR_CFG_B register description

Finite State Machine ODR configuration:

(00: 12.5 Hz;

01: 26 Hz (default);

10: 52 Hz;

11: 104 Hz)

11.33 EMB_FUNC_INIT_B (67h)

Embedded functions initialization register (r/w)

(1)

Table 205. EMB_FUNC_INIT_B register

FIFO_

COMPR_

INIT

1. This bit must be set to '0' for the correct operation of the device.

Table 206. EMB_FUNC_INIT_B register description

FIFO_COMPR_INIT FIFO compression feature initialization request. Default value: 0

FSM_INIT FSM initialization request. Default value: 0

FSM_INIT

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Embedded advanced features pages

12 Embedded advanced features pages

LSM6DSOP

The table given below provides a list of the registers for the embedded advanced features page 1. These registers are accessible when PAGE_SEL[3:0] are set to 0001 in

PAGE_SEL (02h)

Table 207. Register address map - embedded advanced features page 1

Register address

Name Type Default Comment

Hex Binary

FSM_LC_TIMEOUT_L

FSM_LC_TIMEOUT_H

FSM_PROGRAMS

FSM_START_ADD_L

FSM_START_ADD_H r/w r/w r/w r/w r/w

01111010

01111011

01111100

01111110

01111111

00000000

Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

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13

Embedded advanced features register description

Embedded advanced features register description

13.1 Page 1 - Embedded advanced features registers

13.1.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)

FSM long counter timeout register (r/w).

The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

Table 208. FSM_LC_TIMEOUT_L register

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT[7:0]

Table 209. FSM_LC_TIMEOUT_L register description

FSM long counter timeout value (LSbyte). Default value: 00000000

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

Table 210. FSM_LC_TIMEOUT_H register

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT

FSM_LC_

TIMEOUT[15:8]

Table 211. FSM_LC_TIMEOUT_H register description

FSM long counter timeout value (MSbyte). Default value: 00000000

13.1.2 FSM_PROGRAMS (7Ch)

FSM number of programs register (r/w).

FSM_N_

PROG7

FSM_N_

PROG6

Table 212. FSM_PROGRAMS register

FSM_N_

PROG5

FSM_N_

PROG4

FSM_N_

PROG3

FSM_N_

PROG2

FSM_N_

PROG1

FSM_N_PROG[7:0]

Table 213. FSM_PROGRAMS register description

Number of FSM programs; must be less than or equal to 16.

Default value: 00000000

FSM_N_

PROG0

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Embedded advanced features register description LSM6DSOP

13.1.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)

FSM start address register (r/w). First available address is 0x033C.

FSM_

START7

FSM_

START6

Table 214. FSM_START_ADD_L register

FSM_

START5

FSM_

START4

FSM_

START3

FSM_

START2

FSM_

START1

Table 215. FSM_START_ADD_L register description

FSM_START[7:0] FSM start address value (LSbyte). Default value: 00000000

FSM_

START15

FSM_

START14

Table 216. FSM_START_ADD_H register

FSM_

START13

FSM_

START12

FSM_

START11

FSM_

START10

FSM_

START9

Table 217. FSM_START_ADD_H register description

FSM_START[15:8] FSM start address value (MSbyte). Default value: 00000000

FSM_

START0

FSM_

START8

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LSM6DSOP

14 Pull-up configuration register

Pull-up configuration register

The PU_CONFIG register is accessible when PU_REG_ACCESS is set to '1' in

FUNC_CFG_ACCESS (01h) .

Name

PU_CONFIG

Table 218. Pull-up configuration register

Register address

Type

Hex Binary

Default rw 14 00010100 00000000

Comment

14.1 PU_CONFIG (14h)

Pull-up configuration register (r/w)

(1)

Table 219. PU_CONFIG register

PU_EN

1. This bit must be set to '0' for the correct operation of the device.

PU_EN

Table 220. PU_CONFIG register description

Pull-up enable for pin 2 and pin 3. Default value: 0

(0: internal pull-up disabled; 1: internal pull-up enabled)