STMicroelectronics L9950 Datasheet

L9950

L9950XP

Door actuator driver

Features

■

■

■

■

■

■

■

■

■

■

■

■

■

■

■

One full bridge for 6A load (R on

=150 m



)

Two half bridges for 3A load (R on

=300 m



)

Two half bridges for 1.5A load (R on

=800 m



)

One highside driver for 6A load (R on

=100 m



)

Four highside drivers for 1.5 A load

(R on

=800 m



)

Programmable softstart function to drive loads with higher inrush currents (i.e. current

>6 A,>3 A,>1.5 A)

Very low current consumption in standby mode

(I

S

< 6



A typ; I

CC

<25



A typ; T j



85 °C)

All outputs short circuit protected

Current monitor output for 300 m



, 150 m

 and 100 m highside drivers

All outputs over temperature protected

Open load diagnostic for all outputs

Overload diagnostic for all outputs

Seperated half bridges for door lock motor

PWM control of all outputs

Charge pump output for reverse polarity protection

PowerSO-36 PowerSSO-36

Applications

■ Door actuator driver with bridges for door lock and safe lock, mirror axis control, mirror fold and highside driver for mirror defroster and four

10W-light bulbs.

Description

The L9950 and L9950XP are microcontroller driven multifunctional door actuator driver for automotive applications.Up to five DC motors and five grounded resistive loads can be driven with six half bridges and five highside drivers. The integrated standard serial peripheral interface

(SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic informations are available via SPI.

Table 1.

Device summary

Package

PowerSO-36

PowerSSO-36

September 2013

Part number (tube)

L9950

L9950XP

Order codes

Part number (tape and reel)

L9950TR

L9950XPTR

Doc ID 10311 Rev 11 1/39 www.st.com

1

1

2

Contents

Contents

3

4

L9950 - L9950XP

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10

2.5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6

SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1

Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3

Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4

Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.5

Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21

3.7

Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.8

Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9

Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10

PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.11

Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.12

Programmable soft start function to drive loads with higher inrush current .

22

Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2

Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3

Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4

Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5

Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6

Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/39 Doc ID 10311 Rev 11

5

6

L9950 - L9950XP

7

Contents

4.7

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.8

Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2

PowerSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3

PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4

PowerSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.5

PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 10311 Rev 11 3/39

List of tables

List of tables

L9950 - L9950XP

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11.

OUT1 - OUT11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 12.

Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13.

Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 14.

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 15.

DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 16.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 17.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 18.

Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 19.

SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20.

SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21.

PowerSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22.

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 23.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4/39 Doc ID 10311 Rev 11

L9950 - L9950XP

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4.

SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5.

SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6.

SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7.

SPI - driver turn-on/off timing, minimum csn hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8.

SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9.

Example of programmable soft start function for inductive loads . . . . . . . . . . . . . . . . . . . . 23

Figure 10.

Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11.

PowerSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12.

PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13.

PowerSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14.

PowerSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15.

PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16.

PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 10311 Rev 11 5/39

Block diagram and pin description

1 Block diagram and pin description

L9950 - L9950XP

Figure 1.

Block diagram

**

1k

**

**

1k

1k

**

1k

**

1k

DI

DO

CLK

CSN

PWM1

V

BAT

* Note: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition of inductive loads (e.g. TSD, POR)

Reverse

Polarity

Protection

VREG

VCC

*

100µF

100nF

100

EMC

Optimization

+

10

100nF

VS CP

VCC

Charge

Pump

µC

**

1k

CM / PWM2

100k

OUT1 xy-Mirror

Motors

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

M

M

M

Lock

Safe Lock

M

Folder

M

Exterior Light

Footstep Light

Safety Light

Turn Indicator

OUT11

Defroster

MUX

5

GND ** Note: Resistors between µC and L9950 are recommended to limit currents for negative voltage transients at VBAT (e.g. ISO type 1 pulse)

+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior

Table 2.

Pin

1, 18, 19, 36

2, 35

Pin definitions and functions

Symbol

GND

OUT11

Function

Ground.

Reference potential.

Important: for the capability of driving the full current at the outputs all pins of GND must be externally connected.

Highside driver output 11.

The output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The highside driver is a power

DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and open load protected.

Important: for the capability of driving the full current at the outputs both pins of OUT11 must be externally connected.

6/39 Doc ID 10311 Rev 11

L9950 - L9950XP Block diagram and pin description

Table 2.

Pin

Pin definitions and functions (continued)

Symbol Function

3

4

5

6, 7, 14, 15,

23, 24, 25, 28,

29, 32

8

9

10

OUT1

OUT2

OUT3

VS

CSN

Hal bridge output 1,2,3.

The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power

DMOS transistor. Each driver has an internal parasitic reverse diode

(bulk-drain-diode: highside driver from output to VS, lowside driver from

GND to output). This output is over-current and open load protected.

Power supply voltage (external reverse protection required.

For this input a ceramic capacitor as close as possible to GND is recommended.

Important: for the capability of driving the full current at the outputs all pins of VS must be externally connected.

DI

Serial data input.

The input requires CMOS logic levels and receives serial data from the microcontroller. The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred first.

CM/PWM2

Current monitor output/PWM2 input.

Depending on the selected multiplexer bits of Input Data Register this output sources an image of the instant current through the corresponding highside driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the outputs OUT9 and

OUT10.

Chip select not input/test mode.

This input is low active and requires CMOS logic levels. The serial data transfer between L9950 and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more than 7.5V is applied to CSN pin the L9950 will be switched into a test mode.

11

12

13

16,17, 20,21,

22

26

DO

VCC

CLK

OUT4

OUT5

OUT6

CP

Serial data output.

The diagnosis data is available via the SPI and this tristate output. The output will remain in tristate, if the chip is not selected by the input CSN

(CSN = high).

Logic supply voltage.

For this input a ceramic capacitor as close as possible to GND is recommended.

Serial clock input.

This input controls the internal shift register of the SPI and requires

CMOS logic levels.

Half bridge output 4,5,6: see OUT1 (pin 3).

Important: for the capability of driving the full current at the outputs both pins of OUT4 (OUT5, respectively) must be externally connected.

Charge pump output.

This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection

Doc ID 10311 Rev 11 7/39

8/39

Block diagram and pin description L9950 - L9950XP

Table 2.

Pin

27

30

31

33

34

Pin definitions and functions (continued)

Symbol Function

PWM1

OUT7,

OUT8,

OUT9,

OUT10

PWM1 input.

This input signal can be used to control the drivers OUT1-OUT8 and

OUT11 by an external PWM signal.

Highside driver output 7,8,9,10.

The output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The highside driver is a power

DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and open load protected.

Figure 2.

Configuration diagram (top view)

GND 1

OUT11 2

OUT1 3

OUT2 4

OUT3 5

VS 6

VS 7

DI 8

CM/PWM2 9

CSN 10

DO 11

VCC 12

CLK 13

VS 14

VS 15

OUT4 16

OUT4 17

GND 18

Power SO36

Chip

Leadframe

36 GND

35 OUT11

34 OUT10

33 OUT9

32 VS

31 OUT8

30 OUT7

29 VS

28 VS

27 PWM1

26 CP

25 VS

24 VS

23 VS

22 OUT6

21 OUT5

20 OUT5

19 GND

Doc ID 10311 Rev 11

L9950 - L9950XP Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality document.

Table 3.

Absolute maximum ratings

Symbol Parameter

V

S

DC supply voltage

Single pulse t max

< 400 ms

Stabilized supply voltage, logic supply V

CC

V

DI

, V

DO,

V

CLK

,

V

CSN,

V pwm1

V

CM

V

CP

I

OUT1,2,3,6,7,8,9,10

I

OUT4,5,11

Digital input/output voltage

Current monitor output

Charge pump output

Output current

Output current

Value

-0.3 to 28

40

-0.3 to 5.5

-0.3 to V

CC

+ 0.3

-0.3 to V

CC

+ 0.3

-25 to V

S

+ 11

±5

±10

Unit

V

V

V

V

V

V

A

A

Table 4.

ESD protection

Parameter

All pins

Output pins: OUT1 - OUT11

1.

HBM according to CDF-AEC-Q100-002.

2.

HBM with all unzapped pins grounded.

Table 5.

Symbol

T j

Thermal data

Parameter

Operating junction temperature

Value



4

(1)



8

(2)

Unit kV kV

Value

-40 to 150

Unit

°C

Doc ID 10311 Rev 11 9/39

Electrical specifications

2.4

L9950 - L9950XP

Temperature warning and thermal shutdown

Table 6.

Symbol

Temperature warning and thermal shutdown

Parameter

T jTW ON

Temperature warning threshold junction temperature

T jTW OFF

Temperature warning threshold junction temperature

T jTW HYS

Temperature warning hysteresis

T jSD ON

Thermal shutdown threshold junction temperature

T jSD OFF

Thermal shutdown threshold junction temperature

T jSD HYS

Thermal shutdown hysteresis

T j increasing

T j decreasing

T j increasing

T j decreasing

Min.

Typ.

Max.

Unit

-

-

130

-

-

150

-

-

5

-

-

5

150 °C

-

°C

°K

170 °C

-

°C

°K

10/39

V

S

= 8 to 16 V, V

CC

= 4.5 to 5.3 V, T j

= - 40 to 150 °C, unless otherwise specified.

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Table 7.

Symbol

Supply

Parameter Test condition

V

S

Operating supply voltage range

I

I

S

CC

I

S

+ I

CC

VS DC supply current

VS quiescent supply current

VCC DC supply current

VCC quiescent supply current

Sum quiescent supply current

V

S

= 16 V, V

CC

= 5.3 V active mode

OUT1 - OUT11 floating

V

S

= 16 V, V

CC

= 0 V standby mode

OUT1 - OUT11 floating

T test

=-40 °C, 25 °C

V

S

= 16 V, V

CC

= 5.3 V

CSN = V

CC , active mode

V

S

= 16 V, V

CC

= 5.3 V

CSN = V

CC standby mode

OUT1 - OUT11 floating

T test

=-40 °C, 25 °C

V

S

= 16 V, V

CC

= 5.3 V

CSN = V

CC standby mode

OUT1 - OUT11 floating

T test

=-40 °C, 25 °C

Min.

Typ.

Max.

Unit

7

-

-

-

-

-

-

7

4

1

25

31

28

20

12

3

50

75

V mA

µA mA

µA

µA

Doc ID 10311 Rev 11

L9950 - L9950XP Electrical specifications

Table 8.

Symbol

Overvoltage and under voltage detection

Parameter Test condition

V

SUV ON

V

SUV OFF

VS UV-threshold voltage

VS UV-threshold voltage

V

SUV hyst

V

SOV OFF

VS UV-hysteresis

VS OV-threshold voltage

VS OV-threshold voltage V

SOV ON

V

SOV hyst

VS OV-hysteresis

V

V

V

SUV ON

V

V

S

S

S

S

increasing

decreasing

- V

SUV OFF

increasing

decreasing

V

POR OFF

Power-on-reset threshold

V

POR ON

V

POR hyst

Power-on-reset threshold

V

SOV OFF

- V

SOV ON

V

CC

increasing

V

CC

decreasing

Power-on-reset hysteresis V

POR OFF

- V

POR ON

Min.

Typ.

Max.

Unit

5.9

5.5

-

18

17.5

-

-

3.1

-

-

-

0.5

-

-

-

-

1

0.3

7.2

6.5

-

-

24.5

22

-

4.4

-

V

V

V

V

V

V

V

V

V

Table 9.

Symbol

I

V

CM

CM,r

I

CM acc

Current monitor output

Parameter Test condition

Functional voltage range V

CC

= 5 V

Current monitor output ratio:

I

CM

/ I

OUT1,4,5,6,11

0 V



V

CM



4 V, VCC=5 V

Current monitor accuracy

0 V



V

CM



3.8 V,

V

CC

= 5 V, I

Out,min

=500 mA,

I

Out4,5,11,max

= 5.9 A

I

Out1,6,max

= 2.9 A

(FS = full scale= 600 µA)

Min.

0

-

-

Typ.

10.000

Max.

Unit

4 V

-

4% +

1%FS

8% +

2%FS

-

-

Table 10.

Charge pump output

Symbol Parameter

V

CP

I

CP

Charge pump output voltage

Charge pump output current

Test condition

V

S

= 8 V, I

CP

= -60 µA

V

S

= 10 V, I

CP

= -80 µA

V

S



12 V, I

CP

= -100 µA

V

CP

= V

S

+10 V, V

S

=13.5 V

Min.

Typ.

Max.

Unit

6

8

10

-

-

-

13

13

13

V

V

V

95 150 300 µA

Doc ID 10311 Rev 11 11/39

Electrical specifications L9950 - L9950XP

Table 11.

OUT1 - OUT11

Symbol Parameter r r r r r r r

ON OUT1,

ON OUT6

ON OUT2,

ON OUT3

ON OUT4,

ON OUT5 r

ON OUT7, r

ON OUT8, r

ON OUT9 , r

ON OUT10

ON OUT11

On-resistance to supply or

GND

On-resistance to supply or

GND

On-resistance to supply or

GND

On-resistance to supply

On-resistance to supply

|I

OUT1

|,

|I

OUT6

|

|I

OUT2

|,

|I

OUT3

|

|I

OUT4

|,

|I

OUT5

|

|I

OUT7

|,

|I

OUT8

|,

|I

OUT9

|,

|I

OUT10

|

Output current limitation to supply or GND

Output current limitation to supply or GND

Output current limitation to supply or GND

Output current limitation to

GND

Test condition

V

S

= 13.5 V, T

I

OUT1,6 j

= 25 °C,

=



1.5A

V

S

= 13.5 V, T

I

OUT1,6 j

= 125 °C,

=



1.5 A

I

V

S

= 8.0 V, T j

OUT1,6

= 25 °C,

=



1.5 A

V

S

= 13.5 V, T

I

OUT2,3 j

= 25 °C,

=



0.8A

V

S

= 13.5 V, T

I

OUT2,3 j

= 125 °C,

=



0.8 A

I

V

S

= 8.0 V, T j

OUT2,3

= 25 °C,

=



0.8 A

I

VS = 13.5 V, T

OUT4,5 j

= 25 °C,

=



3.0 A

I

V

S

= 13.5 V, T j

OUT4,5

= 125 °C,

=



3.0 A

I

V

S

= 8.0 V, T j

OUT4,5

= 25 °C,

=



3.0 A

V

S

= 13.5 V, T j

= 25 °C,

I

OUT7,8,9,10

= -0.8 A

V

S

= 13.5 V, T j

= 125 °C,

I

OUT7,8,9,10

= -0.8 A

V

S

= 8.0 V, T j

= 25 °C,

I

OUT7,8,9,10

= -0.8 A

V

S

= 13.5 V, T j

= 25 °C,

I

OUT11

= - 3.0 A

V

S

= 13.5 V, T j

= 125 °C,

I

OUT11

= - 3.0A

V

S

= 8.0 V, T j

= 25 °C,

I

OUT11

= - 3.0 A

Sink and source,

V

S

=13.5V

Sink and source,

V

S

= 13.5V

Sink and source,

V

S

= 13.5V

Source, V

S

= 13.5V

Min.

Typ.

Max.

Unit

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

3

1.5

6

1.5

300

450

300

800

1250

800

150

225

150

800

1250

800

100

150

100

-

-

-

-

400

600

400

1100

1700

1100

200

300

200

1100

1700

1100

150

200

150

5

2.5

10

2.5

m m m m m m m m m m m m m m m

A

A

A

A































12/39 Doc ID 10311 Rev 11

L9950 - L9950XP Electrical specifications

Table 11.

OUT1 - OUT11 (continued)

Symbol

|I

OUT11

| t d ON H t d OFF H t d ON L t d OFF L t

D HL t

D LH

I

QLH

I

QLL

I

OLD1

I

OLD23

I

OLD45

I

OLD6

I

OLD78910

I

OLD11 t dOL t

ISC

Parameter Test condition Min.

Typ.

Max.

Unit

Output current limitation to

GND

Source, V

S

= 13.5V

6

Output delay time, highside driver on

Switched-off output current highside drivers of OUT1-11

Switched-off output current lowside drivers of OUT1-6

V

S

= 13.5 V, corresponding lowside driver is not active

Output delay time, highside driver off

V

S

= 13.5 V

Output delay time, lowside driver on

V

S

= 13.5 V, corresponding highside driver is not active

Output delay time, lowside driver off

V

S

= 13.5 V

Cross current protection time, source to sink t d ON L

- t d OFF H,

Cross current protection time, sink to source t d ON H

- t d OFF L

20

50

15

80

-

-

V

OUT1-11

=0 V, standby mode

V

OUT1-11

=0 V, active mode

V

OUT1-6

= V

S

, standby mode

0

-40

0

V

OUT1-6

= V

S

, active mode -40

Open load detection current of OUT1

Open load detection current of OUT2, OUT3

Open load detection current of OUT4 and OUT5

Open load detection current of OUT6

Open load detection current of OUT7, OUT8, OUT9,

OUT10

5

15

60

30

15

Open load detection current of OUT11

Minimum duration of open load condition to set the status bit

Minimum duration of overcurrent condition to switch off the driver

30

500

10

-

40

150

30

150

200

200

-2

-15

110

-15

30

40

150

70

40

150

-

-

10

80

300

70

300

400

400

-5

0

180

0

80

60

300

150

60

300

3000

100

A

µs

µs

µs

µs

µs

µs

µA

µA

µA

µA mA mA mA mA mA mA

µs

µs

Doc ID 10311 Rev 11 13/39

Electrical specifications

Table 11.

OUT1 - OUT11 (continued)

Symbol Parameter dV

OUT16

/dt Slew rate of OUT1,OUT6 dV

OUT23

/dt, dV

OUT78910

/dt

Slew rate of OUT2/3 and

OUT7-OUT10 dV

OUT45

/dt Slew rate of OUT4, OUT5 dV

OUT11

/dt Slew rate of OUT11

Test condition

V

S

=13.5 V

I load

= ±1.5 A

V

S

= 13.5 V

I load

= -0.8 A

V

S

= 13.5 V

I load

= ±3.0 A

V

S

= 13.5 V

I load

= 3.0 A

2.6

Note:

L9950 - L9950XP

Min.

Typ.

Max.

Unit

0.1

0.2

0.4

V/µs

0.09

0.2

0.4

V/µs

0.1

0.2

0.4

V/µs

0.1

0.2

0.4

V/µs

SPI - electrical characteristics

V

S

= 8 to 16 V, V

CC

= 4.5 to 5.3 V, T j

= - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Table 12.

Delay time from standby to active mode

Symbol Parameter Test condition t set

Delay time

Switching from standby to active mode.

Time until output drivers are enabled after CSN going to high.

Min. Typ.

Max.

Unit

160 300 µs

Table 13.

Inputs: CSN, CLK, PWM1/2 and DI

Symbol Parameter Test condition Min. Typ.

Max.

Unit

I

V

I

CSN in

CLK in

I

V

V inL inH inHyst

DI in

I

PWM1 in

C in

Input low level

Input high level

Input hysteresis

Pull up current at input CSN

Pull down current at input CLK

Pull down current at input DI

V

CC

= 5 V

V

CC

= 5 V

1.5

-

V

CC

= 5 V 0.5

V

CSN

= 3.5 V V

CC

= 5 V -40

V

CLK

= 1.5 V

V

DI

= 1.5 V

10

10

Pull down current at input

PWM1

V

PWM

= 1.5 V 10

Input capacitance at input

CSN, CLK, DI and PWM1/2

V

CC

= 0 to 5.3 V -

2.0

3.0

-

-20

25

25

25

10

-

3.5

-

-8

50

50

50

15

µA pF

V

V

V

µA

µA

µA

Value of input capacity is not measured in production test. Parameter guaranteed by design.

14/39 Doc ID 10311 Rev 11

L9950 - L9950XP

Table 14.

DI timing

Symbol Parameter t t t t t

CLK

CLKH

CLKL set CSN set CLK

Clock period

Clock high time

Clock low time

CSN setup time, CSN low before rising edge of CLK

CLK setup time, CLK high before rising edge of CSN t set DI t hold time

DI setup time

DI hold time t t r in f in

Rise time of input signal DI,

CLK, CSN

Fall time of input signal DI,

CLK, CSN

Note:

Test condition

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

V

CC

= 5 V

Electrical specifications

400

200

200

-

-

Min. Typ.

Max.

Unit

1000

400

400 -

-

-

-

-

ns ns ns

400 ns

-

-

-

-

-

-

-

-

100

100 ns ns ns ns ns

DI timing parameters tested in production by a passed/failed test:

Tj=-40 °C/+25 °C: SPI communication @2 MHZ.

Tj=+125 °C: SPI communication @1.25 MHZ.

Table 15.

DO

Symbol Parameter

I

V

V

C

DOL

DOH

DOLK

DO

(1)

Output low level

Output high level

Tristate leakage current

Tristate input capacitance

Test condition

VCC = 5 V, I

D

= -2 mA

VCC = 5 V, I

D

= 2 mA

V

CSN

= V

CC

,

0 V < V

DO

< V

CC

V

CSN

= V

CC

,

0 V < V

CC

< 5.3 V

V

Min.

-

CC

-

-0.4

V

-10

Typ.

Max.

Unit

0.2

CC

-

-0.2

10

1.

Value of input capacity is not measured in production test. Parameter guaranteed by design.

0.4

-

10

15

V

V

µA pF

Doc ID 10311 Rev 11 15/39

Electrical specifications L9950 - L9950XP

Table 16.

DO timing

Symbol Parameter t t t t t r DO f DO en DO tri L dis DO L tri en DO tri H t dis DO H tri t d DO

Test condition

DO rise time

DO fall time

DO enable time from tristate to low level

DO disable time from low level to tristate

C

L

= 100 pF, I load

= -1 mA

C

L

= 100 pF, I load

= 1 mA

C

L

= 100 pF, I load

= 1 mA pull-up load to V

CC

C

L

= 100 pF, I load

= 4 mA pull-up load to V

CC

DO enable time from tristate to high level

C

L

=100 pF, I load

= -1 mA pull-down load to GND

DO disable time from high level to tristate

C

L

= 100 pF, I load

= -4 mA pull-down load to GND

DO delay time

V

DO

< 0.3 V

CC

, V

DO

> 0.7 V

CC

,

C

L

= 100 pF

Min.

Typ.

Max.

Unit

-

80

50

140

100 ns ns

-

-

-

-

100 250 ns

380 450 ns

100 250 ns

380 450 ns

50 250 ns

Table 17.

CSN timing

Symbol Parameter Test condition t

CSN_HI,stb

Minimum CSN HI time, switching from standby mode

Transfer of SPI command to Input Register t

CSN_HI,min

Maximum CSN HI time, active mode

Transfer of SPI command to input register

Min.

Typ.

Max.

Unit

-

20

2

50

4

µs

µs

Figure 3.

SPI - transfer timing diagram

CSN

CLK

DI

0 1 2 3 4 5 6

7

1 2 3

4 5

6 7

DO

Input

Data

Register

0 1 2 3 4 5 6 7

0 1

0 1

16/39 Doc ID 10311 Rev 11

L9950 - L9950XP

Figure 4.

SPI - input timing

CSN t set CSN

CLK

DI t

CLKH t set DI t hold DI t

CLKL

Valid Valid t set CLK

Electrical specifications

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

Figure 5.

SPI - DO valid data delay time and valid time t f in t r in

CLK t r DO

DO

(low to high) t d DO t f DO

DO

(high to low)

0.8 VCC

0.5 VCC

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

Doc ID 10311 Rev 11 17/39

Electrical specifications

Figure 6.

SPI - DO enable and disable time t f in

CSN t r in

L9950 - L9950XP

0.8 VCC

50%

0.2 VCC

DO pull-up load to VCC

C = 100 pF

50% t en DO tri L t dis DO L tri

DO pull-down load to GND t en DO tri H t dis DO H tri

Figure 7.

SPI - driver turn-on/off timing, minimum csn hi time

CSN low to high: data from shift register is transferred to output power switches t r in t

CSN_HI,min t f in

CSN t dOFF output current of a driver

ON state OFF state t dON t

OFF t

ON output current of a driver

OFF state ON state

50%

80%

50%

20%

80%

50%

20%

80%

50%

20%

18/39 Doc ID 10311 Rev 11

L9950 - L9950XP Electrical specifications

Figure 8.

SPI - timing of status bit 0 (fault condition)

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO

CSN

CLK time time

DI

DO time

DI: data is not accepted

0-

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low time

Doc ID 10311 Rev 11 19/39

Application information L9950 - L9950XP

3.1 Dual power supply: V

S

and V

CC

The power supply voltage V

S

supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage V

CC

5 V) is used for the logic part and the SPI of the device.

(stabilized

Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (V

CC

increases from under voltage to V

POR OFF

= 4.2 V) the circuit is initialized by an internally generated power on reset (POR). If the voltage V

CC

decreases under the minimum threshold (V

POR ON

= 3.4 V), the outputs are switched to tristate (high impedance) and the status registers are cleared.

The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data

Register 0. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at V

S

(V

CC

) is less than 6 µA (50 µA) for

CSN = high (DO in tristate). By switching the V

CC

voltage a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode.

Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external free wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive resistive loads. Hence only a limited energy

(E<1 mJ) can be dissipated by the internal ESD diodes in freewheeling condition. For inductive loads (L>100 µ H) an external free wheeling diode connected to GND and the corresponding output is needed.

All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open load: 1 ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the overload and thermal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bits in the Input Data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers.

20/39 Doc ID 10311 Rev 11

L9950 - L9950XP Application information

3.5 Overvoltage under voltage detection

If the power supply voltage V

S

rises above the overvoltage threshold V

SOV OFF

(typical

21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load.

When the voltage V

S

drops below the under voltage threshold V

SUV OFF

(UV switch OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage V

S

recovers to normal operating voltage the outputs stages return to the programmed state (input register 0: bit 20=0).

If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.

3.6 Temperature warning and thermal shutdown

If junction temperature rises above T j TW

a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold T j SD

, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below T j SD

- T j SD HYS

and the thermal shutdown bit has to be cleared by the microcontroller.

The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (t dOL

) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.

3.8 Over detection

In case of an over-current condition a flag is set in the status register in the same way as open load detection. If the over-current signal is valid for at least t

ISC

= 32 µs, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.

Doc ID 10311 Rev 11 21/39

Application information L9950 - L9950XP

The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits

18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5,

OUT6 and OUT11 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open or overload condition. For example this can be used to detect the motor state

(starting, free running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f.

PWM inputs).

Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit is set, the output is controlled by the logically AND combination of the PWM signal and the output control bit in Input Data Register. The outputs

OUT1-OUT8 and OUT11 are controlled by the PWM1 input and the outputs OUT9/10 are controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals.

3.11 Cross current protection

The six half brides of the device are cross current protected by an internal delay time. If one driver (LS or HS) is turned off the activation of the other driver of the same half bridge will be automatically delayed by the cross current protection time. After the cross current protection time is expired the slew rate limited switch off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned on with slew rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned off before the opposite driver will start to conduct.

3.12 Programmable soft start function to drive loads with higher inrush current

Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition.

The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first

50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits.

22/39 Doc ID 10311 Rev 11

L9950 - L9950XP Application information

Figure 9.

Example of programmable soft start function for inductive loads

Doc ID 10311 Rev 11 23/39

Functional description of the SPI

4 Functional description of the SPI

4.1

Note:

L9950 - L9950XP

Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and

CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin will reflect the status bit 0 (fault condition) of the device which is a logical or of all bits in the status registers

0 and 1. The microcontroller can poll the status of the device without the need of a full SPI communication cycle.

In contrast to the SPI standard the least significant bit (LSB) will be transferred first

(see Figure 3 ).

4.2

4.3

Note:

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN input pin is driven above

7.5V, the L9950 will go into a test mode. In the test mode the DO will go from tri state to active mode.

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.

At the rising edge of the CSN signal the contents of the shift register will be transferred to

Data Input Register. The writing to the selected Data Input Register is only enabled if exactly

24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

24/39 Doc ID 10311 Rev 11

L9950 - L9950XP

4.4

Functional description of the SPI

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

4.5

4.6

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.

Input data register

The device has two input registers. The first bit (bit 0) at the DI input is used to select one of the two Input Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data

Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver.

If bit 23 is zero, the device will go into the standby mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).

This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI communication cycle. If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.

Doc ID 10311 Rev 11 25/39

Functional description of the SPI L9950 - L9950XP

The test mode can be entered by rising the CSN input to a voltage higher than 7.0 V. In the test mode the inputs CLK, DI, PWM1/2 and the internal 2 MHz CLK can be multiplexed to data output DO for testing purpose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW and TSD thresholds.

The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched on at the same time. In the test mode this combination is used to multiplex the desired signals according to following table:

Table 18.

Test mode

LS1 HS1 LS2 HS2 LS3 HS3 DO LS3 HS3 LS4 HS4 LS5 HS5 Test pad

! (both HI) ! (both HI) ! (both HI) No error ! (both HI) ! (both HI) ! (both HI) both HI ! (both HI) ! (both HI) DI both HI ! (both HI) ! (both HI)

! (both HI) both HI ! (both HI) both HI both HI ! (both HI)

CLK

INT_CLK

! (both HI) both HI both HI both HI

! (both HI)

! (both HI)

! (both HI) ! (both HI) both HI both HI ! (both HI) both HI

PWM1

PWM2

! (both HI) ! (both HI) both HI both HI ! (both HI) both HI

! (both HI) both HI both HI both HI both HI both HI

5µA Iref

Tsens1

Tsens2

Tsens3

Tsens4

Tsens5

Tsens6

Vbandgap

26/39 Doc ID 10311 Rev 11

L9950 - L9950XP Functional description of the SPI

Table 19.

SPI - input data and status registers 0

Input register 0 (write)

Bit

Name Comment Name

Status register 0 (read)

Comment

23

22

21

20

Enable bit

If Enable Bit is set the device will be switched in active mode. If Enable Bit is cleared device go into standby mode and all bits are cleared. After poweron reset device starts in standby mode.

Always 1

A broken VCC or SPI connection of the L9950 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame.

Reset bit

OC recovery duty cycle

0: 12%

1:

25%

Overvoltage/Un dervoltage recovery disable

If Reset Bit is set both status registers will be cleared after rising edge of CSN input.

This bit defines in combination with the overcurrent recovery bit (Input

Register 1) the duty cycle in over-current condition of an activated driver.

V

S

overvoltage

V

S

undervoltage

In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If

VS voltage recovers to normal operating conditions outputs are reactivated automatically

(if Bit 20 of status register 0 is not set).

If this bit is set the microcontroller has to clear the status register after undervoltage/overvoltage event to enable the outputs.

Thermal shutdown

In case of an thermal shutdown all outputs are switched off.

The microcontroller has to clear the TSD bit by setting the

Reset Bit to reactivate the outputs.

19

18

Depending on combination of bit 18 and

19 the current image

(1/10.000) of the selected

HS output will be multiplexed to the CM output:

Bit

19

0

Bit

18

0

Output

OUT11

Current monitor select bits

1

0

0

1

OUT1/OUT

6

OUT5

1 1 OUT4

HS driver of OUT1 is only selected if HS driver

OUT1 is switched on and

HS driver OUT6 is not activated.

Temperature warning

Not ready bit

This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown.

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events

(e.g. measuring filter times).

Doc ID 10311 Rev 11 27/39

Functional description of the SPI L9950 - L9950XP

Table 19.

SPI - input data and status registers 0 (continued)

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name Comment

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

OUT11 – HS on/off

OUT10 – HS on/off

OUT9 – HS on/off

OUT8 – HS on/off

OUT7 – HS on/off

OUT6 – HS on/off

OUT6 – LS on/off

OUT5 – HS on/off

OUT5 – LS on/off

OUT4 – HS on/off

OUT4 – LS on/off

OUT3 – HS on/off

OUT3 – LS on/off

OUT2 – HS on/off

OUT2 – LS on/off

OUT1 – HS on/off

OUT1 – LS on/off

If a bit is set the selected output driver is switched on. If the corresponding

PWM enable bit is set

(Input Register 1) the driver is only activated if

PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of HS- and LS driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND.

In test mode (CSN>7.5 V) this bit combinations are used to multiplex internal signals to the DO output.

0

OUT11 – HS over-current

OUT10 – HS over-current

OUT9 – HS over-current

OUT8 – HS over-current

OUT7 – HS over-current

OUT6 – HS over-current

OUT6 – LS over-current

OUT5 – HS over-current

OUT5 – LS over-current

OUT4 – HS over-current

OUT4 – LS over-current

OUT3 – HS over-current

OUT3 – LS over-current

OUT2 – HS over-current

OUT2 – LS over-current

OUT1 – HS over-current

OUT1 – LS over-current

In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the overcurrent Recovery Enable bit is set (Input Register 1) the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21).

If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (Reset Bit) to reactivate the output driver.

No error bit

A logical NOR combination of all bits 1 to 22 in both status registers.

28/39 Doc ID 10311 Rev 11

L9950 - L9950XP Functional description of the SPI

Table 20.

SPI - input data and status registers 1

Input register 1 (write)

Bit

Name Comment

Status register 1 (read)

Name Comment

23

22

21

20

19

18

Enable bit

OUT11 OC

Recovery

Enable

OUT10 OC

Recovery

Enable

OUT9 OC

Recovery

Enable

OUT8 OC

Recovery

Enable

OUT7 OC

Recovery enable

If Enable bit is set the device will be switched in active mode.

If Enable Bit is cleared device go into standby mode and all bits are cleared. After poweron reset device starts in standby mode.

Always 1

A broken VCC or SPI connection of the L9950 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame.

VS overvoltage

VS undervoltage

In case of an over-current event the over-current status bit (Status Register 0) is set and the output is switched off.

If the over-current Recovery

Enable bit is set the output will be automatically reactivated after a delay time resulting in a

PWM modulated current with a programmable duty cycle (Bit

21 of Input Data Register 0).

Depending on occurrence of

Overcurrent Event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.

Thermal shutdown

Temperature warning

Not ready bit

In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If VS voltage recovers to normal operating conditions outputs are reactivated automatically.

In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs.

This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown.

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times).

Doc ID 10311 Rev 11 29/39

Functional description of the SPI L9950 - L9950XP

Table 20.

SPI - input data and status registers 1 (continued)

Input register 1 (write) Status register 1 (read)

Bit

Name Comment Name Comment

17

16

15

14

13

12

11

OUT6 OC

Recovery

Enable

OUT5 OC

Recovery

Enable

OUT4 OC

Recovery

Enable

OUT3 OC

Recovery

Enable

OUT2 OC

Recovery

Enable

OUT1 OC

Recovery

Enable

OUT11 PWM1

Enable

After 50 ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed.

10

OUT10 PWM2

Enable

9

8

7

6

5

4

OUT9 PWM2

Enable

OUT8 PWM1

Enable

OUT7 PWM1

Enable

OUT6 PWM1

Enable

OUT4 PWM1

Enable

OUT4 PWM1

Enable

If the PWM1/2 Enable Bit is set and the output is enabled

(Input Register 0) the output is switched on if PWM1/2 input is high and switched off if

PWM1/2 input is low. OUT9 and OUT10 is controlled by

PWM2 input all other outputs are controlled by PWM1 input.

3

2

1

OUT3 PWM1

Enable

OUT4 PWM1

Enable

OUT4 PWM1

Enable

OUT11 – HS open load

OUT10 – HS open load

OUT9 – HS open load

OUT8 – HS open load

OUT7 – HS open load

OUT6 – HS open load

OUT6 – LS open load

OUT5 – HS open load

OUT5 – LS open load

OUT4 – HS open load

OUT4 – LS open load

OUT3 – HS open load

OUT3 – LS open load

OUT2 –HS open load

OUT2– LS open load

OUT1 – HS open load

OUT1 – LS open load

The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (t dOL

) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.

The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (t dOL

) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.

0 1 No Error bit

A logical NOR combination of all bits 1 to 22 in both status registers.

30/39 Doc ID 10311 Rev 11

L9950 - L9950XP

5 Packages thermal data

Figure 10.

Packages thermal data

Packages thermal data

Doc ID 10311 Rev 11 31/39

Package and packing information

6 Package and packing information

L9950 - L9950XP

6.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

6.2

PowerSO-36

package information

Figure 11.

PowerSO-36 package dimensions

32/39 Doc ID 10311 Rev 11

L9950 - L9950XP e e3

G

H h

L

M

N

R s

E

E1 *

E2

E3 b c

D *

D1

A a1 a2 a3

Table 21.

PowerSO-36 mechanical data

Symbol

Min.

-

-

0

15.50

-

0.8

-

-

-

-

13.90

10.90

-

5.80

0.22

0.23

15.80

9.40

-

0.10

-

0

Package and packing information

Millimeters

Typ.

0.65

11.05

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Max.

14.5

11.10

2.90

6.20

-

-

0.10

15.90

1.10

1.10

-

10 deg

-

8 deg

0.38

0.32

16.00

9.80

3.60

0.30

3.30

0.10

Doc ID 10311 Rev 11 33/39

Package and packing information

6.3

PowerSSO-36

package information

Figure 12.

PowerSSO-36 package dimensions

L9950 - L9950XP

34/39

A

A2 a1 b c

D

(1)

E e e3

F

G

G1

H h k

Table 22.

PowerSSO-36 mechanical data

Symbol

7.4

-

-

-

-

-

Min.

2.15

2.15

0

0.18

0.23

10.10

10.1

-

0°

Millimeters

Typ.

-

-

-

-

-

-

-

0.5

8.5

2.3

-

-

-

-

-

Doc ID 10311 Rev 11

7.6

-

-

-

0.1

0.06

Max.

2.45

2.35

0.10

0.36

0.32

10.50

10.5

0.4

8°

L9950 - L9950XP Package and packing information

Table 22.

PowerSSO-36 mechanical data (continued)

Millimeters

Symbol

Min.

Typ.

L

Q

S

T

M

N

O

U

X

Y

0.55

-

-

-

-

-

-

-

4.3

6.9

-

4.3

-

1.2

0.8

2.9

3.65

1

-

-

-

5.2

7.5

-

-

-

Max.

0.85

-

10°

-

1.

“D” and “E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm per side (0.006”).

6.4

PowerSO-36

packing information

Figure 13.

PowerSO-36 tube shipment (no suffix)

Doc ID 10311 Rev 11 35/39

Package and packing information

Figure 14.

PowerSO-36 tape and reel shipment (suffix “TR”)

L9950 - L9950XP

TAPE DIMENSIONS

A0

B0

K0

K1

F

P1

W

15.20 ± 0.1

16.60 ± 0.1

3.90 ± 0.1

3.50 ± 0.1

11.50 ± 0.1

24.00 ± 0.1

24.00 ± 0.3

All dimensions are in mm.

REEL DIMENSIONS

Base qty

Bulk qty

A (max)

B (min)

C (±0.2)

D (min)

G (+2 / -0)

N (min)

T (max)

600

600

330

1.5

13

20.2

24.4

60

30.4

36/39 Doc ID 10311 Rev 11

L9950 - L9950XP

6.5

PowerSSO-36

packing information

Figure 15.

PowerSSO-36 tube shipment (no suffix)

Package and packing information

C

B

Base qty

Bulk qty

Tube length (±0.5)

A

B

C (±0.1)

All dimensions are in mm.

49

1225

532

3.5

13.8

0.6

A

Figure 16.

PowerSSO-36 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base qty

Bulk qty

A (max)

B (min)

C (±0.2)

F

G (+2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape hole spacing

Component spacing

Hole diameter

Hole diameter

Hole position

Compartment depth

Hole spacing

W

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

24

4

P 12

D (±0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

No components Components

500mm min 500mm min

Empty components pockets sealed with cover tape.

Start

No components

User direction of feed

Doc ID 10311 Rev 11 37/39

Revision history L9950 - L9950XP

Table 23.

Document revision history

Date Revision

Apr-2004 1

Jun-2004

Jul-2004

Jun-2005

Jul-2005

Sep-2005

14-Nov-2007

05-Nov-2008

30-Mar-2009

09-Jun-2009

19-Sep-2013

2

3

4

5

6

7

8

9

10

11

Description of changes

First Issue

Changed maturity from product preview to final;

Changed values in the Table 4: ESD protection

Minor changes

PowerSSO-36 package insertion

Figure 1 modification

Features modification;

Table 7

modification (I

CC

; I

S

+ I

CC

);

Figure 10

modification;

I

QLL

modification.

Document restructured and reformatted.

Added PowerSO-36 packing information and

PowerSSO-36 packing information

.

Updated Table 22: PowerSSO-36 mechanical data

.

Changed Section : Application on cover page

Changed

Section 6.1: ECOPACK

®

Table 22: PowerSSO-36 mechanical data :

– Changed A (max) value from 2.50 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Changed L (max) value from 0.90 to 0.85

Updated Disclaimer.

38/39 Doc ID 10311 Rev 11

L9950 - L9950XP

Please Read Carefully:

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Doc ID 10311 Rev 11 39/39