Register map. STMicroelectronics STM8L051F3

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STM8L051F3 Memory and register map address.

2. Refer to Table 7

for an overview of hardware register mapping, to Table 6

for details on I/O port hardware registers, and to

Table 8 for information on CPU/SWIM/debug module controller registers.

Memory area

Table 5. Flash and RAM boundary addresses

Size Start address End address

RAM

Flash program memory

1 Kbyte

8 Kbytes

0x00 0000

0x00 8000

0x00 03FF

0x00 9FFF

Address

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

0x00 5014 to

0x00 501D

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

Block

Port A

Port B

Port C

Port D

Table 6. I/O port hardware register map

Register label Register name

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Reserved area (0 bytes)

Reset status

0xXX

0x00

0xXX

0x00

0xXX

0x00

0x01

0x00

0xXX

0x00

DS9178 Rev 4 27/96

Address

0x00 502E to

0x00 5049

0x00 5050

0x00 5051

0x00 5052

0x00 5053

0x00 5054

0x00 5055 to

0x00 506F

0x00 5070

0x00 5071

0x00 5072 to

0x00 5074

0x00 5075

0x00 5076

0x00 5077

0x00 5078

0x00 5079

0x00 507A

0x00 507B

0x00 507C

Block

Flash

DMA1

Memory and register map STM8L051F3

Table 7. General hardware register map

Register label Register name

Reset status

FLASH_CR1

FLASH_CR2

FLASH _PUKR

FLASH _DUKR

FLASH _IAPSR

Reserved area (44 bytes)

Flash control register 1

Flash control register 2

Flash program memory unprotection key register

Data EEPROM unprotection key register

Flash in-application programming status register

0x00

DMA1_GCSR

DMA1_GIR1

Reserved area (3 bytes)

DMA1_C0CR

DMA1_C0SPR

DMA1_C0NDTR

DMA1_C0PARH

DMA1_C0PARL

DMA1_C0M0ARH

DMA1_C0M0ARL

Reserved area (27 bytes)

DMA1 global configuration & status register

DMA1 global interrupt register 1

DMA1 channel 0 configuration register

DMA1 channel 0 status & priority register

DMA1 number of data to transfer register

(channel 0)

DMA1 peripheral address high register

(channel 0)

DMA1 peripheral address low register

(channel 0)

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 0)

DMA1 memory 0 address low register

(channel 0)

0xFC

0x00

0x52

0x00

28/96 DS9178 Rev 4

STM8L051F3 Memory and register map

Block

Table 7. General hardware register map (continued)

Register label Register name

0x00 508D

0x00 508E

0x00 508F

0x00 5090

0x00 5091

0x00 5092

0x00 5093

0x00 5094

0x00 5095

0x00 5096

0x00 5097

Address

0x00 507D to

0x00 507E

0x00 507F

0x00 5080

0x00 5081

0x00 5082

0x00 5083

0x00 5084

0x00 5085

0x00 5086

0x00 5087

0x00 5088

0x00 5089

0x00 508A

0x00 508B

0x00 508C

DMA1

DMA1_C1CR

DMA1_C1SPR

DMA1_C1NDTR

DMA1_C1PARH

DMA1_C1PARL

DMA1_C1M0ARH

DMA1_C1M0ARL

DMA1_C2CR

DMA1_C2SPR

DMA1_C2NDTR

DMA1_C2PARH

DMA1_C2PARL

DMA1_C2M0ARH

DMA1_C2M0ARL

DMA1_C3CR

DMA1_C3SPR

DMA1_C3NDTR

DMA1_C3PARH_

C3M1ARH

DMA1_C3PARL_

C3M1ARL

Reserved area (2 bytes)

DMA1 channel 1 configuration register

DMA1 channel 1 status & priority register

DMA1 number of data to transfer register

(channel 1)

DMA1 peripheral address high register

(channel 1)

DMA1 peripheral address low register

(channel 1)

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 1)

DMA1 memory 0 address low register

(channel 1)

Reserved area (2 bytes)

DMA1 channel 2 configuration register

DMA1 channel 2 status & priority register

DMA1 number of data to transfer register

(channel 2)

DMA1 peripheral address high register

(channel 2)

DMA1 peripheral address low register

(channel 2)

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 2)

DMA1 memory 0 address low register

(channel 2)

Reserved area (2 bytes)

DMA1 channel 3 configuration register

DMA1 channel 3 status & priority register

DMA1 number of data to transfer register

(channel 3)

DMA1 peripheral address high register

(channel 3)

DMA1 peripheral address low register

(channel 3)

Reset status

0x00

0x40

0x00

0x52

0x00

0x52

0x00

DS9178 Rev 4 29/96

Memory and register map STM8L051F3

Address

0x00 5098

0x00 5099

DMA1

0x00 509A

0x00 50A6

0x00 50A7

0x00 50A8

0x00 50A9

0x00 50AA

0x00 50AB

0x00 50A9 to

0x00 50AF

0x00 50B0

0x00 50B1

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 509B to

0x00 509C

0x00 509D

0x00 509E

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2

0x00 50A3

0x00 50A4

0x00 50A5

SYSCFG

ITC - EXTI

WFE

ITC - EXTI

RST

PWR

CLK

Block

Table 7. General hardware register map (continued)

Register label Register name

DMA_C3M0EAR

DMA1_C3M0ARH

DMA1_C3M0ARL

SYSCFG_RMPCR3

SYSCFG_RMPCR1

SYSCFG_RMPCR2

EXTI_CR1

EXTI_CR2

EXTI_CR3

EXTI_SR1

EXTI_SR2

EXTI_CONF1

WFE_CR1

WFE_CR2

WFE_CR3

WFE_CR4

EXTI_CR4

EXTI_CONF2

DMA channel 3 memory 0 extended address register

DMA1 memory 0 address high register

(channel 3)

DMA1 memory 0 address low register

(channel 3)

Reserved area (3 bytes)

Remapping register 3

Remapping register 1

Remapping register 2

External interrupt control register 1

External interrupt control register 2

External interrupt control register 3

External interrupt status register 1

External interrupt status register 2

External interrupt port select register 1

WFE control register 1

WFE control register 2

WFE control register 3

WFE control register 4

External interrupt control register 4

External interrupt port select register 2

RST_CR

RST_SR

PWR_CSR1

PWR_CSR2

CLK_CKDIVR

CLK_CRTCR

CLK_ICKCR

CLK_PCKENR1

Reserved area (7 bytes)

Reset control register

Reset status register

Power control and status register 1

Power control and status register 2

Reserved area (12 bytes)

CLK Clock master divider register

CLK Clock RTC register

CLK Internal clock control register

CLK Peripheral clock gating register 1

Reset status

0x00

0x01

0x00

0x03

0x00

(1)

0x11

0x00

30/96 DS9178 Rev 4

STM8L051F3 Memory and register map

Address

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

0x00 50CD

0x00 50CE

0x00 50CF

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 50F2

0x00 50F3

0x00 50F4 to0x00 513F

0x00 5140

0x00 5141

0x00 5142

0x00 50D0

0x00 50D1 to

0x00 50D2

0x00 50D3

0x00 50D4

0x00 50D5 to

00 50DF

0x00 50E0

0x00 50E1

0x00 50E2

Block

Table 7. General hardware register map (continued)

Register label Register name

CLK

CLK_PCKENR2

CLK_CCOR

CLK_ECKCR

CLK_SCSR

CLK_SWR

CLK_SWCR

CLK_CSSR

CLK_CBEEPR

CLK_HSICALR

CLK_HSITRIMR

CLK_HSIUNLCKR

CLK_REGCSR

CLK_PCKENR3

CLK Peripheral clock gating register 2

CLK Configurable clock control register

CLK External clock control register

CLK System clock status register

CLK System clock switch register

CLK Clock switch control register

CLK Clock security system register

CLK Clock BEEP register

CLK HSI calibration register

CLK HSI clock calibration trimming register

CLK HSI unlock register

CLK Main regulator control status register

CLK Peripheral clock gating register 3

Reset status

0x00

0xXX

0x00

0bxx11 1

00X

0x00

0x01

0xX0

0x00

WWDG

WWDG_CR

WWDG_WR

Reserved area (2 bytes)

WWDG control register

WWDR window register

0x7F

IWDG

BEEP

RTC

IWDG_KR

IWDG_PR

IWDG_RLR

Reserved area (11 bytes)

IWDG key register

IWDG prescaler register

IWDG reload register

Reserved area (13 bytes)

BEEP_CSR1

BEEP_CSR2

RTC_TR1

RTC_TR2

RTC_TR3

BEEP control/status register 1

Reserved area (2 bytes)

BEEP control/status register 2

Reserved area (76 bytes)

RTC Time register 1

RTC Time register 2

RTC Time register 3

0x01

0x00

0xFF

0x00

0x1F

0x00

DS9178 Rev 4 31/96

Address

0x00 5143

0x00 5144

0x00 5145

0x00 5146

0x00 5147

0x00 5148

0x00 5149

0x00 514A

0x00 514B

0x00 514C

0x00 514D

0x00 514E

0x00 514F

0x00 5150

0x00 5151

0x00 5152

0x00 5153

0x00 5154

0x00 5155

0x00 5156

0x00 5157

0x00 5158

0x00 5159

0x00 5158

0x00 5159

0x00 515A

0x00 515B

0x00 515C

0x00 515D

0x00 515E

0x00 515F

0x00 5160 to

0x00 5163

0x00 5164

0x00 5165

Memory and register map

Block

Table 7. General hardware register map (continued)

Register label Register name

RTC

RTC_DR1

RTC_DR2

RTC_DR3

RTC_CR1

RTC_CR2

RTC_CR3

RTC_ISR1

RTC_ISR2

RTC_SPRERH

RTC_SPRERL

RTC_APRER

RTC_WUTRH

RTC_WUTRL

RTC_SSRL

RTC_SSRH

RTC_WPR

RTC_SSRH

RTC_WPR

RTC_SHIFTRH

RTC_SHIFTRL

RTC_ALRMAR1

RTC_ALRMAR2

RTC_ALRMAR3

RTC_ALRMAR4

RTC_ALRMASSRH

RTC_ALRMASSRL

Reserved area (1 byte)

RTC Date register 1

RTC Date register 2

RTC Date register 3

Reserved area (1 byte)

RTC Control register 1

RTC Control register 2

RTC Control register 3

Reserved area (1 byte)

RTC Initialization and status register 1

RTC Initialization and Status register 2

Reserved area (2 bytes)

RTC Synchronous prescaler register high

RTC Synchronous prescaler register low

RTC Asynchronous prescaler register

Reserved area (1 byte)

RTC Wakeup timer register high

RTC Wakeup timer register low

Reserved area (1 byte)

RTC Subsecond register low

RTC Subsecond register high

RTC Write protection register

RTC Subsecond register high

RTC Write protection register

RTC Shift register high

RTC Shift register low

RTC Alarm A register 1

RTC Alarm A register 2

RTC Alarm A register 3

RTC Alarm A register 4

Reserved area (4 bytes)

RTC Alarm A subsecond register high

RTC Alarm A subsecond register low

STM8L051F3

Reset status

0x01

0x21

0x00

0x01

0x00

(1)

0x7F

0xFF

0x00

32/96 DS9178 Rev 4

STM8L051F3 Memory and register map

Address

0x00 5166

0x00 5167 to

0x00 5169

0x00 516A

0x00 516B

0x00 516C

0x00 516D

0x00 516E to

0x00 518A

0x00 5190

0x00 519A to

0x00 51FF

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

Block

Table 7. General hardware register map (continued)

Register label Register name

RTC

SPI1

RTC_ALRMASSMSKR

RTC_CALRH

RTC_CALRL

RTC_TCR1

RTC_TCR2

RTC Alarm A masking register

Reserved area (3 bytes)

RTC Calibration register high

RTC Calibration register low

RTC Tamper control register 1

RTC Tamper control register 2

CSSLSE_CSR

Reserved area (36 bytes)

CSS on LSE control and status register

SPI1_CR1

SPI1_CR2

SPI1_ICR

SPI1_SR

SPI1_DR

SPI1_CRCPR

SPI1_RXCRCR

SPI1_TXCRCR

Reserved area (111 bytes)

SPI1 control register 1

SPI1 control register 2

SPI1 interrupt control register

SPI1 status register

SPI1 data register

SPI1 CRC polynomial register

SPI1 Rx CRC register

SPI1 Tx CRC register

I2C1

I2C1_CR1

I2C1_CR2

I2C1_FREQR

I2C1_OARL

I2C1_OARH

I2C1_OAR2

I2C1_DR

I2C1_SR1

I2C1_SR2

I2C1_SR3

I2C1_ITR

I2C1_CCRL

I2C1_CCRH

Reserved area (8 bytes)

I2C1 control register 1

I2C1 control register 2

I2C1 frequency register

I2C1 own address register low

I2C1 own address register high

I2C1 own address register for dual mode

I2C1 data register

I2C1 status register 1

I2C1 status register 2

I2C1 status register 3

I2C1 interrupt control register

I2C1 clock control register low

I2C1 clock control register high

Reset status

0x00

0x02

0x00

0x07

0x00

0x0X

0x00

DS9178 Rev 4 33/96

Memory and register map

Address

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 521D

0x00 521E

0x00 521F to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

0x00 523B to

0x00 524F

0x00 5250

Block

Table 7. General hardware register map (continued)

Register label Register name

I2C1

I2C1_TRISER

I2C1_PECR

I2C1 TRISE register

I2C1 packet error checking register

USART1

TIM2

TIM2_CR1

TIM2_CR2

TIM2_SMCR

TIM2_ETR

TIM2_DER

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2_EGR

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCER1

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

USART1_SR

USART1_DR

USART1_BRR1

USART1_BRR2

USART1_CR1

USART1_CR2

USART1_CR3

USART1_CR4

USART1_CR5

USART1_GTR

USART1_PSCR

Reserved area (17 bytes)

USART1 status register

USART1 data register

USART1 baud rate register 1

USART1 baud rate register 2

USART1 control register 1

USART1 control register 2

USART1 control register 3

USART1 control register 4

USART1 control register 5

USART1 guard time register

USART1 prescaler register

Reserved area (21 bytes)

TIM2 control register 1

TIM2 control register 2

TIM2 Slave mode control register

TIM2 external trigger register

TIM2 DMA1 request enable register

TIM2 interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare enable register 1

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

STM8L051F3

Reset status

0x02

0x00

0xC0

0xXX

0x00

0xFF

34/96 DS9178 Rev 4

Address

0x00 5288

0x00 5289

0x00 528A

0x00 528B

0x00 528C

0x00 528D

0x00 528E

0x00 528F

0x00 5290

0x00 5291

0x00 5292

0x00 5293

0x00 5294

0x00 5295

0x00 5296

0x00 5297 to

0x00 52DF

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

0x00 5267 to

0x00 527F

0x00 5280

0x00 5281

0x00 5282

0x00 5283

0x00 5284

0x00 5285

0x00 5286

0x00 5287

STM8L051F3 Memory and register map

Block

Table 7. General hardware register map (continued)

Register label Register name

TIM2

TIM3

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_BKR

TIM2_OISR

TIM3_CR1

TIM3_CR2

TIM3_SMCR

TIM3_ETR

TIM3_DER

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3_EGR

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3_BKR

TIM3_OISR

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 break register

TIM2 output idle state register

Reserved area (25 bytes)

TIM3 control register 1

TIM3 control register 2

TIM3 Slave mode control register

TIM3 external trigger register

TIM3 DMA1 request enable register

TIM3 interrupt enable register

TIM3 status register 1

TIM3 status register 2

TIM3 event generation register

TIM3 Capture/Compare mode register 1

TIM3 Capture/Compare mode register 2

TIM3 Capture/Compare enable register 1

TIM3 counter high

TIM3 counter low

TIM3 prescaler register

TIM3 Auto-reload register high

TIM3 Auto-reload register low

TIM3 Capture/Compare register 1 high

TIM3 Capture/Compare register 1 low

TIM3 Capture/Compare register 2 high

TIM3 Capture/Compare register 2 low

TIM3 break register

TIM3 output idle state register

Reserved area (72 bytes)

0x00

0xFF

0x00

Reset status

0xFF

0x00

DS9178 Rev 4 35/96

Address

0x00 52FF

0x00 5317 to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5349

0x00 534A

0x00 534B

0x00 52E0

0x00 52E1

0x00 52E2

0x00 52E3

0x00 52E4

0x00 52E5

0x00 52E6

0x00 52E7

0x00 52E8

0x00 52E9

0x00 52EA to

0x00 52FE

0x00 534C

0x00 534D

0x00 534E

0x00 534F

0x00 5350

0x00 5351

Memory and register map

Block

Table 7. General hardware register map (continued)

Register label Register name

TIM4

TIM4_CR1

TIM4_CR2

TIM4_SMCR

TIM4_DER

TIM4_IER

TIM4_SR1

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 control register 1

TIM4 control register 2

TIM4 Slave mode control register

TIM4 DMA1 request enable register

TIM4 Interrupt enable register

TIM4 status register 1

TIM4 Event generation register

TIM4 counter

TIM4 prescaler register

TIM4 Auto-reload register

IRTIM

ADC1

IR_CR

Reserved area (21 bytes)

Infrared control register

ADC1_CR1

ADC1_CR2

ADC1_CR3

ADC1_SR

ADC1_DRH

ADC1_DRL

ADC1_HTRH

ADC1_HTRL

ADC1_LTRH

ADC1_LTRL

ADC1_SQR1

ADC1_SQR2

ADC1_SQR3

ADC1_SQR4

ADC1_TRIGR1

ADC1_TRIGR2

ADC1_TRIGR3

ADC1_TRIGR4

Reserved area (41 bytes)

ADC1 configuration register 1

ADC1 configuration register 2

ADC1 configuration register 3

ADC1 status register

ADC1 data register high

ADC1 data register low

ADC1 high threshold register high

ADC1 high threshold register low

ADC1 low threshold register high

ADC1 low threshold register low

ADC1 channel sequence 1 register

ADC1 channel sequence 2 register

ADC1 channel sequence 3 register

ADC1 channel sequence 4 register

ADC1 trigger disable 1

ADC1 trigger disable 2

ADC1 trigger disable 3

ADC1 trigger disable 4

STM8L051F3

0x00

0x0F

0xFF

0x00

0x1F

0x00

Reset status

0x00

36/96 DS9178 Rev 4

STM8L051F3 Memory and register map

Block

Table 7. General hardware register map (continued)

Register label Register name Address

0x00 53C8 to

0x00 542F

0x00 5430

0x00 5433

0x00 5434

0x00 5435

0x00 5436

0x00 5437

0x00 5438

0x00 5439

0x00 543A

0x00 543B

0x00 543C

0x00 543D

0x00 543E

0x00 543F

0x00 5440 to

0x00 544F

0x00 5450

0x00 5451

0x00 5452

0x00 5453

0x00 5454

0x00 5455

RI_IOIR1

RI_IOIR2

RI_IOIR3

RI_IOCMR1

RI_IOCMR2

RI_IOCMR3

RI_IOSR1

RI_IOSR2

RI_IOSR3

RI_IOGCR

RI_ASCR1

RI_ASCR2

RI_RCR

RI_CR

RI_MASKR1

RI_MASKR2

RI_MASKR3

RI_MASKR4

RI_IOIR4

Reserved area(104 bytes)

Reserved area (1 byte)

RI I/O input register 1

RI I/O input register 2

RI I/O input register 3

RI I/O control mode register 1

RI I/O control mode register 2

RI I/O control mode register 3

RI I/O switch register 1

RI I/O switch register 2

RI I/O switch register 3

RI I/O group control register

Analog switch register 1

RI Analog switch register 2

RI Resistor control register

Reserved area (16 bytes)

RI I/O control register

RI I/O mask register 1

RI I/O mask register 2

RI I/O mask register 3

RI I/O mask register 4

RI I/O input register 4

0x00 5456

0x00 5457

RI_IOCMR4

RI_IOSR4

RI I/O control mode register 4

RI I/O switch register 4

1. These registers are not impacted by a system reset. They are reset at power-on.

Reset status

0x00

0xXX

0x00

0xFF

0x00

0xXX

0x00

DS9178 Rev 4 37/96

Memory and register map

Address

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

Table 8. CPU/SWIM/debug module/interrupt controller registers

Block Register label Register name

CPU

(1)

CPU

ITC-SPR

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

PCE

PCH

PCL

SPH

SPL

CCR

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 bytes)

Global configuration register

Interrupt Software priority register 1

Interrupt Software priority register 2

Interrupt Software priority register 3

Interrupt Software priority register 4

Interrupt Software priority register 5

Interrupt Software priority register 6

Interrupt Software priority register 7

Interrupt Software priority register 8

SWIM

SWIM_CSR

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM Debug module control register 1

STM8L051F3

0x00

0xFF

0x00

0xFF

Reset status

0x00

0x03

0xFF

0x28

38/96 DS9178 Rev 4

STM8L051F3 Memory and register map

Address

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Block Register label Register name

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

0x00 7F9B to

0x00 7F9F

1. Accessible by debug module only

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

DM Debug module control register 2

DM Debug module control/status register 1

DM Debug module control/status register 2

DM enable function register

Reserved area (5 bytes)

Reset status

0x00

0x10

0x00

0xFF

DS9178 Rev 4 39/96

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