LPS22HB Mechanical and electrical specifications
3.3.2 I
2
C - inter-IC control interface
Subject to general operating conditions for Vdd and T
OP
.
Symbol Parameter (1)
Table 7. I 2 C slave timing values
I²C standard mode
(1)
Min Max f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
0
4.7
4.0
250
0
4
100
3.45
t su(SR)
Repeated START condition setup time
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1. Data based on standard I
2
C protocol requirement, not tested in production.
Figure 5. I 2 C slave timing diagram
Min
0
1.3
0.6
100
0
0.6
I²C fast mode
(1)
Max
400
0.9
0.6
0.6
1.3
μ s
Unit kHz
μ s ns
μ s
5(3($7('
67$57
67$57
6'$
W
VX65
W
Z6365
67$57
W
VX6'$
W
K6'$
W
VX63
6723
6&/
Note:
W
K67
W
Z6&//
W
Z6&/+
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
DocID027083 Rev 6 13/49
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