STMicroelectronics STA518 Datasheet
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STA518
40 V, 3.5 A quad power half-bridge
Datasheet
-
production data
PowerSSO36 with exposed pad (or slug) up
Description
The STA518 is a monolithic quad half-bridge stage in multipower BCD technology. The device can be used also as dual bridge or reconfigured, by connecting the CONFIG pin to the V dd
pin, as a single bridge with double current capacity.
The device is particularly designed to make the output stage of a stereo all-digital high-efficiency
(DDX™) amplifier capable of delivering an output power of 24 W x 4 channels @ THD = 10% at
V
CC
30 V into a 4 configuration.
load in single-ended
It can also deliver 50 + 50 W @ THD = 10% at
V
CC
29 V as output power into an 8 load in BTL configuration and 70 W @ THD = 10% at V
34 V into 8 in a single paralleled BTL
CC configuration.
The input pins have a threshold proportional to the V
L
pin voltage .
Features
Multipower BCD technology
Minimum input output pulse width distortion
200 m R dsON stage
complementary DMOS output
CMOS-compatible logic inputs
Thermal protection
Thermal warning output
Undervoltage protection
Short-circuit protection
Order code
STA51813TR
Table 1. Device summary
Temperature range °C Package
-40 to 90 PowerSSO36 (slug up)
Packaging
Tape & reel
September 2014
This is information on a product in full production.
DocID010708 Rev 6 1/21 www.st.com
Contents
Contents
STA518
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic interface and decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Parallel output / high current operation . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/21 DocID010708 Rev 6
STA518
List of tables
List of tables
, V
HIGH
variation with I
bias
Figure 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DocID010708 Rev 6 3/21
21
List of figures
List of figures
STA518
STA518 block diagralm full-bridge DDX
or binary modes . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical stereo full-bridge configuration to obtain 50 + 50 W @ THD = 10%, R
= 8 ,
V
CC
= 29 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical single BTL configuration to obtain 70 W @ THD 10%, R
= 8 , V
CC
= 34 V . . . 14
4/21 DocID010708 Rev 6
STA518
1 Audio application circuit
Audio application circuit
Figure 1. Audio application circuit (quad single-ended)
DocID010708 Rev 6 5/21
21
Pin description
6/21
Pin n°
10, 11
12
13
14
15
16, 17
18
1
2, 3
4
5
6
7
8, 9
Figure 2. Pin connections (top view)
V
CC
Sign
V
CC
Sign
V
SS
V
SS
IN2B
IN2A
IN1B
IN1A
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
V
L
VDD
VDD
GND-Reg
GND-Clean
26
25
24
23
30
29
28
27
22
21
20
19
36
35
34
33
32
31
D01AU1273
Name
GND-SUB
OUT2B
Vcc2B
GND2B
GND2A
Vcc2A
OUT2A
OUT1B
Vcc1B
GND1B
GND1A
Vcc1A
OUT1A
NC
Table 2. Pin function
Description
Substrate ground
Output half-bridge 2B
Positive supply
Negative supply
Negative supply
Positive supply
Output half-bridge 2A
Output half-bridge 1B
Positive supply
Negative supply
Negative supply
Positive supply
Output half-bridge 1A
Not connected
11
12
13
14
7
8
9
10
15
16
17
18
3
4
5
6
1
2
GND-SUB
OUT2B
OUT2B
V
CC
2B
GND2B
GND2A
V
CC
2A
OUT2A
OUT2A
OUT1B
OUT1B
V
CC
1B
GND1B
GND1A
V
CC
1A
OUT1A
OUT1A
N.C.
DocID010708 Rev 6
STA518
STA518 Pin description
Pin n°
28
29
30
31
32
33, 34
35, 36
24
25
26
27
19
20
21, 22
23
Name
GND-clean
GND-Reg
V dd
V
L
Table 2. Pin function (continued)
Description
Logical ground
Ground for regulator V dd
5 V regulator referred to ground
Logic reference voltage
PWRDN
TRI-STATE
FAULT
TH_WAR
IN1A
IN1B
IN2A
IN2B
V ss
V
CC
Sign
Short-circuit pin
Hi-Z pin
Fault pin advisor
Thermal warning advisor
Input of half-bridge 1A
Input of half-bridge 1B
Input of half-bridge 2A
Input of half-bridge 2B
5 V regulator referred to +V
CC
Signal positive supply
Pin name Pin n°
Table 3. Functional pin status
Logical value IC - status
FAULT
FAULT *
TRI-STATE
TRI-STATE
PWRDN
PWRDN
TH_WAR
TH_WAR
(1)
26
25
25
28
28
27
27
26
0
1
0
1
0
1
0
1
Fault detected (short-circuit, or thermal)
Normal operation
All powers in Hi-Z state
Normal operation
Low consumption
Normal operation
Temperature of the IC = 130 °C
Normal operation
1. The pin is an open collector. To have a high logic value, it needs to be pulled up by a resistor.
DocID010708 Rev 6 7/21
21
Electrical specifications STA518
3.1
3.2
Absolute maximum ratings
Symbol
V
CC
V max
T op
P tot
T stg
, T j
Table 4. Absolute maximum ratings
Parameter
DC supply voltage (pin 4, 7, 12, 15)
Maximum voltage on pins 23 to 32
Operating temperature range
Power dissipation (T case
= 70 °C)
Storage and junction temperature
Value
40
5.5
-40 to 90
21
-40 to 150
Recommended operating conditions
Symbol
Table 5. Recommended operating conditions
(1)
Parameter
V
CC
V
L
T amb
DC supply voltage
Input logic reference
Ambient temperature
1. Performance not guaranteed beyond recommended operating conditions
Min.
Typ.
Max.
Unit
10
2.7
0
3.3
36.0
5.0
70
V
V
°C
Unit
°C
W
V
V
°C
Symbol
Table 6. Thermal data
(1)
Parameter
T j-case
T jSD
T warn t hSD
Thermal resistance junction to case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
Thermal shut-down hysteresis
1. See thermal information
Min.
Typ.
Max.
Unit
150
130
25
1.5
°C/W
°C
°C
°C
8/21
The power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. The PSSO36 package of the STA518 includes an exposed thermal slug on the top of the device to provide a direct thermal path from the IC to the heatsink. For the quad single-ended application the dissipated power vs. output power is
.
DocID010708 Rev 6
STA518 Electrical specifications
Considering that for the STA518 the thermal resistance junction to slug is 1.5 °C/W and the estimated thermal resistance due to the grease placed between slug and heat sink is
2.3 °C/W (the use of thermal pads for this package is not recommended), the suitable heat sink R th
to be used can be drawn from the following graph
Figure 11 , where is shown the
derating power vs. t amb
for different heat sinks.
Refer to the circuit in Figure 3 (V
L
°C unless otherwise specified)
= 3.3 V; V
CC
= 30 V; R
L
= 8 ; f sw
= 384 kHz; T amb
= 25
Symbol
R dsON
I dss g
N g
P
Dt_s
Dt_d t d ON t d OFF t r t f
V
CC
Parameter
Table 7. Electrical characteristics
Test conditions
Power P-channel / N-channel
MOSFET R dsON
Power P-channel / N-channel leakage I dss
Power P-channel R dsON matching
I
I d
V d
= 1 A
CC
= 35 V
= 1 A
Power N-channel R dsON matching
Low current dead time (static)
I d
= 1 A see test circuit
High current dead time (dynamic)
Turn-on delay time
Turn-off delay time
L = 22 μ H; C = 470 nF; R
L
= 8
I d
Resistive load; V
CC
= 30 V
Resistive load; V
CC
= 30 V
Rise time
Resistive load; as
Fall time
Supply voltage operating voltage
V
IN-H
High-level input voltage
Min.
95
95
10
Typ.
Max.
Unit
200
10
270
50
20
50
100
100
25
25
36
V
L
/2
+300mV m
μ A
%
% ns ns ns ns ns ns
V
V
V
L
/2 -
300mV
V
IN-L
Low-level input voltage
I
I
IN-H
IN-L
I
PWRDN-H
V
V
I
LOW
HIGH
VCC-
PWRDN
High-level input current
Low-level input current
High-level PWRDN pin input current
Low logical state voltage V
(pin PWRDN, TRISTATE)
High logical state voltage V
(pin PWRDN, TRISTATE)
Pin voltage = V
L
Pin voltage = 0.3 V
V
V
V
L
L
L
= 3.3 V
= 3.3 V
= 3.3 V
Supply current from V
CC down
in power
PWRDN = 0
0.8
1
1
35
1.7
3
V
A
A
A
V
V mA
DocID010708 Rev 6 9/21
21
Electrical specifications STA518
Symbol
Table 7. Electrical characteristics (continued)
Parameter Test conditions
I
I
FAULT
VCC-hiz
Output current pins
FAULT, TH_WAR when fault conditions
Supply current from V
CC state
in Tri-
V
V pin
CC
= 3.3 V
= 30 V; Tri-state = 0
I
VCC
Supply current from V operation
CC
in
(both channels switching)
V
CC
= 30V;
Input pulse width = 50% Duty;
Switching frequency = 384 kHz;
No LC filters;
V
CC
= 30 V I
VCC-q
V
UV
I sc
(short-circuit current limit)
(2)
Undervoltage protection threshold t pw_min
Output minimum pulse width No load
1.
explains the V
LOW
, V
HIGH
variation with I bias
.
2. See relevant Application Note AN1994
Min.
3.5
70
Typ.
Max.
Unit
1
22
50
6
7
150 mA mA mA
A
V ns
V
L
2.7
3.3
5
Table 8. V
LOW
, V
HIGH
variation with I bias
V
Low min
V
High max
0.7
0.8
0.85
1.5
1.7
1.85
Unit
V
V
V
TRI-STATE
0
1
1
1
1
INxA x
0
0
1
1
Table 9. Logic truth table (see Figure 4 )
INxB Q1 Q2 Q3 x
0
1
0
1
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
Q4
OFF
ON
OFF
ON
OFF
Output mode
Hi-Z
DUMP
NEGATIVE
POSITIVE
Not used
10/21 DocID010708 Rev 6
STA518 Electrical specifications
Figure 3. Low-current dead time for single-ended application: test circuit
OUTxY
Vcc
Low current dead time = MAX(DTr,DTf)
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
+Vcc t
Duty cycle = 50%
DTr DTf
M58
R 8 Ω
INxY
OUTxY
M57 gnd
+
-
V67 = vdc = Vcc/2
D03AU1458
Figure 4. High-current dead time for bridge application: block diagram
+V
CC
Q1
OUTxA
Q2
OUTxB
INxA INxB
Q3 Q4
GND
D00AU1134
Duty cycle=A
Figure 5. High-current dead time for bridge application: test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=B
DTin(A)
INA
M58
M57
DTout(A)
Q1
Q3
OUTA
Iout=4.5A
L67 22
μ
C69
470nF
Rload=8
Ω
C71 470nF
DTout(B)
L68 22
μ
Iout=4.5A
OUTB
Q2
C70
470nF
Q4
M64
M63
DTin(B)
INB
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D03AU1517
DocID010708 Rev 6 11/21
21
Technical information STA518
4.1
12/21
The STA518 is a high-efficiency dual-channel H-Bridge that is able to deliver 50 W per channel (@ THD = 10% R
L
= 8 , V
CC
= 29 V) of audio output power.
The STA518 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a logic interface, integrated bridge drivers, high-efficiency MOSFET outputs and thermal and short-circuit protection circuitry.
In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a bridge configuration, according to the damped ternary modulation operation.
In binary mode operation, both full-bridge and half-bridge modes are supported. The
STA518 includes overcurrent and thermal protection as well as an undervoltage lockout with automatic recovery. A thermal warning status is also provided.
Figure 6. STA518 block diagram full-bridge DDX ® or binary modes
INL 1:2
INR 1:2
VL
PWRDN
TRI-STATE
Logic I/F and Decode
Left
H-Bridge
OUTPL
OUTNL
FAULT
TWARN
Protection
Circuitry
OUTPR
Right
H-Bridge
Regulators OUTNR
Figure 7. STA518 block diagram binary half-bridge mode
INL 1:2
INR 1:2
VL
PWRDN
TRI-STATE
Logic I/F and Decode
LeftA
-Bridge
LeftB
-Bridge
OUTPL
OUTNL
FAULT
TWARN
Protection
Circuitry
Regulators
RightA
-Bridge
RightB
-Bridge
OUTPR
OUTNR
Logic interface and decode
The STA518 power outputs are controlled using one or two logic level timing signals. In order to provide a proper logic interface, the V bias the DDX control logic supply.
input must operate at the same voltage as
Protection circuitry:
The STA518 includes protection circuitry for overcurrent and thermal overload conditions. A thermal warning pin (pin 28) is activated low (open-drain MOSFET) when the IC
DocID010708 Rev 6
STA518 Technical information temperature exceeds 130 °C, in advance of the thermal shutdown protection. When a fault condition is detected, an internal fault signal acts to immediately disable the output power
MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-drain
MOSFET connected to the FAULT pin (pin 27) is switched on.
There are two possible modes subsequent to activating a fault:
1.
SHUTDOWN mode : with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output.
The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from high to low to high using an external logic signal.
2. AUTOMATIC recovery mode: This is shown in the audio application circuit of quad single-ended. The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising R59 and C58.
An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit.
If the fault condition is still present, the circuit operation will continue repeating until the fault condition is removed.
An increase in the time constant of the circuit will produce a longer recovery interval.
Care must be taken in the overall system design as not to exceed the protection thresholds under normal operation.
4.3
The STA518 power and output pins are duplicated to provide a low impedance path for the device's bridged outputs. All duplicate power, ground and output pins must be connected for proper operation.
The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, V
L
, is settled.
Parallel output / high current operation
When using DDX mode output, the STA518 outputs can be connected in parallel in order to increase the output current capability to a load. In this configuration the STA518 can provide
70 W into 8 ohm.
This mode of operation is enabled with the CONFIG pin (pin 24) connected to VREG1 and the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB,
OUTRA=OUTRB.
Output Filter: A passive 2 nd
order passive filter is used on the STA518 power outputs to reconstruct an analog audio signal. System performance can be significantly affected by the output filter design and choice of passive components. A filter design for 6 ohm / 8 ohm loads is shown in the typical application circuit of
.
Quad single-ended circuit (
) shows a filter for half-bridge mode, 4 ohm loads.
DocID010708 Rev 6 13/21
21
Technical information STA518
Figure 8. Typical stereo full-bridge configuration to obtain 50 + 50 W @ THD = 10%,
R
L
= 8 , V
CC
= 29 V
+V
CC V
CC
1A
15
IN1A
IN1A 29 M3
C30
1
μ
F
L18 22 μ H
C55
1000
μ
F
+3.3V
VL
CONFIG
23
24
17
16
OUT1A
TH_WAR
R57
10K
PWRDN
R59
10K
C58
100nF
PWRDN
FAULT
TRI-STATE
TH_WAR
IN1B
25
27
26
PROTECTIONS
&
LOGIC
M2
M5
14
12
11
OUT1A
GND1A
V
CC
1B
C31
1 μ F
C20
100nF
C52
330pF R98
6
R63
20
R100
6
C21
100nF
L19 22 μ H
C99
100nF
C23
470nF
C101
100nF
8 Ω
IN1B
28
30
10
OUT1B
OUT1B
M4
V
DD
V
DD
V
SS
V
SS
21
22
33
34
REGULATORS
13
7
GND1B
V
CC
2A
C58
100nF
C53
100nF V
CC
SIGN
35
M17
8
C32
1 μ F
L113 22
μ
H
OUT2A
C60
100nF V
CC
SIGN
IN2A
IN2A
GND-Reg
IN2B
GND-Clean
IN2B
36
31
20
19
32
M15
M16
9
6
4
3
2
OUT2A
GND2A
V
CC
2B
OUT2B
OUT2B
C33
1
μ
F
C110
100nF
C109
330pF R103
6
R104
20
R102
6
C111
100nF
L112 22
μ
H
C107
100nF
C108
470nF
C106
100nF
8
Ω
GNDSUB M14
1 5 GND2B
D00AU1148B
Figure 9. Typical single BTL configuration to obtain 70 W @ THD 10%, R
L
V
CC
= 34 V (a)
= 8 ,
VL
+3.3V
23
TH_WAR
10K nPWRDN
IN1A
IN1B
100nF
100nF
X7R
10K
100nF
100nF
X7R
GND-Clean
GND-Reg
19
20
V
DD
V
DD
CONFIG
TH_WAR
PWRDN
FAULT
28
25
27
26
TRI-STATE
IN1A
IN1B
IN2A
IN2B
V
SS
V
SS
33
34
29
30
31
32
21
22
24
V
CC
SIGN
35
100nF
X7R
Add.
V
CC
SIGN
GNDSUB
36
1
18 N.C.
17
16
OUT1A
OUT1A
11
10
9
8
OUT1B
OUT1B
OUT2A
OUT2A
3
2
OUT2B
OUT2B
15
V
CC
1A
12
V
CC
1B
7
V
CC
2A
4
V
CC
2B
GND1A
14
13
GND1B
6
GND2A
GND2B
5
22 μ H
22 Ω
1/2W
330pF
22
μ
H
6.2
1/2W
6.2
1/2W
100nF
FILM
100nF
FILM
100nF
X7R
470nF
FILM
100nF
X7R
1 μ F
X7R
2200 μ F
63V
32V
1
μ
F
X7R
32V
8 Ω
D04AU1549
14/21 a. A PWM modulator as driver is needed. In particular, this result is achieved using the STA308 + STA518 +
STA50X demo board. Peak Power for t 1sec.
DocID010708 Rev 6
STA518 Characterization curves
The following characterization curves are obtained using the quad single-ended
) with an STA308A controller.
Figure 10. Power dissipation vs. output power Figure 11. Power derating curve
Figure 12. THD+N vs. output power Figure 13. Output power vs. supply voltage
Figure 14. THD vs. frequency
DocID010708 Rev 6 15/21
21
Characterization curves STA518
The following characterizations are obtained using the stereo full-bridge configuration
) with STA308A controller.
Figure 15. Output power vs. supply voltage Figure 16. THD+N vs. output power
Figure 17. Power dissipation vs. output power
The following characterization is obtained using a single BTL configuration ( Figure 9 ) with
the STA308A controller.
Figure 18. THD+N vs. output power
16/21 DocID010708 Rev 6
STA518 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID010708 Rev 6 17/21
21
Figure 19. PSSO36 (slug up) mechanical outline
7618147_F
STA518 Package information
Symbol k
L
H h e e3
F
G
D
E b c
A
A2 a1
S
T
U
O
Q
M
N
Min.
10.1
-
0 deg
0.55
-
-
-
-
2.15
2.15
0
0.18
0.23
10.10
7.4
-
-
-
-
-
-
-
Table 10. PowerSO36 exposed pad up dimensions
Dimensions in mm.
Dimensions in inch.
Typ.
-
-
-
-
0.5
8.5
2.3
-
-
-
-
-
-
-
-
4.3
-
1.2
0.8
2.9
3.65
1.0
Max.
10.5
0.4
8 deg
0.85
-
0.1
-
-
2.45
2.35
0.1
0.36
0.32
10.50
7.6
-
10 deg
-
-
-
-
-
0.169
-
0.047
0.031
0.114
0.114
0.039
Typ.
-
-
-
0.020
0.335
0.091
-
-
-
-
-
-
-
-
Min.
-
-
0 deg
0.022
-
-
-
-
0.085
0.085
0.00
0.007
0.009
0.398
0.291
-
-
-
-
-
-
-
Max.
-
-
-
0.004
0.413
0.016
8 deg
0.033
0.096
0.092
0.004
0.014
0.013
0.413
0.299
-
10 deg
-
-
-
-
-
DocID010708 Rev 6 19/21
21
Revision history STA518
Date
19-Aug-2004
11-Nov-2004
18-May-2006
26-Feb-2014
11-Jul-2014
16-Sep-2014
Revision
Table 11. Document revision history
Changes
4
5
1
2
3
6
Initial release.
Changed symbol in “Electrical Characteristics”.
Changed operating temperature range value to -40 to 90°C
).
Updated order code
.
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20/21 DocID010708 Rev 6
STA518
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
DocID010708 Rev 6 21/21
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