STMicroelectronics VND5E008AY-E Datasheet

VND5E008AY-E

Features

Double channel high-side driver with analog current sense for automotive applications

Datasheet

-

production data

PowerSSO-36

•

Protection:

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Thermal shut down

– Reverse battery protection with self switch of the Power MOS

Max transient supply voltage

Operating voltage range

Typ on-state resistance (per ch.)

Current limitation (typ)

Off-state supply current

1.

Typical value with all loads connected.

V

CC

V

CC

R

ON

I

LIMH

I

S

41 V

4.5 to 28V

8 m Ω

76 A

2 μ A

(1)

Applications

• All types of resistive, inductive and capacitive loads

•

General:

– Inrush current active management by power limitation

– Very low standby current

– 3.0V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– Compliant with European directive

2002/95/EC

– Proportional load current sense

– High current sense precision for wide range current

– Very low current sense leakage

•

Diagnostic functions:

– Off-state open-load detection

– Current sense disable

– Thermal shutdown indication

– Output short to V

CC

detection

– Overload and short to ground (power limitation) indication

Description

The VND5E008AY-E is a device made using

STMicroelectronics

®

VIPower

®

MO-5 technology.

It is intended for driving resistive or inductive loads with one side connected to ground. Active

V

CC

pin voltage clamp protects the device against low energy spikes.

This device integrates an analog current sense which delivers a current proportional to the load current when CS_DIS high leads the current sense pin in high impedance.

Fault conditions such as overload, overtemperature or open-load are reported via the current sense pin

Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention.

Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

October 2013

This is information on a product in full production.

DocID13620 Rev 5

1/39

www.st.com

6

7

1

2

Contents

Contents

3

4

5

VND5E008AY-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3.1

Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 27

3.4

Maximum demagnetization energy (V

CC

= 13.5 V) . . . . . . . . . . . . . . . . . 29

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1

PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2/39

DocID13620 Rev 5

VND5E008AY-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (V

CC

= 13V; T j

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Current sense (8 V < V

CC

< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Open-load detection (8 V < V

CC

< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12.

Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13.

Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14.

Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15.

Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16.

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DocID13620 Rev 5

3/39

3

List of figures

List of figures

VND5E008AY-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

I

OUT

/I

SENSE

vs I

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

Delay response time between rising edge of output current and rising edge of current sense

(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11.

Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.

Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.

Off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15.

Short to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16.

T

J

evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 20.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 21.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 22.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 23.

On-state resistance vs T

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 24.

On-state resistance vs V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 25.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26.

I

LIMH

vs T case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 27.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 28.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 29.

CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 30.

Low level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 31.

High level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 32.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 33.

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 34.

Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 35.

PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 36.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 31

Figure 37.

PowerSSO-36 Thermal impedance junction ambient single pulse (one channel ON) . . . . 31

Figure 38.

Thermal fitting model of a double channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . . 32

Figure 39.

PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 40.

PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 41.

PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/39

DocID13620 Rev 5

VND5E008AY-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1. Block diagram

9

&&

,1

,1

6LJQDO&ODPS

8QGHUYROWDJH

5HYHUVH

%DWWHU\

3URWHFWLRQ

&RQWURO 'LDJQRVWLF

&RQWURO 'LDJQRVWLF

3RZHU

&ODPS

'5,9(5

9

21

/LPLWDWLRQ

2YHU

WHPS

&XUUHQW

/LPLWDWLRQ

&+

&6B

',6

9

6(16(+

&6

&6

Name

V

CC

OUT

1,2

GND

IN

1,2

CS

1,2

CS_DIS

/2*,&

)DXOW

29(5/2$'3527(&7,21

$&7,9(32:(5/,0,7$7,21

&XUUHQW

6HQVH

&+

287

287

*1'

*$3*&)7

Table 1. Pin function

Function

Battery connection

Power output

Ground connection

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state

Analog current sense pin, delivers a current proportional to the load current

Active high CMOS compatible pin, to disable the current sense pin

DocID13620 Rev 5

5/39

38

Block diagram and pin description

Figure 2. Configuration diagram (top view)

287

287

287

287

287

287

287

287

287

287

1&

1&

,1

1&

&6

1&

1&

*1'

287

287

287

287

287

287

287

287

287

287

1&

1&

,1

1&

&6

1&

1&

&6B',6

7$% 9

&&

VND5E008AY-E

("1($'5

Table 2. Suggested connections for unused and not connected pins

Connection / pin

Current sense N.C.

Output Input CS_DIS

Floating

To ground

Not allowed

Through 1 K Ω resistor

X

X

X

Not allowed

X

Through 10 K Ω resistor

X

Through 10 K Ω resistor

6/39

DocID13620 Rev 5

VND5E008AY-E Electrical specifications

9

&6'

9

,1

9

,1

Figure 3. Current and voltage conventions

,

&6'

,

,1

,

,1

&6B',6

,1

,1

*1'

,

*1'

,

6

9

&&

9

)Q

,

287

287

,

6(16(

&6

,

287

9

6(16(

287

&6

,

6(16(

9

6(16(

9

287

9

287

9

&&

*$3*&)7

Symbol

Table 3. Absolute maximum ratings

Parameter

V

CC

V

CCPK

-V

CC

DC supply voltage

Transient supply voltage (T < 400 ms, R

LOAD

Reverse DC supply voltage

> 1

Ω

)

V

CC_LSC

Maximum supply voltage for full protection to short-circuit

(acc. AEC-Q100-012)

-I

GND

I

OUT

-I

OUT

I

IN

I

CSD

DC reverse ground pin current

DC output current

Reverse DC output current

DC input current

DC current sense disable input current

V

CSENSE

Current sense maximum voltage

Value

28

41

16

18

200

Internally limited

50

-1 to 10

-1 to 10

V

CC

- 41

+V

CC

E

MAX

V

ESD

Maximum switching energy (single pulse)

(L = 0.85 mH; R

L

= 0 Ω ; V bat

= 13.5 V; T jstart

= 150 °C;

I

OUT

= I limL

(Typ.))

Electrostatic Discharge (Human Body Model: R = 1.5 K Ω;

C = 100 pF)

– V

CC

, OUTPUT

– INPUT, CS_DIS

– CURRENT SENSE

260

5000

4000

2000

V mA

A

A mA mA

V

V

Unit

V

V

V mJ

V

DocID13620 Rev 5

7/39

38

Electrical specifications VND5E008AY-E

Symbol

V

ESD

T j

T stg

Table 3. Absolute maximum ratings (continued)

Parameter

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

Value

750

-40 to 150

-55 to 150

Unit

V

°C

°C

Symbol

Table 4. Thermal data

Parameter

R thj-case

Thermal resistance junction-case (MAX) (with one channel ON)

R thj-amb

Thermal resistance junction-ambient (MAX)

Max. value Unit

0.85

°C/W

See Figure 36

in the

Thermal section

°C/W

8/39

DocID13620 Rev 5

VND5E008AY-E Electrical specifications

8 V < V

CC

< 28 V; -40 °C < T j

< 150 °C, unless otherwise specified

Symbol Parameter

Table 5. Power section

Test conditions

V

CC

V

USD

Operating supply voltage

Undervoltage shutdown

V

USDhyst

Undervoltage shutdown hysteresis

I

OUT

= 6 A; T j

= 25 °C

R

ON

ON-state resistance I

OUT

= 6 A; T j

= 150 °C

I

OUT

= 6 A; V

CC

= 5 V; T j

= 25 °C

R

ON REV

Reverse battery ON-state resistance

V

CC

= -13 V; I

OUT

= -6 A;

T j

= 25 °C

V

I clamp

I

S

L(off)

Clamp Voltage I

S

= 20 mA

Off-state; V

CC

= 13 V; T j

= 25 °C;

V

IN

= V

OUT

= V

SENSE

= V

CSD

= 0 V

Supply current

Off-state output current

(2)

On-state; V

CC

= 13 V; V

IN

= 5 V;

I

OUT

= 0 A

V

IN

= V

OUT

= 0 V; V

CC

= 13 V;

T j

= 25 °C

V

IN

= V

OUT

= 0 V; V

CC

= 13 V;

T j

= 125 °C

1.

PowerMOS leakage included.

2.

For each channel.

Min.

Typ. Max. Unit

4.5

13 28

3.5

4.5

V

V

41

0

0.5

2

8

8

46

(1)

3.5

0.01

5

11

52

(1)

6.5

3

5

V m Ω

15 m

Ω m m

V

Ω

Ω

µA mA

µA

µA

Table 6. Switching (V

CC

= 13V; T j

= 25°C)

Parameter Test conditions Min.

Typ.

Symbol t d(on) t d(off)

(dV

OUT

/dt) on

(dV

OUT

/dt) off

Turn-on delay time R

L

= 2.2 Ω

(see Figure 8 )

Turn-off delay time R

L

= 2.2

Ω

(see Figure 8 )

Turn-on voltage slope

R

L

= 2.2 Ω

Turn-off voltage slope

R

L

= 2.2 Ω

W

ON

Switching energy losses during t won

R

L

= 2.2 Ω (see

Figure 8

)

W

OFF

Switching energy losses during t woff

R

L

= 2.2 Ω (see

Figure 8

)

—

—

—

—

—

—

30

15

See

Figure 23

See

Figure 24

1.2

0.43

Max.

Unit

—

—

—

—

—

—

µs

µs

V / µs

V / µs mJ mJ

DocID13620 Rev 5

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38

Electrical specifications VND5E008AY-E

Symbol

Table 7. Current sense (8 V < V

CC

< 18 V)

Parameter Test conditions Min. Typ. Max. Unit dK dK dK

V

I

I

1

/K

2

/K

3

/K

1

(1)

2

(1)

3

(1)

SENSE0

V

K

K

K

K

0

1

2

3

SENSE

SENSEH

SENSEH t

DSENSE1H

I

I

I

I

OUT

OUT

/I

/I

SENSE

SENSE

Current sense ratio drift

OUT

Current sense ratio drift

OUT

/I

/I

SENSE

SENSE

Current sense ratio drift

I

OUT

= 0.25 A; V

SENSE

= 0.5 V

T j

= -40 °C...150 °C

I

OUT

= 6 A; V

SENSE

= 0.5 V

T j

= -40 °C...150 °C

T j

= 25 °C...150 °C

I

OUT

= 6 A; V

SENSE

= 0.5 V

V

CSD

= 0 V;

T

J

= -40 °C to 150 °C

I

OUT

= 10 A; V

SENSE

= 4 V

T j

= -40 °C...150 °C

T j

= 25 °C...150 °C

I

OUT

= 10 A; V

SENSE

= 4 V;

V

CSD

= 0 V;

T j

= -40 °C to 150 °C

I

OUT

= 25 A; V

SENSE

= 4 V

T j

= -40 °C...150 °C

T j

= 25 °C...150 °C

I

OUT

= 25 A; V

SENSE

= 4 V;

V

CSD

= 0V;

T j

= -40 °C to 150 °C

Analog sense leakage current

I

OUT

= 0 A; V

SENSE

= 0 V;

V

CSD

= 5 V; V

IN

= 0 V;

T j

= -40 °C...150 °C

V

CSD

= 0 V; V

IN

= 5 V;

T j

= -40 °C...150 °C

I

OUT

= 6 A; V

SENSE

= 0 V;

V

CSD

= V

IN

= 5 V;

Max analog sense output voltage

I

OUT

= 15 A; V

CSD

= 0 V

Analog sense output voltage in overtemperature condition

(2)

Analog sense output current in overtemperature condition

(2)

V

V

CC

CC

= 13 V; R

= 13 V; V

SENSE

SENSE

= 10 K

= 5 V

Ω

Delay Response time from falling edge of

CS_DIS pin

V

SENSE

< 4 V, 1.5 A < I

OUT

< 25 A

I

SENSE

= 90 % of I

SENSE max

(see Figure 4 )

3658 6000 8926

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6000

8928

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5298

6000

6000

7372

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-7 7

5455

5535

6000

6000

6762

6282

-5

0

0

0

5

8

9

50

5

1

2

1

100

%

%

%

µA

µA

µA

V

V mA

µs

10/39

DocID13620 Rev 5

VND5E008AY-E Electrical specifications

Symbol

Table 7. Current sense (8 V < V

CC

< 18 V) (continued)

Parameter Test conditions Min. Typ. Max. Unit t t

DSENSE1L

DSENSE2H

Delay Response time from rising edge of

CS_DIS pin

Delay Response time from rising edge of

INPUT pin

V

SENSE

< 4 V, 1.5 A < I

OUT

< 25 A

I

SENSE

= 10 % of I

SENSE max

(see Figure 4 )

V

SENSE

< 4 V, 1.5 A < I

OUT

< 25 A

I

SENSE

= 90 % of I

SENSE max

(see Figure 4 )

5

70

20

300

µs

µs

Δ t t

DSENSE2H

DSENSE2L

Delay response time between rising edge of output current and rising edge of current sense

Delay Response time from falling edge of

INPUT pin

V

SENSE

< 4 V,

I

SENSE

= 90 % of I

SENSEMAX,

I

OUT

= 90 % of I

OUTMAX

I

OUTMAX

= 5 A (see

Figure 11 )

V

SENSE

< 4 V, 1.5 A < I

OUT

< 25 A

I

SENSE

= 10 % of I

SENSE max

(see Figure 4 )

100

1.

Parameter guaranteed by design; it is not tested.

2.

Fault condition includes: power limitation, overtemperature and open load OFF-state detection.

300

250

µs

µs

Symbol

I

V

OL

L(off2)r

Open-load off-state voltage detection threshold t

DSTKON

Output short circuit to V

CC detection delay at turn-off

Off-state output current at

V

OUT

= 4 V

I

L(off2)f

Table 8. Open-load detection (8 V < V

CC

< 18 V)

Parameter

Off-state output current at

V

OUT

= 2 V

Test conditions

V

IN

= 0 V

Min Typ Max Unit

2 — 4 V

See Figure 5

180 — 1200 µs

V

IN

= 0V; V

SENSE

= 0 V;

V

OUT

rising from 0 V to 4 V

V

IN

= 0V;

V

SENSE

= V

SENSEH

;

V

OUT

falling from V

CC

to 2 V

-120 —

-50 —

90

90

µA

µA

Symbol

I limH

I limL

T

TSD

Table 9. Protections

(1)

Test conditions Parameter

DC short circuit current

V

CC

= 13 V

5 V < V

CC

< 18 V

Short circuit current during thermal cycling

V

CC

= 13 V; T

R

< T j

< T

TSD

Shutdown temperature

T

R

T

RS

Reset temperature

Thermal reset of

STATUS

Min.

Typ.

Max.

Unit

53 76 106

106

A

A

21 A

150 175

T

RS

+1

T

RS

+5

135

200 °C

°C

°C

DocID13620 Rev 5

11/39

38

Electrical specifications VND5E008AY-E

Parameter

Table 9. Protections

(1)

(continued)

Test conditions Min.

Typ.

Max.

Unit Symbol

T

HYST

V

DEMAG

Thermal hysteresis

(T

TSD

- T

R

)

Turn-off output voltage clamp

I

OUT

= 2 A; V

IN

= 0; L = 6 mH

V

ON

Output voltage drop limitation

I

OUT

= 0.4 A; T j

= -40 °C...150 °C

(see

Figure 10 )

V

CC

29

V

7

CC

32

25

V

CC

36

1.

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

-

°C

V mV

Table 10. Logic input

Test conditions Symbol Parameter

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

V

IN

IN

= 0.9 V

= 2.1 V

V

ICL

Input clamp voltage

I

IN

= 1 mA

I

IN

= -1 mA

V

CSDL

I

CSDL

V

CSCL

CS_DIS low level voltage

Low level CS_DIS current V

CSD

= 0.9 V

V

CSDH

I

CSDH

CS_DIS high level voltage

High level CS_DIS current V

CSD

= 2.1 V

V

CSD(hyst

)

CS_DIS hysteresis voltage

CS_DIS clamp voltage

I

CSD

= 1 mA

I

CSD

= -1 mA

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

1

2.1

-0.7

10

7

0.9

10

V

V

µA

V

µA

V

µA

V

µA

V

V

0.25

5.5

7

-0.7

V

V

V

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12/39

DocID13620 Rev 5

VND5E008AY-E Electrical specifications

Figure 5. Open-load off-state delay timing

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Figure 6. I

OUT

/I

SENSE

vs I

OUT

9250

8500

7750

7000

6250

5500

4750

4000

3250

2500

0.0

C

A

E

5.0

B

D

10.0

15.0

, Tj = 25 °C t

50 °C

: Min,

GAPGRI00301

DocID13620 Rev 5

13/39

38

Electrical specifications VND5E008AY-E

Figure 7. Maximum current sense ratio drift vs load current

20 dK/K [%]

15

10

5

A

-10

-15

0

-5

B

-20

0 5 10 15

Iout [A]

20 25

A: Max, Tj = -40 C to 150 C B: Min, Tj = -40 C to 150 C

30

Conditions

Normal operation

Overtemperature

Undervoltage

Overload

Table 11. Truth table

Input

L

H

L

H

L

H

H

H

Output

L

L

L

H

L

L

X

(no power limitation)

Cycling

(power limitation)

L

L

Sense (V

CSD

= 0 V)

(1)

0

Nominal

0

V

SENSEH

0

0

Nominal

V

SENSEH

Short circuit to GND

(Power limitation)

Open-load off-state

(with external pull up)

L

H

L H

V

V

0

SENSEH

SENSEH

Short circuit to V

CC

(external pull up disconnected)

Negative output voltage clamp

L

H

L

H

H

L

V

SENSEH

< Nominal

0

1.

If the V

CSD

is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.

14/39

DocID13620 Rev 5

VND5E008AY-E

9

287

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RQ

W

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Figure 8. Switching characteristics

W

:RQ

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:RII

Electrical specifications

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Figure 9. Delay response time between rising edge of output current and rising edge of current sense (CS enabled)

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DocID13620 Rev 5

15/39

38

Electrical specifications

Figure 10. Output voltage drop limitation

9

&&

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VND5E008AY-E

16/39

DocID13620 Rev 5

VND5E008AY-E Electrical specifications

ISO 7637-2:

2004(E)

Test pulse

Table 12. Electrical transient requirements (part 1)

III

Test levels

(1)

IV

Number of pulses or test times

Burst cycle/pulse repetition time

Delays and impedance

1

2a

-75 V

+37 V

-100 V

+50 V

5000 pulses

5000 pulses

0.5 s

0.2 s

5 s

5 s

2 ms, 10

50 µs, 2

Ω

Ω

3a

3b

4

5b

(2)

-100 V

+75 V

-6 V

+65 V

-150 V

+100 V

-7 V

+87 V

1h

1h

1 pulse

1 pulse

90 ms

90 ms

100 ms

100 ms

0.1 µs, 50 Ω

0.1 µs, 50 Ω

100 ms, 0.01

Ω

400 ms, 2 Ω

1.

The above test levels must be considered referred to V

CC

= 13.5 V except for pulse 5b.

2.

Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy along the time and to transfer a part of it to the load.

ISO 7637-2:

2004(E)

Test pulse

Table 13. Electrical transient requirements (part 2)

III

Test level results

(1)

IV

1

2a

3a

3b

C

C

C

C

C

C

C

C

4

5b

(2)(3)

C C

C C

1.

The above test levels must be considered referred to V

CC

= 13.5 V except for pulse 5b.

2.

Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy along the time and to transfer a part of it to the load.

3.

Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in

Table 3: Absolute maximum ratings .

Class

C

E

Table 14. Electrical transient requirements (part 3)

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the

DocID13620 Rev 5

17/39

38

Electrical specifications

2.4 Waveforms

VND5E008AY-E

Figure 11. Normal operation

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19/39

38

Electrical specifications

Figure 14. Off-state open-load with external circuitry

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20/39

DocID13620 Rev 5

VND5E008AY-E Electrical specifications

Figure 15. Short to V

CC

6KRUWWR9

&&

5HVLVWLYH

6KRUWWR9

&&

+DUG

6KRUWWR9

&&

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J

evolution in overload or short to GND

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21/39

38

Electrical specifications VND5E008AY-E

,ORII>Q$@

Figure 17. Off-state output current Figure 18. High level input current

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Figure 19. Input clamp voltage

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Figure 20. Input high level

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Figure 21. Input low level

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Figure 22. Input hysteresis voltage

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22/39

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DocID13620 Rev 5

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Figure 23. On-state resistance vs T case

5RQ>P2KP@

Electrical specifications

Figure 24. On-state resistance vs V

CC

5RQ>P2KP@

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LIMH

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Figure 27. Turn-on voltage slope

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23/39

38

Electrical specifications

9FVGFO>9@

Figure 29. CS_DIS clamp voltage

,LQ P$

VND5E008AY-E

Figure 30. Low level CS_DIS voltage

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Figure 31. High level CS_DIS voltage

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24/39

DocID13620 Rev 5

VND5E008AY-E Application information

3.1

3.2

Figure 32. Application schematic

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Note: Channel 2 has the same internal circuit as channel 1.

Load dump protection

D ld

is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the

V

CCPK

max rating. The same applies if the device is subject to transients on the V

CC

line that are greater than the ones shown in the ISO T/R 7637/1 table.

MCU I/Os protection

When negative transients are present on the V

CC

line, the control pin is pulled negative to approximately -1.5 V. ST suggests to insert a resistor (R prot

) in line to prevent the microcontroller I/O pins from latching-up.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os.

Equation 1:

-V

CCpeak

/ I latchup

≤

R prot

≤

(V

OH

μ

C

- V

IH

) / I

IHmax

Calculation example:

For V

CCpeak

= - 1.5 V; I latchup

≥

20 mA; V

OH

μ

C

≥

4.5 V

75 Ω ≤ R prot

≤ 240 k Ω .

Recommended values: R prot

=10 k Ω, C

EXT

=10 nF

.

DocID13620 Rev 5

25/39

38

Application information

3.3

VND5E008AY-E

Current sense and diagnostic

The current sense pin performs a double function (see

Figure 33: Current sense and diagnostic

):

•

Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio K

X

.

The current I

SENSE

can be easily converted to a voltage V

SENSE

by means of an external resistor R

SENSE

. Linearity between I

OUT

and V

SENSE

is ensured up to 5 V minimum (see parameter V

SENSE

in Table 7: Current sense (8 V < VCC < 18 V)

). The current sense accuracy depends on the output current (refer to current sense electrical characteristics

Table 7: Current sense (8 V < VCC < 18 V)

).

•

Diagnostic flag in fault conditions, delivering a fixed voltage V maximum current I

SENSEH

SENSEH

up to a

in case of the following fault conditions (refer to

Table 11: Truth table

):

– Power limitation activation

– Overtemperature

– Short to V

CC

in off-state

– Open-load in off-state with additional external components.

A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high-impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.

26/39

DocID13620 Rev 5

VND5E008AY-E Application information

Figure 33. Current sense and diagnostic

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Short to V

CC

and off-state open-load detection

Short to V

CC

A short-circuit between V

CC and output is indicated by the relevant current sense pin set to

V

SENSEH

during the device off-state. Small or no current is delivered by the current sense during the ON-state depending on the nature of the short-circuit.

Off-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor R

PU

connecting the output to a positive supply voltage V

PU

.

It is preferable V

PU

to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected.

An external pull-down resistor R

PD

connected between output and GND is mandatory to

avoid misdetection in case of floating outputs in off-state (see Figure 33: Current sense and diagnostic

).

R

PD

must be selected in order to ensure V circuitry:

OUT

< V

OLmin

unless pulled-up by the external

DocID13620 Rev 5

27/39

38

Application information VND5E008AY-E

Equation 2:

V

OUT

Pull

− up _ OFF

=

R

PD

⋅

I

L ( off 2 ) f

<

V

OL min

=

2 V

R

PD

≤ 22 k Ω is recommended.

For proper open-load detection in off-state, the external pull-up resistor must be selected according to the following formula:

Equation 3:

V

OUT

Pull − up _ ON

=

(

R

PD

⋅

V

PU

(

)

−

(

R

PU

R

PU

+

⋅

R

PD

R

PD

)

⋅

I

L ( off 2 ) r

)

>

V

OL max

=

4 V

For the values of V

OLmin

,V

OLmax

, I

L(off2)r and I

(8 V < VCC < 18 V) ).

L(off2)f

(see

Table 8: Open-load detection

28/39

DocID13620 Rev 5

VND5E008AY-E

3.4 Maximum demagnetization energy (V

CC

Application information

= 13.5 V)

Figure 34. Maximum turn-off current versus inductance

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A: T jstart

= 150 °C (single pulse)

B: T jstart

= 100 °C (repetitive pulse)

C: T jstart

= 125 °C (repetitive pulse)

V

IN

, I

L

Demagnetization Demagnetization Demagnetization

Note: t

Values are generated with R

L

= 0

Ω.

In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

DocID13620 Rev 5

29/39

38

Package and PCB thermal data

4 Package and PCB thermal data

4.1 PowerSSO-36 thermal data

Figure 35. PowerSSO-36 PC board

VND5E008AY-E

30/39

$*9

Note:

Layout condition of R th

and Z th

measurements (Board finish thickness 1.6 mm +/-10 %; Board double layer; Board dimension 129 mm x 60 mm; Board Material FR4; Cu thickness 0.070 mm;

Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/-0.08 mm; Cu thickness on vias

0.025 mm; Footprint dimension 4.1 mm x 6.5 mm)

DocID13620 Rev 5

VND5E008AY-E Package and PCB thermal data

Figure 36. R thj-amb

vs PCB copper area in open box free air condition (one channel

ON)

57+MBDPEƒ&:

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57+MDPE

3&%&XKHDWVLQNFPA

*$3*&)7

Figure 37. PowerSSO-36 Thermal impedance junction ambient single pulse (one channel ON)

=7+ƒ&:

&X FP

&X FP

&X IRRWSULQW

7LPHV

("1($'5

DocID13620 Rev 5

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38

Package and PCB thermal data VND5E008AY-E

Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-36

32/39

Equation 4: pulse calculation formula

Z

TH

δ where

= R

TH

δ

= t

⋅ p

δ

+ Z

THtp

(

1 –

δ )

⁄

T

*$3*&)7

Note:

The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Table 15. Thermal parameter

Area/island (cm

2

) Footprint

R1 = R7 (°C/W)

R2 = R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 = C7 (W.s/°C)

C2 = C8 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

0.05

0.3

5

8

18

27

0.004

0.008

0.04

0.5

1

3

2

10

23

2

6

8

10

14

2

9

DocID13620 Rev 5

VND5E008AY-E Package information

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

DocID13620 Rev 5

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38

Package information

5.2 PowerSSO-36 mechanical data

Figure 39. PowerSSO-36 package dimensions

VND5E008AY-E

34/39

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VND5E008AY-E

Symbol

G1

H h

L e e3

G

N

X

Y

A

A2 a1 b c

D

E

Table 16. PowerSSO-36 mechanical data

Millimeters

Min.

—

10.1

—

0.55

—

—

—

—

4.1

6.5

2.15

2.15

0

0.18

0.23

10.10

7.4

Typ.

—

—

—

—

0.5

8.5

—

—

—

—

—

—

—

—

—

—

—

Package information

Max.

—

—

0.1

0.06

10.5

0.4

0.85

10 deg

4.7

7.1

2.47

2.40

0.075

0.36

0.32

10.50

7.6

DocID13620 Rev 5

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38

Package information VND5E008AY-E

&

Figure 40. PowerSSO-36 tube shipment (no suffix)

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

49

1225

532

3.5

13.8

0.6

All dimensions are in mm.

$

%

Figure 41. PowerSSO-36 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

24

4

P 12

D (± 0.05) 1.55

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

GAPGCFT00003

36/39

DocID13620 Rev 5

VND5E008AY-E Order codes

Package

PowerSSO-36

Table 17. Device summary

Order codes

Tube

VND5E008AY-E

Tape and reel

VND5E008AYTR-E

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38

Revision history VND5E008AY-E

38/39

Date

05-Jun-2007

20-Apr-2011

12-July-2012

20-Sep-2013

25-Oct-2013

Table 18. Document revision history

Revision Changes

1

2

3

4

5

Initial release

Updated Features list.

Updated following figures:

–

Figure 1: Block diagram

–

Figure 2: Configuration diagram (top view)

–

Figure 3: Current and voltage conventions

Inserted following figures:

–

Figure 6: IOUT/ISENSE vs IOUT

–

Figure 7: Maximum current sense ratio drift vs load current

–

Figure 9: Delay response time between rising edge of output current and rising edge of current sense (CS enabled) .

Updated following tables:

–

Table 1: Pin function

–

Table 2: Suggested connections for unused and not connected pins

–

Table 3: Absolute maximum ratings

V

CCPK

, V

ESD

: updated parameter

V

CC_LSC

, -I

GND

: added parameter

Updated E

MAX

parameter

–

Table 4: Thermal data

R thj-case

: added value

–

Table 5: Power section

–

Table 6: Switching (VCC = 13V; Tj = 25°C)

–

Table 7: Current sense (8 V < VCC < 18 V)

Updated dK

1

/K

1, dK values

2

/K

2 and dK

3

/K

3 minimum and maximum

V

SENSEH

, I

SENSEH

: added note

–

Table 8: Open-load detection (8 V < VCC < 18 V)

–

Table 9: Protections

Updated V

DEMAG

and I

LIMH values

–

Table 13: Electrical transient requirements (part 2)

Added Section 2.4: Waveforms

.

Updated Section 2.5: Electrical characteristics curves

Updated Chapter 3: Application information

Updated Chapter 4: Package and PCB thermal data

Updated Figure 39: PowerSSO-36 package dimensions

Updated Disclaimer.

Updated footnote 2 into the

Table 12: Electrical transient requirements (part 1) and Table 13: Electrical transient requirements (part 2) .

DocID13620 Rev 5

VND5E008AY-E

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