STMicroelectronics L6391 Datasheet
Publicité
Publicité
L6391
Features
High voltage rail up to 600 V
dV/dt immunity ± 50 V/nsec in full temperature range
Driver current capability:
– 290 mA source
– 430 mA sink
Switching times 75/35 nsec rise/fall with 1 nF load
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Integrated bootstrap diode
Comparator for fault protections
Smart shutdown function
Adjustable deadtime
Interlocking function
Compact and simplified layout
Bill of material reduction
Effective fault protection
Flexible, easy and fast design
High voltage high and low-side driver
Datasheet
-
production data
Applications
Motor driver for home appliances, factory automation, industrial drives and fans
HID ballasts, power supply units
Description
The L6391 is a high voltage device manufactured with the BCD™ “OFF-LINE” technology. It is a single-chip half-bridge gate driver for N-channel power MOSFET or IGBT.
The high-side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing the microcontroller/DSP.
An integrated comparator is available for protections against overcurrent, overtemperature, etc.
September 2015
This is information on a product in full production.
DocID17892 Rev 3 1/23 www.st.com
Contents
Contents
L6391
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/23 DocID17892 Rev 3
L6391 Block diagram
9&&
+,1
/,1
6'2'
'7
*1'
9
89
'(7(&7,21
Figure 1. Block diagram
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6+,)7(5
6
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DocID17892 Rev 3 3/23
23
Pin connection L6391
Figure 2. Pin connection (top view)
EDGE
DEADTIME
/,1
LIN
6'2'
HIN +,1
9&&
LVG
'7
HVG
1& gate driver outputs OFF
*1'
G
DT
LH
%227
+9*
287
1&
/9*
&3 gate driver outputs OFF
&3
G G
DT
HL
Pin number
Pin name
1 LIN
Type
I
2 SD/OD
(1)
I/O
3
4
HIN
VCC
Table 1. Pin description
I
P
Function
Low-side driver logic input (active low)
Shutdown logic input (active low)/open-drain comparator output
High-side driver logic input (active high)
Lower section supply voltage
$0Y
Not connected 6 NC
10
11
12
13
8 CP-
LVG
(1)
NC
OUT
HVG
(1)
O
P
O
Low-side driver output
Not connected
High-side (floating) common voltage
High-side driver output
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at I sink
= 10 mA), with V
CC
> 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/23 DocID17892 Rev 3
L6391 Truth table
SD
L
H
H
H
H
1. X: don't care.
Table 2. Truth table
Input Output
LIN
X
(1)
L
H
H
L
HIN
X
(1)
L
H
L
H
LVG
L
L
L
H
L
HVG
L
L
L
L
H
DocID17892 Rev 3 5/23
23
Electrical data L6391
4.1 Absolute maximum ratings
Symbol
Table 3. Absolute maximum ratings
Value
Parameter
Min.
V cc
V out
V boot
Output voltage
Bootstrap voltage
V hvg
High-side gate output voltage
V lvg
Low-side gate output voltage
V cp-
V cp+
Comparator negative input voltage
Comparator positive input voltage
V i
V
OD
Logic input voltage
Open-drain voltage dv out
/ dt Allowed output slew rate
P tot
Total power dissipation (T
A
= 25 °C)
T
J
T stg
Junction temperature
Storage temperature
ESD Human body model
-0.3
V boot
- 21
-0.3
V out
- 0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
2
Max.
21
V boot
+ 0.3
620
V boot
+ 0.3
V cc
+ 0.3
V cc
+ 0.3
V cc
+ 0.3
15
15
50
800
150
150
Unit
V
V
V
V
V
V
V
V
V
V/ns mW
°C
°C kV
Table 4. Thermal data
Symbol Parameter
R th(JA)
Thermal resistance junction to ambient
SO-14
120
Unit
°C/W
6/23 DocID17892 Rev 3
L6391
4.3
Electrical data
Recommended operating conditions
Symbol Pin
Table 5. Recommended operating conditions
Parameter Test Min.
Max.
Unit
V cc
V
BO
(1)
V out
4 Supply voltage
14 - 12 Floating supply voltage
12.5
12.4
- 9
(2)
20
20
V
CP-
12 DC output voltage
8
Comparator negative input voltage
V
CP+
[ 2.5 V] V
580
CC
(3)
V
CP+
9
Comparator positive input voltage
V
CP-
[ 2.5 V] V
CC
(3) f sw
T
J
Switching frequency
Junction temperature
HVG, LVG load C
L
= 1 nF
-40
800
125
1. V
BO
= V
BOOT
- V
OUT
.
2. LVG off. V cc
= 12.5 V. Logic is operational if V
BOOT
> 5 V.
3. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation.
V
V
V
V
V kHz
°C
DocID17892 Rev 3 7/23
23
Electrical characteristics L6391
Symbol
Table 6. AC operation electrical characteristics (V
CC
= 15 V; T
J
= +25 °C)
Pin Parameter Test conditions Min. Typ. Max. Unit t t t t on off sd isd t r t f
MT
DT
1 vs. 10
3 vs. 13
High/low-side driver turn-on propagation delay
High/low-side driver turn-off propagation delay
2 vs. 10,
13
Shutdown to high/low-side driver propagation delay
Comparator triggering to high/low-side driver turn-off propagation delay
Delay matching, HS and LS turn-on/off
V out
= 0 V
V boot
= Vcc
C
L
= 1 nF
V i
= 0 to 3.3 V
Measured applying a voltage step from
0 V to 3.3 V to pin CP+; CP- = 0.5 V
5
10,13
Deadtime setting range
Rise time
Fall time
(1)
1. See
2. MDT = | DT
LH
- DT
HL
| (see
).
50
50
50
125 200
125 200
125 200 ns ns ns
200 250 ns
30 ns
R
DT
= 0 , C
L
= 1 nF 0.1 0.18 0.25 µs
R
DT
= 37 k , C
L
= 1 nF, C
DT
= 100 nF 0.48 0.6 0.72 µs
R
DT
= 136 k , C
L
= 1 nF, C
DT
= 100 nF 1.35 1.6 1.85 µs
R
DT
= 260 k , C
L
= 1 nF, C
DT
= 100 nF 2.6 3.0 3.4 µs
R
DT
= 0 , C
L
= 1 nF 80 ns
R
DT
= 37 k , C
L
= 1 nF, C
DT
= 100 nF
R
DT
= 136 k , C
L
= 1 nF, C
DT
= 100 nF
R
DT
= 260 k , C
L
= 1 nF, C
DT
= 100 nF
C
L
= 1 nF
120
250
400
75 120 ns ns ns ns
C
L
= 1 nF 35 70 ns
8/23 DocID17892 Rev 3
L6391 Electrical characteristics
Figure 3. Timing
-*/
U
S
U
G
-7(
U
PO
U
PGG
)*/
U
S
U
G
)7(
U
PO
U
PGG
4%
U
G
-7()7(
U
TE
3.5
3
2.5
2
1.5
1
0.5
0
0
Figure 4. Typical deadtime vs. DT resistor value
Approximated formula for
Rdt calculation (typ.):
50 100 150
Rdt (kOhm)
200 250 300
".
AM16763v1
DocID17892 Rev 3 9/23
23
Electrical characteristics L6391
Symbol
V cc_hys
V cc_thON
V cc_thOFF
Table 7. DC operation electrical characteristics (V
CC
= 15 V; T
J
= + 25 °C)
Pin Parameter
V cc
UV hysteresis
V cc
UV turn-ON threshold
V cc
UV turn-OFF threshold
Test conditions Min.
Typ.
Max. Unit
1.2
11.5
10
1.5
12
10.5
1.8
12.5
11
V
V
V
I
I qccu qcc
4
Undervoltage quiescent supply current
Quiescent current
V cc
= 9.5 V
SD = 5 V; LIN = 5 V;
HIN = GND; R
DT
= 0 ;
CP+ = GND; CP- = 5 V
V cc
= 15 V
SD = 5 V; LIN = 5 V;
HIN = GND; R
DT
= 0 ;
CP+ = GND; CP- = 5 V
100
500
150
1000
A
A
Bootstrapped supply voltage section
(1)
V
BO_hys
V
BO_thON
V
BO_thOFF
V
BO
UV hysteresis
V
BO
UV turn-ON threshold
V
BO
UV turn-OFF threshold
1.2
10.6
9.1
1.5
11.5
10
1.8
12.4
10.9
V
V
V
I
I
QBOU
QBO
14 - 12
Undervoltage V
BO current
V
BO
quiescent
quiescent current
V
BO
= 9 V
SD = 5 V; LIN and
HIN = 5 V; R
DT
= 0 ;
CP+ = GND; CP- = 5 V
V
BO
= 15 V
SD = 5 V; LIN and
HIN = 5 V; R
DT
= 0 ;
CP+ = GND; CP- = 5 V
V hvg
= V out
= V boot
= 600 V
LVG ON
70
200
I
LK
R
DS(on)
Driving buffer section
High voltage leakage current
Bootstrap driver on resistance
(2)
I
I so si
10, 13
120
High/low-side source short-circuit current
High/low-side sink short-circuit current
V
IN
= V ih
(t p
< 10 s) 200 290
V
IN
= V il
(t p
< 10 s) 250 430
110
240
10
A
A
A
W mA mA
Logic inputs
V il
V ih
1, 2, 3
V il_S
1, 3
Low level logic threshold
High level logic threshold voltage
Single input voltage
LIN and HIN connected together and floating
0.8
1.9
1.1
V
2.25
V
0.8
V
10/23 DocID17892 Rev 3
L6391 Electrical characteristics
Table 7. DC operation electrical characteristics (V
CC
= 15 V; T
J
= + 25 °C) (continued)
Symbol Pin Parameter Test conditions Min.
Typ.
Max. Unit
I
HINh
I
HINl
I
LINl
I
LINh
I
SDh
I
SDl
3
1
2
HIN logic “1” input bias current
HIN logic “0” input bias current
LIN logic “0” input bias current
LIN logic “1” input bias current
SD logic “1” input bias current
SD logic “0” input bias current
HIN = 15 V
HIN = 0 V
LIN = 0 V
LIN = 15 V
SD = 15 V
SD = 0 V
1. V
BO =
V
BOOT
- V
OUT
.
2. R where I
is tested in the following way: R
1
is pin 14 current when V
BOOT
= V
= [(V
BOOT1
, I
CC
2
- V
BOOT1
) - (V
BOOT
CC
- V
= V
BOOT2
.
110 175 260 A
1 A
3 6 20
1
A
A
10 40 100 A
1 A
)] / [I
1
(V
CC
,V
BOOT1
) - I
2
(V
CC
,V
BOOT2
)]
Symbol Pin
Table 8. Sense comparator (1) (V
CC
= 15 V, T
J
= +25 °C)
Parameter Test conditions t
V io
I
V ib ol d_comp
8, 9
8, 9
2
Input offset voltage
Input bias current
Open-drain low level output voltage
Comparator delay
V
CP+
= 1 V, V
CP -
= 0.5 V
I od
V
= - 3 mA V
CP+
CP-
= 0.5 V;
= 1 V;
R pull
= 100 k to 5 V on
SD/OD pin; V
CP
- = 0.5 V; voltage step on CP+ = 0 to
3.3 V
SR 2 Slew rate
1. Comparator is disabled when V cc
is in UVLO condition.
C
L
= 180 pF; R pu
= 5 k
Min.
-15
Typ.
90
60
Max.
Unit
15
1 mV
A
0.5
V
130 ns
V/ s
DocID17892 Rev 3 11/23
23
Waveform definitions
Figure 5. Deadtime and interlocking waveform definitions
LIN
HIN
CONTROL SIGNAL EDGE
OVERLAPPED:
INTERLOCKING + DEADTIME
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
G
DT LH
CONTROL SIGNAL EDGE
SYNCHRONOUS (*):
DEADTIME
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH
CONTROL SIGNAL EDGE
NOT OVERLAPPED,
BUT INSIDE THE DEADTIME:
DEADTIME
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL
DT
HL gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
CONTROL SIGNAL EDGE
NOT OVERLAPPED,
OUTSIDE THE DEADTIME:
DIRECT DRIVING
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
DT
HL
L6391
12/23 DocID17892 Rev 3
L6391
7
Smart shutdown function
Smart shutdown function
The L6391 device integrates a comparator committed to the fault sensing function. Both comparator's inputs are available on pins 8 and 9. For example, applying a voltage reference to CP- and connecting the CP+ to an external shunt resistor, a simple overcurrent detection function can be implemented.
The output signal of the comparator is fed to an integrated MOSFET with the open-drain output available on the pin 2, shared with the SD input. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leaving the halfbridge in tristate.
Figure 6. Smart shutdown timing waveforms
CP-
CP+
HIN/LIN
HVG/LVG
SD/OD
PROTECTION open-drain gate
(internal) disable time
Fast shutdown : the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reached the lower input threshold
An approximation of the disable time is given by:
V
BIAS
SHUTDOWN CIRCUIT
FROM/TO
CONTROLLER
R
SD
SD/OD
C
SD
R
ON_OD
R
PD_SD
SMART
SD
LOGIC where:
AM16755v1
DocID17892 Rev 3 13/23
23
Smart shutdown function L6391
In common overcurrent protection architectures, the comparator output is usually connected to the SD input and an RC network is connected to this SD/OD line in order to provide a monostable circuit, which implements a protection time following the fault condition.
Differently from the common fault detection systems, the L6391 smart shutdown architecture allows immediate turn-off of the output gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the current output switch-off. In fact the time delay between the fault and the output turn-off is no longer dependent on the
RC value of the external network connected to the SD/OD pin. In the smart shutdown circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At the same time, the internal logic turns on the open-drain output and holds it on until the SD voltage goes below the SD logic input lower threshold. When such threshold is reached, the open-drain output is turned off, allowing the external pull-up to recharge the capacitor. The driver outputs restart following the input pins as soon as the voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart shutdown system gives the possibility to increase the time constant of the external RC network (that determines the disable time after the fault event) up to very large values without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa.
In some applications, it may be useful to latch the driver in the shutdown condition for an arbitrary time, until the controller decides to reset it to normal operation. This may, for
example, be achieved by a circuit as the one shown in Figure 7
. When the open-drain starts pulling down the SD/OD pin, the external latch turns on and keeps the pin to GND, preventing it from being pulled up again once the SD logic input lower threshold is reached and the internal open-drain turns off. One pin of the controller is used to release the external latch, and one to externally force a shutdown condition and also to read the status of the
SD/OD pin.
Figure 7. Protection latching circuit
HV BUS
VDD
μC
SD_force
VCC
+
VCC
-
+
R1
9*R
R2
R
R3
2*R
C1
HIN
LIN
VCC
L6391
VBOOT
HVG
GND OUT
DT
SD/OD
OPOUT
LVG
CP+
CP-
V
BIAS
C2
SD/OD
C3
SD/OD
VDD
GND
SD_sense
C1: disable time setting capacitor
C2, C3: small noise filtering capacitors AM16756v1
In applications using only one L6391 for the protection of different legs (such as a single-
shunt inverter, for example), the resistor divider, shown in Figure 8
, can be implemented.
This simple network allows the SD pins of the other devices to reach a voltage lower than
L6391 V il
, so that each device can get its low logic level regardless of part to part variations of the thresholds.
14/23 DocID17892 Rev 3
L6391
7
7%%
(/%
Smart shutdown function
Figure 8. SD level shifting circuit
4%@SFTFU
3
3
4%@GPSDFTFOTF
7
3
3
7$$
)*/
-*/ -
7#005
)7(
7$$
065
(/%
-7(
%5
4%0%
01065
$1
$1
5PPUIFSESJWFSEFWJDFT
".W
DocID17892 Rev 3 15/23
23
Typical application diagram
8 Typical application diagram
Figure 9. Application diagram
L6391
16/23 DocID17892 Rev 3
AM02458v1
L6391 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is usually accomplished by a high voltage fast recovery diode (
). In the L6391 device a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with diode in series, as shown in
Figure 11 . An internal charge pump ( Figure 11 ) provides the DMOS driving voltage.
C
BOOT
selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent capacitor. This capacitor C
EXT
is related to the MOS total gate charge:
Equation 1
C
EXT
=
Q
V gate
The ratio between the capacitors C
EXT
It has to be:
and C
BOOT
is proportional to the cyclical voltage loss.
Equation 2
C
BOOT
>>>C
EXT if Q gate
is 30 nC and V gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop is 300 mV.
If HVG has to be supplied for a long time, the C
BOOT the leakage and quiescent losses.
selection has also to take into account
HVG steady-state consumption is lower than 240 supply C
EXT
A, so if HVG T
ON
is 5 ms, C
BOOT
has to with 1.2 C. This charge on a 1 F capacitor means a voltage drop of 1.2 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T charge
) of the C
BOOT
is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DS(on)
(typical value:
120 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to take into account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
V drop
=
I ch arg e
R
DS on
V drop
=
T
Q ch arg e
R
DS on where Q gate
is the gate charge of the external power MOS, the bootstrap DMOS and T charge
R
DS(on)
is the on resistance of
is the charging time of the bootstrap capacitor.
DocID17892 Rev 3 17/23
23
Bootstrap driver L6391
For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the T charge
is 5 s. In fact:
Equation 4
V drop
=
30nC
5 s
120 0.7V
V drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used.
Figure 10. Bootstrap driver with high voltage fast recovery diode
D
BOOT
V
CC
BOOT
H.V.
HVG
C
BOOT
OUT
TO LOAD
LVG
Figure 11. Bootstrap driver with internal charge pump
V
CC
BOOT
H.V.
HVG
C
BOOT
OUT
TO LOAD
LVG
18/23 DocID17892 Rev 3
L6391 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
SO-14 package information
Figure 12. SO-14 package outline
DocID17892 Rev 3
0016019_E
19/23
23
Package information L6391
Table 9. SO-14 package mechanical data
Dimensions (mm )
Symbol
A 1.35
A1 0.10
A2 1.10
B 0.33
C 0.19
D 8.55
E 3.80
Min. Typ. Max.
1.75
0.25
1.65
0.51
0.25
8.75
4.00
e 1.27
H 5.80
h 0.25
L 0.40
K 0 e ddd
0.40
6.20
0.50
1.27
8
0.10
Figure 13. SO-14 footprint
".
20/23 DocID17892 Rev 3
L6391 Order codes
Order code
L6391D
L6391DTR
Table 10. Order codes
Package
SO-14
SO-14
Packaging
Tube
Tape and reel
DocID17892 Rev 3 21/23
23
Revision history L6391
Date
14-Dec-2010
10-May-2013
11-Sep-2015
Revision
Table 11. Document revision history
Changes
1
2
3
First release.
Added HBM parameter to Table 3
.
Added I
QBO
.
Changed V il and V ih min. and max. values in
Added note to
.
Updated
Updated SO-14 mechanical data.
Updated DIP-14 mechanical data.
Removed DIP-14 package from the entire document.
Updated
th(JA)
value).
Moved Table 10 on page 21 (moved from page 1 to page 21, updated
titles.
Updated
Table 3 on page 6 (updated ESD parameter and value).
Updated note
below Table 7 on page 10 (minor
modifications, replaced V
CBOOTx by V
BOOTx
).
Added
Updated cross-references throughout document.
Minor modifications throughout document.
22/23 DocID17892 Rev 3
L6391
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© 2015 STMicroelectronics – All rights reserved
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