STMicroelectronics L6390 Datasheet
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L6390
SO-16
Features
High voltage rail up to 600 V
dV/dt immunity ± 50 V/nsec in full temperature range
Driver current capability: 290 mA source, 430 mA sink
Switching times 75/35 nsec rise/fall with 1 nF load
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Integrated bootstrap diode
Operational amplifier for advanced current sensing
Comparator for fast fault protection
Smart shutdown function
Adjustable deadtime
Interlocking function
Compact and simplified layout
Bill of material reduction
Applications
Home appliances
Motor drivers
– DC, AC, PMDC and PMAC motors
– FOC and sensorless BEMF detection systems
Industrial applications and drives
Induction heating
HVAC
Factory automation
Power supply systems
High voltage high/low-side driver
Datasheet
-
production data
Description
The L6390 is a full featured high voltage device manufactured with the BCD
™
“offline” technology. It is a single-chip half-bridge gate driver for N-channel power MOSFETs or IGBTs.
The high-side (floating) section is able to work with voltage rail up to 600 V.
Both device outputs can sink and source 430 mA and 290 mA respectively. Prevention from cross conduction is ensured by interlocking and programmable deadtime functions.
The device has dedicated input pins for each output and a shutdown pin. The logic inputs are
CMOS/TTL compatible down to 3.3 V for easy interfacing with control devices. Matched delays between low-side and high-side sections guarantee no cycle distortion and allow high frequency operation.
The L6390 embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control or for sensorless BEMF detection. A comparator featuring advanced smartSD function is also integrated in the device, ensuring fast and effective protection against fault events like overcurrent, overtemperature, etc.
The L6390 device features also UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions.
The integrated bootstrap diode as well as all of the integrated features of this IC make the application PCB design easier, more compact and simple thus reducing the overall bill of material.
The device is available in an SO-16 tube and tape and reel packaging options.
March 2018
This is information on a product in full production.
DocID14493 Rev 11 1/25 www.st.com
Contents
Contents
L6390
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing and waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/25 DocID14493 Rev 11
L6390 Block diagram
Figure 1. Block diagram
VCC
HIN
4
3
LIN
1
SD/OD
GND
DT
OPOUT
2
8
5
7
UV
DETECTION
5V
BOOTSTRAP DRIVER
FLOATING STRUCTURE from LVG
UV
DETECTION
LEVEL
SHIFTER
S
R
LOGIC
SHOOT
THROUGH
PREVENTION
SMART
SD
SD
LATCH
COMPARATOR
5V
+
-
HVG
DRIVER
16
15
BOOT
HVG
14
OUT
VCC
LVG
DRIVER
LVG
11
10
CP+
VREF
+
DEAD
TIME
OPAMP
VCC
+
-
9
6
OP+
OP-
DocID14493 Rev 11 3/25
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Pin connection L6390
Figure 2. Pin connection (top view)
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Pin no.
Pin name
Table 1. Pin description
Type Function
1
2
10
11
12, 13
14
15
16
8
9
6
7
3
4
5
LIN
SD/OD
(1)
I
I/O
HIN
VCC
DT
OP-
OPOUT
GND P
OP+ I
CP+
LVG
(1)
I
O
I
O
NC
OUT
HVG
(1)
BOOT
I
P
I
P
O
P
Low-side driver logic input (active low)
Shutdown logic input (active low)/open drain
(comparator output)
High-side driver logic input (active high)
Lower section supply voltage
Deadtime setting
Op amp inverting input
Op amp output
Ground
Op amp non-inverting input
Comparator input
Low-side driver output
Not connected
High-side (floating) common voltage
High-side driver output
Bootstrap supply voltage
1. The circuit provides less than 1 V on the LVG and HVG pins (at I sink
= 10 mA), with V
CC
> 3 V. This allows the omission of the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/25 DocID14493 Rev 11
L6390 Electrical data
3.1 Absolute maximum ratings
Symbol
Table 2. Absolute maximum ratings
Value
Parameter
Min.
V
CC
V
OUT
V
BOOT
V hvg
V lvg
V
OP+
V
OP-
V
CP+
V i
Supply voltage
Output voltage
Bootstrap voltage
High-side gate output voltage
Low-side gate output voltage
Op amp non-inverting input
Op amp inverting input
Comparator input voltage
Logic input voltage
V od
Open drain voltage dV
OUT
/dt Allowed output slew rate
P tot
T
J
Total power dissipation (T
Junction temperature
A
= 25 °C)
T stg
Storage temperature
ESD Human body model
- 0.3
V
BOOT
- 21
- 0.3
V
OUT
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
-
-
-
-50
2
Max.
21
V
BOOT
+ 0.3
620
V
BOOT
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
15
15
50
800
150
150
Unit
V
V
V/ns mW
°C
°C kV
V
V
V
V
V
V
V
V
Table 3. Thermal data
Symbol Parameter
R th(JA)
Thermal resistance junction to ambient
SO-16
120
Unit
°C/W
DocID14493 Rev 11 5/25
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Electrical data
3.3
L6390
Recommended operating conditions
Symbol Pin
Table 4. Recommended operating conditions
Parameter Test condition Min.
Max.
Unit
V
CC
V
BO
(1)
V
OUT f sw
T
J
4 Supply voltage
16 - 14 Floating supply voltage
14
-
-
DC output voltage
Switching frequency
Junction temperature -
-
-
-
HVG, LVG load C
L
= 1 nF
12.5
12.4
- 9
-
(2)
-40
20
20
580
800
125
1. V
BO
= V
BOOT
- V
OUT
.
2. LVG off. V
CC
= 12.5 V. Logic is operational if V
BOOT
> 5 V. Refer to the AN2738 for more details.
V
V
V kHz
°C
6/25 DocID14493 Rev 11
L6390 Electrical characteristics
Symbol
Table 5. AC operation electrical characteristics (V
CC
= 15 V; T
J
= +25 °C)
Pin Parameter Test condition Min.
Typ. Max. Unit t t t t on off sd isd
MT
DT
MDT t r t f
1 vs. 11
3 vs. 15
2 vs. 11, 15
High/low-side driver turn-on propagation delay
High/low-side driver turn-off propagation delay
Shutdown to high/low-side driver propagation delay
V
OUT
= 0 V
V
BOOT
= V
CC
C
L
= 1 nF
V i
= 0 to 3.3 V
See
-
-
5
-
11, 15
Comparator triggering to high/low-side driver turn-off propagation delay
Delay matching, HS and LS turn-on/off
-
Measured applying a voltage step from 0 V to 3.3 V to pin CP+.
Deadtime setting range
Matching deadtime
Rise time
Fall time
(2)
1. See
2. MDT = | DT
LH
- DT
HL
| see
(1)
R
DT
= 0, C
L
= 1 nF
R
DT
= 37 k , C
L
= 1 nF,
C
DT
= 100 nF
R
DT
= 136 k , C
L
= 1 nF,
C
DT
= 100 nF
R
DT
= 260 k , C
L
= 1 nF,
C
DT
= 100 nF
R
DT
= 0, C
L
= 1 nF
R
DT
= 37 k , C
L
= 1 nF,
C
DT
= 100 nF
R
DT
= 136 k , C
L
= 1 nF,
C
DT
= 100 nF
R
DT
= 260 k , C
L
= 1 nF,
C
DT
= 100 nF
C
L
= 1 nF
C
L
= 1 nF
50
50
50
50
0.1
ns ns ns ns ns
s
0.48
0.6
0.72
s
1.35
1.6
1.85
s
2.6
-
-
-
-
-
-
-
125
125
125
200
-
0.18
3.0
-
-
-
-
75
35
200
200
200
250
30
0.25
3.4
80
120
250
400
120
70
s ns ns ns ns ns ns
DocID14493 Rev 11 7/25
25
Electrical characteristics
Figure 3. Typical deadtime vs. DT resistor value
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8/25 DocID14493 Rev 11
L6390 Electrical characteristics
Symbol
Table 6. DC operation electrical characteristics (V
CC
= 15 V; T
J
= + 25 °C)
Pin Parameter Test condition Min.
Typ.
Max.
Unit
Low supply voltage section
V
CC_hys
V
CC_thON
V
CC_thOFF
I
QCCU
4
V
CC
UV hysteresis
Undervoltage quiescent supply current
-
V
CC
UV turn-ON threshold -
V
CC
UV turn-OFF threshold -
V
CC
= 10 V
SD = 5 V; LIN = 5 V;
HIN = GND;
R
DT
= 0 ;
CP+ = OP+ = GND;
OP- = 5 V
I
QCC
Quiescent current
V ref
Internal reference voltage
Bootstrapped supply voltage section
(1)
-
V
CC
= 15 V
SD = 5 V; LIN = 5 V;
HIN = GND;
R
DT
= 0 ;
CP+ = OP+ = GND;
OP- = 5 V
V
BO_hys
V
BO_thON
V
BO_thOFF
I
R
I
QBOU
QBO
I
LK
DS(on)
16
-
-
V
BO
UV hysteresis
V
BO
UV turn-ON threshold -
-
V
BO
UV turn-OFF threshold -
Undervoltage V
BO quiescent current
V
BO
= 9 V
SD = 5 V; LIN and
HIN = 5 V;
R
DT
= 0 ;
CP+ = OP+ = GND;
OP- = 5 V
V
BO
quiescent current
V
BO
= 15 V
SD = 5 V; LIN and
HIN = 5 V;
R
DT
= 0 ;
CP+ = OP+ = GND;
OP- = 5 V
High voltage leakage current
Bootstrap driver onresistance
(2)
V hvg
= V
LVG ON
OUT
= V
BOOT
= 600 V
1200 1500 1800 mV
11.5
10
12
10.5
12.5
11
V
V
90
300
500
A
A mV
1200 1500 1800 mV
11.1
9.8
11.5
10
12.1
10.6
V
V
30
30
-
-
120
720
540
70
150
-
120
150
1000
580
110
240
10
-
A
A
A
DocID14493 Rev 11 9/25
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Electrical characteristics L6390
Table 6. DC operation electrical characteristics (V
CC
= 15 V; T
J
= + 25 °C) (continued)
Symbol Pin Parameter Test condition Min.
Typ.
Max.
Unit
Driving buffers section
I
I so si
11, 15
High/low-side source shortcircuit current
High/low-side sink shortcircuit current
Logic inputs
V
V
IN
IN
= V
= V ih il
(t
(t p p
< 10 s) 200
< 10 s) 250
290
430 -
mA mA
V
V il ih
1, 2, 3
Low level logic threshold voltage
High level logic threshold voltage
-
0.8
1.9
-
1.1
2.25
V
V
V il_S
1, 3
Single input voltage
LIN and HIN connected together and floating
0.8
V
I
I
HINh
HINl
3
HIN logic “1” input bias current
HIN logic “0” input bias current
HIN = 15 V
HIN = 0 V
110
-
175
-
260
1
A
A
I
I
LINl
LINh
1
LIN logic “0” input bias current
LIN logic “1” input bias current
LIN = 0 V
LIN = 15 V
3
-
6
-
20
1
A
A
I
SDh
SD logic “1” input bias current
SD = 15 V 10 40 100 A
I
SDl
2
SD logic “0” input bias current
SD = 0 V 1 A
R
PD_SD
2 SD input pull-down resistor SD = 15 V 150 375 1500 k
1. V
BO =
V
BOOT
- V
OUT
.
2. R
I
1
DSON
is tested in the following way: R
is the pin 16 current when V
BOOT
= V
= [(V
BOOT1
, I
2
- V
when V
) - (V
BOOT
= V
CC
- V
BOOT2
.
BOOT2
)] / [I
1
(V
CC
,V
BOOT1
) - I
2
(V
CC
,V
BOOT2
)] where
10/25 DocID14493 Rev 11
L6390 Electrical characteristics
Symbol Pin
Table 7. Op amp characteristics (1) (V
CC
= 15 V, T
J
= +25 °C)
Parameter Test condition Min.
Typ.
Max.
Unit
V io
I io
I ib
V icm
V
OPOUT
I o
SR
GBWP
A vd
SVR
CMRR
6, 9
7
-
-
-
-
-
Input offset voltage
Input offset current
Input bias current
(2)
V
V ic ic
= 0 V, V
= 0 V, V o o
= 7.5 V
= 7.5 V
Input common mode voltage range -
Output voltage swing OPOUT = OP-; no load
Output short-circuit current
Slew rate
Source, V id
= +1; V o
= 0 V
Sink,V id
= -1; V o
= V
CC
V i
= 1
4 V; C unity gain
L
= 100 pF;
Gain bandwidth product
Large signal voltage gain
V o
= 7.5 V
R
L
= 2 k
Supply voltage rejection ratio vs. V
CC
Common mode rejection ratio
-
1. The operational amplifier is disabled when V
CC
is in UVLO condition.
2. Input bias current flows out the IC leads.
-
-
-
0
0.07
16
50
2.5
8
70
60
55
12
85
75
-
30
80
-
4
100
-
3.8
70
V
CC
-4
V
CC
-4
-
-
-
-
-
6
40
200
-
mV nA nA
V
V mA mA
V/ s
MHz dB dB dB
Symbol
Table 8. Sense comparator characteristics
(1)
(V
CC
= 15 V, T
J
= +25 °C)
Pin Parameter Test condition Min.
Typ.
Max.
Unit
1 A I ib
10 Input bias current V
CP+
= 1 V
V
OL
2
Open drain low level output voltage
I
OD
= - 3 mA
R
ON_OD
2 Open drain ON resistor t d_comp
SR
-
2
Comparator delay
Slew rate
SD/OD pulled to 5 V through 100 k resistor
C
L
= 180 pF; R pu
= 5 k
1. The comparator is disabled when V
CC
is in UVLO condition.
-
-
-
-
125
90
60
0.5
167
130
-
V
ns
V/ s
DocID14493 Rev 11 11/25
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Timing and waveforms definitions
5 Timing and waveforms definitions
Figure 4. Propagation delay timing definition
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Figure 5. Dead time and interlocking timing definitions
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12/25 DocID14493 Rev 11
L6390 Timing and waveforms definitions
Figure 6. Deadtime and interlocking waveforms definition
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DocID14493 Rev 11 13/25
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Input logic L6390
Input logic is provided with an interlocking circuitry which avoids cross-conduction in case of wrong signals on LIN and HIN tries to turn-on both LVG and HVG outputs at the same times.
In addition, to prevent cross conduction of the external MOSFETs, after each output is turned off, the other output cannot be turned on before a certain amount of time (DT) (see
Figure 5: Dead time and interlocking timing definitions
).
SD
L
H
H
H
H
1. X: don't care.
Table 9. Truth table
Input Output
LIN
X
(1)
H
L
L
H
HIN
X
(1)
L
H
L
H
LVG
L
L
L
H
L
HVG
L
L
L
L
H
14/25 DocID14493 Rev 11
L6390
7
Smart shutdown function
Smart shutdown function
The L6390 device integrates a comparator committed to the fault sensing function. The comparator has an internal voltage reference V ref
connected to the inverting input, while the non-inverting input is available on the pin 10. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on the pin 2, shared with the SD input. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leaving the half-bridge in tristate.
Figure 7. Smart shutdown timing waveforms
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".W
15/25
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Smart shutdown function L6390
In common overcurrent protection architectures the comparator output is usually connected to the SD input and an RC network is connected to this SD/OD line in order to provide a monostable circuit, which implements a protection time that follows the fault condition.
Differently from the common fault detection systems, the L6390 smart shutdown architecture allows immediate turn-off of the outputs of the gate driver in the case of fault, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is no longer dependent on the value of the external RC network connected to the SD/OD pin. In the smart shutdown circuitry the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At the same time the internal logic turns on the open drain output and holds it on until the SD voltage goes below the SD logic input lower threshold. When such threshold is reached, the open drain output is turned off, allowing the external pull-up to recharge the capacitor. The driver outputs restart following the input pins as soon as the voltage at the SD/OD pin reaches the higher threshold of the
SD logic input. The smart shutdown system provides the possibility to increase the time constant of the external RC network (that determines the disable time after the fault event) up to very large values without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa.
In some applications it may be useful to latch the driver in the shutdown condition for an arbitrary time, until the controller decides to reset it to normal operation. This may, for example, be achieved with a circuit similar to the one shown in
. When the open drain starts pulling down the SD/OD pin, the external latch turns on and keeps the pin to
GND, preventing it from being pulled up again once the SD logic input lower threshold is reached and the internal open drain turns off. One pin of the controller is used to release the external latch, and one to externally force a shutdown condition and also to read the status of the SD/OD pin.
Figure 8. Protection latching example circuit
3.3 / 5 V
VDD
GND
µC
SD_reset
R3
2.2 K
Ω
R4
20 K Ω
3.3 / 5 V
R1
20 K Ω
+
VCC
-
+
R2
1.5 K Ω
SD_force/sense
HIN
LIN
VCC
GND
DT
HVG
OUT
LVG
L6390
CP+
SD/OD
OPOUT
VBOOT
OP+
OP-
To other driver/devices
AM12949v1
In applications using only one L6390 for the protection of several different legs (such as a single-shunt inverter, for example) it may be useful to implement the resistor divider shown in
Figure 9 . This simple network allows the pushing of the SD pins of the other devices to
a voltage lower than L6390 V il
, so that each device can reach its low logic level regardless of part-to-part variations of the thresholds.
16/25 DocID14493 Rev 11
L6390
VDD
VDD
GND
µC
Smart shutdown function
Figure 9. SD level shifting example circuit
HV BUS
SD_force
SD_sense
VCC
+
VCC +
-
R1
9*R
R2
R
R3
2*R
C1
HIN
LIN
VCC
VBOOT
L6390
HVG
GND OUT
DT
SD/OD
OPOUT
LVG
CP+
OP+
OP-
C2
SD/OD
C3
SD/OD
C1: disable time setting capacitor
C2, C3: small noise filtering capacitors
AM12948v1
DocID14493 Rev 11 17/25
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Typical application diagram
8 Typical application diagram
L6390
Figure 10. Application diagram
V
CC
+
VCC 4
FROM CONTROLLER HIN 3
FROM CONTROLLER
V
BIAS
FROM/TO
CONTROLLER
LIN
SD/OD
1
2
TO ADC
GND 8
DT 5
OPOUT
7
5V
UV
DETECTION
BOOTSTRAP DRIVER
FLOATING STRUCTURE from LVG
UV
DETECTION
LEVEL
SHIFTER
S
R
LOGIC
SHOOT
THROUGH
PREVENTION
SMART
SD
SD
LATCH
COMPARATOR
5V
+
-
16
BOOT
HVG
DRIVER
15 HVG
14 OUT
V
CC LVG
DRIVER
11
LVG
V
REF
10 CP+
+
V
BIAS
DEAD
TIME
OPAMP
VCC
+
-
9 OP+
OP-
6
H.V.
Cboot
TO LOAD
18/25 DocID14493 Rev 11
L6390 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (
Figure 11 .a). In the L6390 device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
.b. An internal charge pump (
Figure 11 .b) provides the DMOS driving
voltage.
C
BOOT
selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent capacitor. This capacitor C
EXT
is related to the MOS total gate charge:
Equation 1
C
EXT
=
Q
V gate
The ratio between the capacitors C
EXT
It must be:
and C
BOOT
is proportional to the cyclical voltage loss.
Equation 2
C
BOOT
>>> C
EXT
E.g.: if Q gate
300 mV.
is 30 nC and V gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop would be
If HVG must be supplied for a long time, the C
BOOT quiescent losses into account.
selection must also take the leakage and
E.g.: HVG steady-state consumption is lower than 240 A, so if HVG T must supply 1.2 C to C
EXT
ON
is 5 ms, C
BOOT
. This charge on a 1 F capacitor means a voltage drop of 1.2 V.
The internal bootstrap driver offers important advantages: the external fast recovery diode can be avoided (it usually has a high leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and, at the same time, the
LVG is on. The charging time (T charge
) of the C
BOOT
is the time in which both conditions are fulfilled and it must be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DSon
(typical value:
120 ). This drop can be neglected at low switching frequency, but it should be taken into account when operating at high switching frequency.
DocID14493 Rev 11 19/25
25
Bootstrap driver
7$$
L6390
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
V drop
=
I ch arg e
R dson
V drop
=
T
Q ch arg e
R dson where Q gate is the gate charge of the external power MOSFET, R dson the bootstrap DMOS and T charge
is the on-resistance of
is the charging time of the bootstrap capacitor.
For example: using a power MOSFET with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the T charge
is 5 s. In fact:
Equation 4
V drop
=
30nC
5 s
120 0.7V
V drop
should be taken into account when the voltage drop on C
BOOT
is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used.
Figure 11. Bootstrap driver
%#005
#005
)7
7$$
#005
)7
)7( )7(
065
$ #005
50-0"%
065
$ #005
50-0"%
-7( -7(
B C
%*/7
20/25 DocID14493 Rev 11
L6390 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
10.1 SO-16 package informatio n
Figure 12. SO-16 narrow package outline
DocID14493 Rev 11
40
21/25
25
Package information
Symbol h
L
E1 e k ccc
D
E b c
A
A1
A2
L6390
Table 10. SO-16 narrow package mechanical data
Dimensions (mm)
Min. Typ. Max.
3.80
-
0.25
0.40
0
-
-
0.10
1.25
0.31
0.17
9.80
5.80
9.90
6.00
3.90
1.27
-
-
-
-
-
-
-
-
-
1.75
0.25
-
0.51
0.25
10.00
6.20
4.00
-
0.50
1.27
8°
0.10
Figure 13. SO-16 narrow footprint
22/25 DocID14493 Rev 11
L6390 Order codes
Order code
L6390D
L6390DTR
Table 11. Order codes
Package
SO-16
SO-16
Packaging
Tube
Tape and reel
DocID14493 Rev 11 23/25
25
Revision history L6390
Date
11-Sep-2015
07-Apr-2017
21-Mar-2018
Revision
Table 12. Document revision history
Changes
9
10
11
Removed DIP-16 package from the whole document.
Updated Table 3 on page 6 (added ESD parameter and value).
Updated Table 4 on page 6 (updated R th(JA)
value).
Updated note 1.
and 2.
below Table 7 on page 10 (minor modifications, replaced V
CBOOTx by V
BOOTx
).
Minor modifications throughout document.
Updated Table 5 on page 7 (updated cross reference to Figure 4 on page 12 instead of removed Figure 3. Timing ).
Updated Table 6 on page 9 (added R
PD_SD
(added R
ON_OD
).
) and Table 8 on page 11
Updated Section 5 on page 12 (updated title, added Figure 4 and
Figure 5 ).
Added Section 6 on page 14 (and moved Table 9: Truth table to this section).
Updated Figure 11 on page 20 and Figure 12 on page 21 (replaced by new figure).
Minor modifications throughout document.
Updated Figure of SO-16 package on page 1 and Figure 2: Pin connection (top view) on page 4 .
Updated
Table 5 on page 7 (updated DT and MDT test conditions).
Updated note
.
Updated
Minor modifications throughout document.
24/25 DocID14493 Rev 11
L6390
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DocID14493 Rev 11 25/25
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