STMicroelectronics STM32F313RC Datasheet
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STM32F313xx
ARM™Cortex-M4 32b MCU+FPU, up to 256KB Flash+48KB SRAM
4 ADCs, 2 DAC ch., 7 comp., 4 PGA, timers, 1.8 V operation
Datasheet
-
production data
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
Features
• Up to four operational amplifiers that can be used in PGA mode, all terminal accessible with analog supply from 2.4 to 3.6 V
• Up to 23 capacitive sensing channels supporting touchkey, linear and rotary touch sensors
• Core: ARM® 32-bit Cortex™-M4 with FPU
CPU (72 MHz max), single-cycle multiplication
• Up to 13 timers
– One 32-bit timer and two 16-bit timers with up to 4 IC/OC/PWM or pulse counter and and HW division, DSP instruction with FPU quadrature (incremental) encoder input
(floating-point unit), MPU (memory protection
– Up to two 16-bit 6-channel advancedunit) and 90 DMIPS (from control timers, with up to 6 PWM channels, CCM)/1.25 DMIPS/MHz (Dhrystone 2.1)
• Operating conditions:
– VDD: 1.8V +/- 8% deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1
OCN/PWM, deadtime generation and
– VDDA voltage range: 1.65 to 3.6 V
• Memories
– 128 to 256 Kbytes of Flash memory emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM, deadtime generation and emergency stop
– Up to 40 Kbytes of SRAM on data bus with
– 2 watchdog timers (independent, window)
HW parity check
– SysTick timer: 24-bit downcounter
– 8 Kbytes of SRAM on instruction bus with
– Up to two 16-bit basic timers to drive the
HW parity check (CCM)
DAC
• CRC calculation unit
• Reset and supply management
– Low power modes: Sleep and Stop
• Calendar RTC with Alarm, periodic wakeup from Stop
• Clock management
– 4 to 32 MHz crystal oscillator
• Communication interfaces
– CAN interface (2.0B Active)
– Two I2C Fast mode plus (1 Mbit/s) with 20
– 32 kHz oscillator for RTC with calibration mA current sink, SMBus/PMBus, wakeup
– Internal 8 MHz RC with x 16 PLL option
– Internal 40 kHz oscillator
• Up to four ADC 0.20 µS (up to 38 channels) with selectable resolution of 12/10/8/6 bits, 0 to from STOP
• Up to 86 fast I/Os
– All mappable on external interrupt vectors
Obsolete Product(s) - Obsolete Product(s)
• 12-channel DMA controller
– Up to five USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)
– Up to three SPIs, two with multiplexed I2S interface, 4 to 16 programmable bit frame
– Infrared Transmitter
• Cortex-M4 with FPU ETM, Serial wire debug,
JTAG
3.6 V conversion range, separate analog
• 96-bit unique ID supply from 1.8 to 3.6 V
• Up to two 12-bit DAC channels with analog supply from 2.4 to 3.6 V
Table 1. Device summary
Reference Part number
• Seven fast rail-to-rail analog comparators with analog supply from 1.65 to 3.6 V STM32F313xx STM32F313CC, STM32F313RC, STM32F313VC
April 2013
This is information on a product in full production.
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1
Contents
Contents
2/124
STM32F31xx
Cortex™-M
4
with FPU core with embedded Flash and SRAM . . . 12
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
OPAMP reference voltage (VOPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 21
Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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STM32F31xx Contents
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22
Inter-integrated circuit interface (I 2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Universal synchronous/asynchronous receiver transmitter (USART) . . . 24
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 24
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 24
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 56
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Contents
STM32F31xx
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 120
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List of tables STM32F31xx
List of tables
C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Capacitive sensing GPIOs available on STM32F313xx devices . . . . . . . . . . . . . . . . . . . . 27
No. of capacitive sensing channels available on
Table 19.
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical and maximum current consumption from V
DD
Typical and maximum current consumption from the V
DDA
at V
DD
= 1.94 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
supply
supply . . . . . . . . . . . . . . . . . . 59
consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical current consumption in Run mode, code with data processing running from Flash 61
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 62
Obsolete Product(s) - Obsolete Product(s)
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of tables STM32F31xx
2 S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 113
LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 115
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 117
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List of figures STM32F31xx
List of figures
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - master mode
2
2
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
S slave timing diagram (Philips protocol)
(1)
S master timing diagram (Philips protocol)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 113
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Introduction
1 Introduction
STM32F31xx
This datasheet provides the ordering information and mechanical device characteristics of the STM32F31x microcontrollers.
This STM32F31x datasheet should be read in conjunction with the STM32F31x reference manual. The reference manual is available from the STMicroelectronics website www.st.com.
For information on the Cortex™-M4 with FPU core please refer to:
• Cortex™-M4 with FPU Technical Reference Manual , available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.cortexm.m4/ index.html
• STM32F3xxx and STM32F4xxx Cortex-M4 programming manual (PM0214) available from the www.st.com website at the following address: http://www.st.com/internet/com/TECHNICAL_RESOURCES/
TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/DM00046982.pdf
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STM32F31xx
2 Description
Description
The STM32F313xx family is based on the high-performance ARM ® Cortex™-M4 with FPU
32-bit RISC core operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash memory, up to 48 Kbytes of SRAM) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
The devices offer up to four fast 12-bit ADCs (5 Msps), up to seven comparators, up to four operational amplifiers, up to two DAC channels, a low-power RTC, up to five generalpurpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to two I 2 Cs, up to three SPIs (two SPIs are with multiplexed full-duplex I2Ss on STM32F313xx devices), three USARTs, up to two UARTs and CAN. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.
The STM32F313xx family operates in the -40 to +85 °C and -40 to +105 °C temperature ranges. A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F313xx family offers devices in three packages ranging from 48 pins to 100 pins.
The set of included peripherals changes with the device chosen.
Obsolete Product(s) - Obsolete Product(s)
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Description STM32F31xx
Table 2. STM32F31x family device features and peripheral counts
Peripheral
STM32F
313Cx
STM32F
313Rx
STM32F
313Vx
Flash (Kbytes)
SRAM (Kbytes) on data bus
SRAM (Kbytes) on instruction bus
(CCM: core coupled memory)
Advanced control
Timers
General purpose
128
32
256
40
128
32
8
256
40
2 (16-bit)
128
32
256
40
Comm. interfaces
GPIOs
DMA channels
12-bit ADCs
12-bit DAC channels
Analog comparator
Operational amplifiers
CPU frequency
Basic
SPI(I2S)
(1)
I 2 C
USART
UART
CAN
Normal
I/Os
(TC, TTa)
5 volts
Tolerant
I/Os
(FT, FTf)
19
17
5 (16-bit)
1 (32-bit)
2 (16-bit)
3(2)
2
3
2
1
26
25
12
4
2
7
4
72 MHz
44
42
Operating voltage V
DD
= 1.8 V +/- 8%, V
DDA
= 1.65 V to 3.6 V
Operating temperature
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Obsolete Product(s) - Obsolete Product(s)
Packages LQFP48 LQFP64 LQFP100
1. In 128K and 256K Flash STM32F313xx devices the SPI interfaces can work in an exclusive way in either the SPI mode or the I 2 S audio mode.
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STM32F31xx Description
TRADECLK
TRACED[0-3] as AF
JTRST
JTDI
JTCK/SWCLK
JTMS/SWDAT
JTDO
As AF
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[7:0]
XX Groups of
4 channels as AF
V
REF+
V
REF-
XX AF
2 Channels,1 Comp
Channel, BRK as AF
1 Channel, 1 Comp
Channel, BRK as AF
1 Channel, 1 Comp
Channel, BRK as AF
4 Channels,
4 Comp channels,
ETR, BRK as AF
4 Channels,
4 Comp channels,
ETR, BRK as AF
MOSI, MISO,
SCK, NSS as AF
RX, TX, CTS, RTS,
SmartCard as AF
12-bit ADC3
12-bit ADC4
IF
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
Figure 1. STM32F313xx block diagram
TPIU
SWJTAG
ETM
Trace/Trig
MPU/FPU
Cortex M4 CPU
F max
: 72 MHz
Ibus
Dbus
System
NVIC
GP DMA1
7 channels
GP DMA2
5 channels
Temp. sensor
12-bit ADC1
12-bit ADC2
IF
V
DD18
Power
@V
DDIO
FLASH 256 KB
64 bits
CCM RAM
8KB
SRAM
40 KB
Reset
@V
DDA
RC HS 8MHz
RC LS
PLL
Supply
Supervision
@V
DDA
@V
DDIO
XTAL OSC
4 -32 MHz
Ind. WDG32K
Reset & clock control
AHBPCLK
APBP1CLK
APBP2CLK
HCLK
FCLK
USARTCLK
I2CCLK
ADC SAR
1/2/3/4 CLK
CRC
RTC
AWU
@VSW
XTAL 32kHz
Backup
Reg
(64Byte)
Backup interface
TIMER2
(32-bit/PWM)
TIMER 3
TIMER 4
Touch Sensing
Controller
EXT.IT
WKUP
AHB2
APB2
AHB2
APB1
WinWATCHDOG
SPI2/I2S
SPI3/I2S
USART2
USART3
UART4
UART5
I2C1
I2C2 bx CAN &
512B SRAM
TIMER 15
TIMER 16
TIMER 17
TIMER 8 / PWM
SPI1
USART1
TIMER6
TIMER7
SYSCFG CTL
@V
DDA
GP Comparator...
GP Comparator 1
IF 12bit DAC1
@V
DDA
OpAmp1
OpAmp2
OpAmp3
OpAmp4
@V
DDA
V
DDIO
= 1.8 +/- 8%
V
SS
NRESET
V
DDA
V
SSA
NPOR
OSC_IN
OSC_OUT
V
DD
OSC32_IN
OSC32_OUT
ANTI-TAMP
DAC1_CH1 as AF
DAC1_CH2 as AF
INxx / OUTxx
INxx / OUTxx
INxx / OUTxx
INxx / OUTxx
4 Channels, ETR as AF
4 Channels, ETR as AF
4 Channels, ETR as AF
MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF
MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF
RX, TX, CTS, RTS, as AF
RX, TX, CTS, RTS, as AF
RX, TX as AF
RX, TX as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
CAN TX, CAN RX
Xx Ins, 7 OUTs as AF
MSv30364V2
1. AF: alternate function on I/O pins.
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Functional overview STM32F31xx
3.1 ARM
®
Cortex™-M4 with FPU core with embedded Flash and
SRAM
The ARM Cortex-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4 with FPU 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.
With its embedded ARM core, the STM32F313xx family is compatible with all ARM tools and software.
Figure 1 shows the general block diagrams of the STM32F313xx family devices.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Embedded Flash memory
All STM32F313xx devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).
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STM32F31xx Functional overview
STM32F313xx devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from CCM, core coupled memory).
• 8 Kbytes of SRAM mapped on the instruction bus (Core Coupled Memory (CCM)), used to execute critical routines or to access data (parity check on all of CCM RAM).
• 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10) or USART2 (PD5/PD6) or I2C1 (PB6/PB7).
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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Functional overview STM32F31xx
3.7.1
3.7.2
Power supply schemes
• V
SS
, V
DD
= 1.8 V+/- 8% : external power supply for I/Os and core. It is provided externally through V
DD pins.
• V
SSA
, V
DDA
= 1.65 to 3.6 V: external analog power supply for ADC, DACs, comparators operational amplifiers, reset blocks, RCs and PLL (minimum voltage to be applied to
V
DDA
is 2.4 V when the DACs and operational amplifiers are used and 1.8 V when the
ADC is used). The V
DDA
voltage level must be always greater or equal to the V voltage level and must be provided first.
DD
• V
BAT
: must be always connected to V
DD
power supply .
Power supply supervision
The device power on reset is controlled through the external NPOR pin. The device remains in reset state when NPOR pin is held low.
To guarantee a proper power-on reset, the NPOR pin must be held low when VDDA is applied. Then, when VDD is stable, the reset state can be exited by:
• either putting the NPOR pin in high impedance. NPOR pin has an internal pull up.
• or forcing the pin to high level by connecting it to V
DDA
.
Note:
The STM32F313xx supports two low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines,the RTC alarm, COMPx, I2Cx or U(S)ARTx.
The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop mode.
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STM32F31xx
3.8
Functional overview
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 15/124
Functional overview STM32F31xx
Figure 2. Clock tree
HSI
SYSCLK
FLITFCLK to Flash programming interface to I2Cx (x = 1,2)
SYSCLK
Ext. clock
I2SSRC to I2Sx (x = 2,3)
I2S_CKIN
8 MHz
HSI RC
HSI
/2
HCLK
PLLSRC
PLLMUL
PLL x2,x3,..
x16
HSI
PLLCLK
HSE
SW prescaler
/1,2,..512
/8
APB1 prescaler
/1,2,4,8,16
PCLK1 to AHB bus, core, memory and DMA to cortex System timer
FHCLK Cortex free running clock to APB1 peripherals
SYSCLK
CSS
If (APB1 prescaler
=1) x1 else x2 to TIM 2,3,4,6,7
/2,/3,...
/16
OSC_OUT
4-32 MHz
HSE OSC
PCLK1
SYSCLK
HSI
LSE to U(S)ARTx (x = 2..5)
OSC_IN
APB2 prescaler
/1,2,4,8,16
PCLK2 to APB2 peripherals
/32
OSC32_IN RTCCLK to RTC
LSE OSC
32.768kHz
LSE to TIM 15,16,17
OSC32_OUT
If (APB2 prescaler
=1) x1 else x2
RTCSEL[1:0]
PCLK2
LSI IWDGCLK to IWDG to USART1
LSI RC
40kHz
Obsolete Product(s) - Obsolete Product(s)
MCO
Main clock output
/2 PLLCLK
HSI
LSI
LSE x2 TIM1/8
HSE
SYSCLK
MCO
SYSCLK
HSI
ADC
Prescaler
/1,2,4 to ADCxy
(xy = 12, 34)
ADC
Prescaler
/1,2,4,6,8,10,12,16,
32,64,128,256
MS30366V1
16/124 DocID024472 Rev 1
STM32F31xx Functional overview
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I 2 C, USART, general-purpose timers,
DAC and ADC.
3.11.1 Nested vectored interrupt controller (NVIC)
The STM32F313xx devices embed a nested vectored interrupt controller (NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.
DocID024472 Rev 1 17/124
Functional overview STM32F31xx
3.12 Fast analog-to-digital converter (ADC)
Up to four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F313xx family devices. The ADCs have up to 38 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, Voltage reference V
REFINT
connected to the 4 ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2 channel 17, VOPAMP3 connected to
ADC3 channel 17, VOPAMP4 connected to ADC4 channel 17.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
• Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timers can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
The temperature sensor (TS) generates a voltage V
SENSE temperature.
that varies linearly with
The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.
The internal voltage reference (V
REFINT
ADC and Comparators. V
REFINT precise voltage of V
REFINT
) provides a stable (bandgap) voltage output for the
is internally connected to the ADC_IN18 input channel. The
is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.
3.12.3 OPAMP reference voltage (VOPAMP)
Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2
18/124 DocID024472 Rev 1
STM32F31xx Functional overview channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to ADC4 channel 17.
Up to two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.
This digital interface supports the following features:
• Up to two DAC output channels on STM32F313xx devices
• 8-bit or 10-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability on STM32F313xx devices
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions on STM32F313xx devices
• DMA capability (for each channel on STM32F313xx devices)
• External triggers for conversion
The STM32F313xx embeds up to four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement.
The operational amplifier features:
• 8.2 MHz bandwidth
• 0.5 mA output capability
• Rail-to-rail input/output
• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.
3.15 Fast comparators (COMP)
The STM32F313xx devices embed seven fast rail-to-rail comparators with programmable Obsolete Product(s) - Obsolete Product(s) with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output pin
•
reference voltage.
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Functional overview STM32F31xx
All comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator
3.16 Timers and watchdogs
The STM32F313xx includes up to two advanced control timers, up to 6 general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.
Timer type Timer
Table 3. Timer feature comparison
Counter resolution
Counter type
Prescaler factor
DMA request generation
Capture/ compare
Channels
Complementary outputs
Advanced
TIM1,
TIM8 (on
STM32F313xx devices only)
16-bit Yes 4 Yes
Generalpurpose
Generalpurpose
Generalpurpose
Generalpurpose
TIM2
TIM3, TIM4
TIM15
TIM16, TIM17
32-bit
16-bit
16-bit
16-bit
Up, Down,
Up/Down
Any integer between 1 and 65536
Up, Down,
Up/Down
Up, Down,
Up/Down
Up
Up
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Any integer between 1 and 65536
Yes
Yes
Yes
Yes
4
4
2
1
No
No
1
1
Basic
TIM6,
TIM7 (on
STM32F313xx devices only)
16-bit Up
Any integer between 1 and 65536
Yes 0 No
The advanced-control timers (TIM1 on all devices and TIM8 on STM32F313xx devices) can
Obsolete Product(s) - Obsolete Product(s) general-purpose timers. The 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
20/124 DocID024472 Rev 1
STM32F31xx Functional overview
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
There are up to six synchronizable general-purpose timers embedded in the STM32F313xx
(see Table 3 for differences). Each general-purpose timer can be used to generate PWM
outputs, or act as a simple time base.
• TIM2, 3, and TIM4
These are full-featured general-purpose timers:
– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17
These three timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode output.
The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop mode. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
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Functional overview STM32F31xx
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source
The RTC and the 16 backup registers are supplied through V
DD
supply pin. The backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when
V
DD
power is not present.
They are not reset by a system or power reset.
The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
• Two programmable alarms with wake up from Stop mode capability.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.
• Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop mode on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop mode on timestamp event detection.
• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP capability.
Obsolete Product(s) - Obsolete Product(s)
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 40 kHz)
• The high-speed external clock divided by 32.
22/124 DocID024472 Rev 1
STM32F31xx Functional overview
circuit interface (I
2
C)
Up to two I
2
C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses
(2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.
Pulse width of suppressed spikes
Benefits
Drawbacks
Table 4. Comparison of I2C analog and digital filters
Analog filter Digital filter
≥ 50 ns
Available in Stop mode
Variations depending on temperature, voltage, process
Programmable length from 1 to 15
I2C peripheral clocks
1. Extra filtering capability vs. standard requirements.
2. Stable length
Wakeup from Stop on address match is not available when digital filter is enabled.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
for the features available in I2C1 and I2C2.
Table 5. STM32F31x I
2
C implementation
I2C features
(1)
I2C1 I2C2
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
X
X
X
X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X
Independent clock X X
SMBus X X Obsolete Product(s) - Obsolete Product(s)
Wakeup from STOP X X
X
X
X
X
1. X = supported.
DocID024472 Rev 1 23/124
Functional overview STM32F31xx
(USART)
The STM32F313xx devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.
The STM32F313xx devices have 2 embedded universal asynchronous receiver transmitters
(UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller.
for the features available in all U(S)ARTs interfaces
Table 6. USART features
USART modes/features
(1)
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
USART1 USART2 USART3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1. X = supported.
UART4
X
X
X
X
X
X
X
X
UART5
X
X
X
X
X
X
X
3.21 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
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STM32F31xx Functional overview
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.
for the features available in SPI1, SPI2 and SPI3.
Table 7. STM32F31x SPI/I2S implementation
SPI features (1) SPI1 SPI2
Hardware CRC calculation
Rx/Tx FIFO
NSS pulse mode
I2S mode
TI mode
1. X = supported.
X
X
X
X
X
X
X
X
X
SPI3
X
X
X
X
X
3.22 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
The STM32F313xx devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 25/124
Functional overview
TIMER 16
(for envelop)
OC
Figure 3. Infrared transmitter
STM32F31xx
PB9/PA13
TIMER 17
(for carrier)
OC
MS30365V1
3.24 Touch sensing controller (TSC)
The STM32F313xx devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.
Obsolete Product(s) - Obsolete Product(s)
26/124 DocID024472 Rev 1
STM32F31xx Functional overview
Group
Table 8. Capacitive sensing GPIOs available on STM32F313xx devices
Capacitive sensing signal name
Pin name
Group
Capacitive sensing signal name
Pin name
1
2
3
4
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PA7
PC5
PB0
PB1
PA9
PA10
PA13
PA14
PA0
PA1
PA2
PA3
PA4
PA5
PA6
5
6
7
8
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
PB14
PE2
PE3
PE4
PE5
PD12
PB3
PB4
PB6
PB7
PB11
PB12
PB13
PD13
PD14
PD15
Table 9. No. of capacitive sensing channels available on
STM32F313xx devices
Number of capacitive sensing channels
Analog I/O group
STM32F31xVx STM32F31xRx STM32F31xCx
G1
G2
G3
G4
G5
G6
3
3
3
3
3
3
3
2
3
3
3
0
0
3
3
2
3
3
3
0
0
3
3
1
G8
Number of capacitive sensing channels
23 17 16
DocID024472 Rev 1 27/124
Functional overview STM32F31xx
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
The ARM embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F313xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.
Obsolete Product(s) - Obsolete Product(s)
28/124 DocID024472 Rev 1
STM32F31xx
4 Pinouts and pin description
Figure 4. STM32F313xx LQFP48 pinout
Pinouts and pin description
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
VSSA/VREF-
VDDA/VREF+
PA0
PA1
PA2
2
3
1
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
4 33
5 32
6
7
,1&0
31
30
8
9
29
28
10 27
11 26
12
13 14 15 16
25
17 18 19 20 21 22 23 24
VDD_3
VSS_3
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
.47
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 29/124
Pinouts and pin description
Figure 5. STM32F313xx LQFP64 pinout
STM32F31xx
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA/VREF-
VDDA/VREF+
PA0
PA1
PA2
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9
,1&0
40
10 39
11 38
12 37
13 36
14 35
15 34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
VDD_3
VSS_3
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
-36
Obsolete Product(s) - Obsolete Product(s)
30/124 DocID024472 Rev 1
STM32F31xx
Figure 6. STM32F313xx LQFP100 pinout
Pinouts and pin description
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0$
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Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 31/124
Pinouts and pin description STM32F31xx
Name
Pin name
Pin type
I/O structure
Notes
Table 10. Legend/abbreviations used in the pinout table
Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
S
I
Supply pin
Input only pin
I/O
FT
FTf
TTa
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
TC
B
RST
Standard 3.3V I/O
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
POR
External power on reset pin with embedded weak pull-up resistor, powered from VDDA
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions
Pin functions
Additional functions
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral registers
Obsolete Product(s) - Obsolete Product(s)
32/124 DocID024472 Rev 1
STM32F31xx
Pin number
Pin name
(function after reset)
Pinouts and pin description
Table 11. STM32F313xx pin definitions
Pin functions
Alternate functions Additional functions
1
2
3
4
5
6
7
1
2
1
2
PE2
PE3
PE4
PE5
PE6
V
BAT
(2)
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
PC13
(3)
I/O TC
(1)
TRACECK, TIM3_CH1,
TSC_G7_IO1
TRACED0, TIM3_CH2,
TSC_G7_IO2
TRACED1, TIM3_CH3,
TSC_G7_IO3
TRACED2, TIM3_CH4,
TSC_G7_IO4
TRACED3
TIM1_CH1N
WKUP3, RTC_TAMP3
Backup power supply
WKUP2, RTC_TAMP1,
RTC_TS, RTC_OUT
8
9
3
4
3
4
OSC32_IN
(PC14)
OSC32_
OUT
(PC15)
PF9
PF10
I/O TC
I/O TC
OSC32_IN
OSC32_OUT
10
11
I/O FT
I/O FT
TIM15_CH1, SPI2_SCK
TIM15_CH2, SPI2_SCK
12
13
5
6
5
6
PF0-
OSC_IN
(PF0)
PF1-
OSC_OUT
(PF1)
I/O FTf
I/O FTf
TIM1_CH3N, I2C2_SDA
I2C2_SCL
OSC_IN
OSC_OUT
14
15
7
8
7 NRST
PC0
I/O RST
I/O TTa
Device reset input / internal reset output (active low)
ADC12_IN6, COMP7_INM
16 9 PC1 I/O TTa
ADC12_IN7, COMP7_INP
17 10 PC2 I/O TTa COMP7_OUT ADC12_IN8
18 11 PC3 I/O TTa TIM1_BKIN2 ADC12_IN9
19 PF2 I/O TTa ADC12_IN10
20 12 8
VSSA/
VREF-
S Analog ground/Negative reference voltage
21
22
VREF+
VDDA
S
S
Positive reference voltage
Analog power supply
DocID024472 Rev 1 33/124
Pinouts and pin description
Pin number
Table 11. STM32F313xx pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions
STM32F31xx
Additional functions
13 9
VDDA/
VREF+
S Analog power supply/Positive reference voltage
23
24
25
14
15
16
10
11
12
PA0
PA1
PA2
I/O TTa
I/O TTa
I/O TTa
USART2_CTS,
TIM2_CH1_ETR, TIM8_BKIN,
TIM8_ETR, TSC_G1_IO1,
COMP1_OUT
USART2_RTS, TIM2_CH2,
TSC_G1_IO2, TIM15_CH1N,
RTC_REFIN
USART2_TX, TIM2_CH3,
TIM15_CH1, TSC_G1_IO3,
COMP2_OUT
ADC1_IN1, COMP1_INM,
RTC_ TAMP2, WKUP1,
COMP7_INP
ADC1_IN2, COMP1_INP,
OPAMP1_VINP,
OPAMP3_VINP
ADC1_IN3, COMP2_INM,
OPAMP1_VOUT
26 17 13 PA3 I/O TTa
USART2_RX, TIM2_CH4,
TIM15_CH2, TSC_G1_IO4
COMP1_OUT
ADC1_IN4, OPAMP1_VINP,
COMP2_INP,
OPAMP1_VINM
ADC1_IN5 27
28
18
19
PF4
VDD_4
I/O TTa
S
29 20 14 PA4 I/O TTa
SPI1_NSS, SPI3_NSS,
I2S3_WS, USART2_CK,
TSC_G2_IO1, TIM3_CH2
ADC2_IN1, DAC1_OUT1,
OPAMP4_VINP,
COMP1_INM, COMP2_INM,
COMP3_INM, COMP4_INM,
COMP5_INM, COMP6_INM,
COMP7_INM
30 21 15 PA5 I/O TTa
SPI1_SCK, TIM2_CH1_ETR,
TSC_G2_IO2
ADC2_IN2, DAC1_OUT2
OPAMP1_VINP,
OPAMP2_VINM,
OPAMP3_VINP,
COMP1_INM, COMP2_INM,
COMP3_INM, COMP4_INM,
COMP5_INM, COMP6_INM,
Obsolete Product(s) - Obsolete Product(s)
SPI1_MISO, TIM3_CH1,
TIM8_BKIN, TIM1_BKIN,
31 22 16 PA6 I/O TTa ADC2_IN3, OPAMP2_VOUT
TIM16_CH1, COMP1_OUT,
TSC_G2_IO3
32
33
23
24
17 PA7
PC4
I/O TTa
I/O TTa
SPI1_MOSI, TIM3_CH2,
TIM17_CH1, TIM1_CH1N,
TIM8_CH1N, TSC_G2_IO4,
COMP2_OUT
USART1_TX
ADC2_IN4, COMP2_INP,
OPAMP2_VINP,
OPAMP1_VINP
ADC2_IN5
34/124 DocID024472 Rev 1
STM32F31xx
Pin number
Pinouts and pin description
Table 11. STM32F313xx pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
34
35
36
40
41
42
43
37
38
39
44
45
46
47
48
25
26
27
28
29
30
18
19
20
21
22
PC5
PB0
PB1
NPOR
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
I/O TTa
I/O TTa
I/O TTa
I POR
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
(4)
USART1_RX, TSC_G3_IO1
TIM3_CH3, TIM1_CH2N,
TIM8_CH2N, TSC_G3_IO2
ADC2_IN11, OPAMP2_VINM,
OPAMP1_VINM
ADC3_IN12, COMP4_INP,
OPAMP3_VINP,
OPAMP2_VINP
TIM3_CH4, TIM1_CH3N,
TIM8_CH3N, COMP4_OUT,
TSC_G3_IO3
ADC3_IN1, OPAMP3_VOUT
Device power-on reset input
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4, TIM1_BKIN2
USART3_RX, TIM1_BKIN
USART3_TX, TIM2_CH3,
TSC_SYNC
ADC3_IN13, COMP4_INP
COMP4_INM, ADC34_IN6
ADC3_IN2
ADC3_IN14
ADC3_IN15
ADC3_IN16
ADC3_IN3
ADC4_IN1
ADC4_IN2
COMP5_INM,
OPAMP4_VINM,
OPAMP3_VINM
USART3_RX, TIM2_CH4,
TSC_G6_IO1
COMP6_INP, OPAMP4_VINP
Digital ground
Digital power supply
49
50
31
32
23
24
VSS_2
VDD_2
S
S
SPI2_NSS, I2S2_WS,
51 33 25 PB12 I/O TTa I2C2_SMBA, USART3_CK,
ADC4_IN3, COMP3_INM,
Obsolete Product(s) - Obsolete Product(s)
SPI2_SCK, I2S2_CK, ADC3_IN5, COMP5_INP,
52 34 26 PB13 I/O TTa USART3_CTS, TIM1_CH1N,
TSC_G6_IO3
OPAMP4_VINP,
OPAMP3_VINP
53
54
35
36
27
28
PB14
PB15
I/O TTa
I/O TTa
SPI2_MISO, I2S2ext_SD,
USART3_RTS, TIM1_CH2N,
TIM15_CH1, TSC_G6_IO4
SPI2_MOSI, I2S2_SD,
TIM1_CH3N, RTC_REFIN,
TIM15_CH1N, TIM15_CH2
COMP3_INP, ADC4_IN4,
OPAMP2_VINP
ADC4_IN5, COMP6_INM
DocID024472 Rev 1 35/124
Pinouts and pin description
Pin number
Table 11. STM32F313xx pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions
STM32F31xx
Additional functions
55
56
57
58
PD8
PD9
PD10
PD11
I/O TTa
I/O TTa
I/O TTa
I/O TTa
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
ADC4_IN12, OPAMP4_VINM
ADC4_IN13
ADC34_IN7, COMP6_INM
ADC34_IN8, COMP6_INP,
OPAMP4_VINP
59
60
61
PD12
PD13
PD14
I/O TTa
I/O TTa
I/O TTa
USART3_RTS, TIM4_CH1,
TSC_G8_IO1
TIM4_CH2, TSC_G8_IO2
TIM4_CH3, TSC_G8_IO3
ADC34_IN9, COMP5_INP
ADC34_IN10, COMP5_INM
COMP3_INP, ADC34_IN11,
OPAMP2_VINP
62
63
64
37
38
PD15
PC6
PC7
I/O TTa
I/O FT
I/O FT
SPI2_NSS, TIM4_CH4,
TSC_G8_IO4
I2S2_MCK, COMP6_OUT,
TIM8_CH1, TIM3_CH1
I2S3_MCK, TIM8_CH2,
TIM3_CH2, COMP5_OUT
COMP3_INM
65
66
67
39
40
41 29
PC8
PC9
PA8
I/O FT
I/O FT
I/O FT
TIM8_CH3, TIM3_CH3,
COMP3_OUT
TIM8_CH4, TIM8_BKIN2,
TIM3_CH4, I2S_CKIN
I2C2_SMBA, I2S2_MCK,
USART1_CK, TIM1_CH1,
TIM4_ETR, MCO,
COMP3_OUT
68 42 30 PA9 I/O FTf
I2C2_SCL, I2S3_MCK,
USART1_TX, TIM1_CH2,
TIM2_CH3, TIM15_BKIN,
TSC_G4_IO1, COMP5_OUT
Obsolete Product(s) - Obsolete Product(s)
69 43 31 PA10 I/O FTf
I2C2_SDA, USART1_RX,
TIM1_CH3, TIM2_CH4,
TIM8_BKIN, TIM17_BKIN,
TSC_G4_IO2, COMP6_OUT
70 44 32 PA11 I/O FT
USART1_CTS, CAN_RX,
TIM1_CH1N, TIM1_CH4,
TIM1_BKIN2, TIM4_CH1,
COMP1_OUT
36/124 DocID024472 Rev 1
STM32F31xx
Pin number
Pinouts and pin description
Table 11. STM32F313xx pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions Additional functions
71
72
73
74
75
76
77
78
79
45
46
47
48
49
50
51
52
33
34
35
36
37
38
PA12
PA13
PF6
VSS_3
VDD_3
PA14
PA15
PC10
PC11
I/O FT
I/O FT
I/O FTf
S
S
I/O FTf
I/O FTf
I/O FT
I/O FT
USART1_RTS, CAN_TX,
TIM1_CH2N, TIM1_ETR,
TIM4_CH2, TIM16_CH1,
COMP2_OUT
USART3_CTS, TIM4_CH3,
TIM16_CH1N, TSC_G4_IO3,
IR_OUT, SWDIO-JTMS
I2C2_SCL, USART3_RTS,
TIM4_CH4
Ground
Digital power supply
I2C1_SDA, USART2_TX,
TIM8_CH2, TIM1_BKIN,
TSC_G4_IO4, SWCLK-JTCK
I2C1_SCL, SPI1_NSS,
SPI3_NSS, I2S3_WS, JTDI,
USART2_RX, TIM1_BKIN,
TIM2_CH1_ETR, TIM8_CH1
SPI3_SCK, I2S3_CK,
USART3_TX, UART4_TX,
TIM8_CH1N
SPI3_MISO, I2S3ext_SD,
USART3_RX, UART4_RX,
TIM8_CH2N
80 53 PC12 I/O FT
SPI3_MOSI, I2S3_SD,
USART3_CK, UART5_TX,
TIM8_CH3N
81 PD0 I/O FT CAN_RX
82 PD1 I/O FT
CAN_TX, TIM8_CH4,
Obsolete Product(s) - Obsolete Product(s)
83 54 PD2 I/O FT
UART5_RX, TIM3_ETR,
TIM8_BKIN
84 PD3 I/O FT
USART2_CTS,
TIM2_CH1_ETR
USART2_RTS, TIM2_CH2 85 PD4 I/O FT
86
87
PD5
PD6
I/O FT
I/O FT
USART2_TX
USART2_RX, TIM2_CH4
88 PD7 I/O FT USART2_CK, TIM2_CH3
DocID024472 Rev 1 37/124
Pinouts and pin description
Pin number
Table 11. STM32F313xx pin definitions (continued)
Pin functions
Pin name
(function after reset)
Alternate functions
STM32F31xx
Additional functions
89
90
91
92
93
94
95
97
55
56
57
58
59
60
61
62
98
99 63
100 64
39
40
41
42
43
44
45
46
47
48
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_1
VDD_1
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
S
S
FT
FT
FT
FTf
FTf
B
FTf
FTf
FT
FT
SPI3_SCK, I2S3_CK,
SPI1_SCK, USART2_TX,
TIM2_CH2, TIM3_ETR,
TIM4_ETR, TIM8_CH1N,
TSC_G5_IO1, JTDO-
TRACESWO
SPI3_MISO, I2S3ext_SD,
SPI1_MISO, USART2_RX,
TIM3_CH1, TIM16_CH1,
TIM17_BKIN, TIM8_CH2N,
TSC_G5_IO2, NJTRST
SPI3_MOSI, SPI1_MOSI,
I2S3_SD, I2C1_SMBA,
USART2_CK, TIM16_BKIN,
TIM3_CH2, TIM8_CH3N,
TIM17_CH1
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM4_CH1,
TIM8_CH1, TSC_G5_IO3,
TIM8_ETR, TIM8_BKIN2
I2C1_SDA, USART1_RX,
TIM3_CH4, TIM4_CH2,
TIM17_CH1N, TIM8_BKIN,
TSC_G5_IO4
Boot memory selection
I2C1_SCL, CAN_RX,
TIM16_CH1, TIM4_CH3,
TIM8_CH2, TIM1_BKIN,
TSC_SYNC, COMP1_OUT
I2C1_SDA, CAN_TX,
TIM17_CH1, TIM4_CH4,
TIM8_CH3, IR_OUT,
COMP2_OUT
USART1_TX, TIM4_ETR,
TIM16_CH1
USART1_RX, TIM17_CH1
Ground
Digital power supply
1. Function availability depends on the chosen device.
When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must not be configured in analog mode.
38/124 DocID024472 Rev 1
STM32F31xx Pinouts and pin description
2. V
BAT
pin must be connected to V
DD
supply.
3. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the reference manual.
4. This pin is powered by VDDA.
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 39/124
Table 12. Alternate functions for port A
Port
&
Pin
Name
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RTC_
REFIN
PA8 MCO
PA9
TIM2_
CH1_
ETR
TIM2_
CH2
TIM2_
CH3
TIM2_
CH4
TIM3_
CH2
TIM2_
CH1_
ETR
TIM16_
CH1
TIM3_
CH1
TIM17_
CH1
TIM3_
CH2
TSC_
G1_IO1
TSC_
G1_IO2
TSC_
G1_IO3
TSC_
G1_IO4
TSC_
G2_IO1
TSC_
G2_IO2
TSC_
G2_IO3
TSC_
G2_IO4
TSC_
G4_IO1
TIM8_
BKIN
TIM8_
CH1N
I2C2_
SMBA
I2C2_
SCL
SPI1_
NSS
SPI1_
SCK
SPI1_
MISO
SPI1_
MOSI
I2S2_
MCK
I2S3_
MCK
SPI3_NSS,
I2S3_WS
USART2
_CTS
COMP1
_OUT
USART2
_RTS
USART2
_TX
COMP2
_OUT
USART2
_RX
USART2
_CK
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
COMP1
_OUT
COMP2
_OUT
USART1
_CK
COMP3
_OUT
USART1
_TX
COMP5
_OUT
TIM8_
BKIN
TIM15_
CH1N
TIM15_
CH1
TIM15_
CH2
TIM15_
BKIN
TIM8_
ETR
TIM4_
ETR
TIM2_
CH3
TIM17_ TSC_ I2C2_ USART1 COMP6
PA10
BKIN G4_IO2 SDA
TIM1_CH3
_RX _OUT Obsolete Product(s) - Obsolete Product(s)
PA11 TIM1_CH1N
USART1
_CTS
COMP1
_OUT
CAN_RX
TIM2_
CH4
TIM4_
CH1
AF11 AF12 AF14 AF15
TIM8_
BKIN
TIM1_CH4
TIM1_
BKIN2
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 12. Alternate functions for port A (continued)
Port
&
Pin
Name
AF0 AF1 AF2 AF3 AF4
PA12
PA13
PA14
SWDIO
-JTMS
SWCLK
-JTCK
TIM16_
CH1
TIM16_
CH1N
PA15 JTDI
TIM2_
CH1_
ETR
TIM8_
CH1
TSC_
G4_IO3
TSC_
G4_IO4
I2C1_
SDA
I2C1_
SCL
AF5 AF6
SPI1_
NSS
SPI3_NSS,
I2S3_WS
AF7 AF10
IR_
OUT
TIM8_
CH2
TIM1_CH2N
USART1
_RTS
COMP2
_OUT
TIM1_BKIN
USART3
_CTS
USART2
_TX
CAN_TX
TIM4_
CH2
TIM4_
CH3
USART2
_RX
AF8 AF9
TIM1_
BKIN
AF11
TIM1_ETR
AF12 AF14 AF15
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Obsolete Product(s) - Obsolete Product(s)
Table 13. Alternate functions for port B
Port
&
Pin
Name
AF0 AF1 AF2
PB0
PB1
TIM3_
CH3
TIM3_
CH4
PB3
PB4
PB5
JTDO-
TRACES
WO
TIM2_
CH2
NJTRST
TIM16_
CH1
TIM16_
BKIN
PB6
PB7
PB8
PB9
PB10
PB11
TIM16_
CH1N
TIM17_
CH1N
TIM16_
CH1
TIM17_
CH1
TIM2_
CH3
TIM2_
CH4
TIM4_
ETR
TIM3_
CH1
TIM3_
CH2
TIM4_
CH1
TIM4_
CH2
TIM4_
CH3
TIM4_
CH4
PB13
AF3
TSC_
G3_IO2
TSC_
G3_IO3
AF4
TIM8_
CH2N
TIM8_
CH3N
TSC_
G5_IO1
TIM8_
CH1N
AF5
SPI1_
SCK
TSC_
SYNC
TSC_
G6_IO1
TSC_
G6_IO2
TSC_
G6_IO3
TSC_
G5_IO2
TIM8_
CH3N
TSC_
G5_IO3
TSC_
G5_IO4
TSC_
SYNC
TIM8_
CH2N
I2C1_
SMBA
SPI1_
MISO
SPI1_
MOSI
I2C1_SCL TIM8_CH1
I2C1_
SDA
I2C1_SCL
TIM8_
BKIN
I2C1_
SDA
I2C2_
SMBA
SPI2_NSS,
I2S2_WS
SPI2_SCK,
I2S2_CK
AF6
TIM1_CH2N
TIM1_CH3N
AF7
SPI3_SCK,
I2S3_CK
USART2_
TX
AF8
COMP4_
OUT
AF9 AF10
TIM3_
ETR
SPI3_MISO,
I2S3ext_SD
SPI3_MOSI,
I2S3_SD
TIM8_
ETR
USART2_
RX
USART2_
CK
USART1_
TX
USART1_
RX
IR_OUT
COMP1_
OUT
COMP2_
OUT
CAN_RX
CAN_TX
TIM17_
BKIN
TIM17_
CH1
TIM8_
BKIN2
TIM3_
CH4
TIM8_
CH2
TIM8_
CH3
TIM1_
BKIN
TIM1_
CH1N
USART3_
TX
USART3_
RX
USART3_
CK
USART3_
CTS
AF12 AF15
EVENT
OUT
EVENT
OUT
EVENT
OUT
TIM1_
BKIN
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 13. Alternate functions for port B (continued)
Port
&
Pin
Name
AF0
PB14
PB15
RTC_
REFIN
AF1 AF2 AF3 AF4
TIM15_
CH1
TIM15_
CH2
TIM15_
CH1N
TSC_
G6_IO4
TIM1_
CH3N
AF5 AF6
SPI2_MISO,
I2S2ext_SD
SPI2_MOSI,
I2S2_SD
TIM1_
CH2N
AF7
USART3_
RTS
AF8 AF9 AF10 AF12 AF15
EVENT
OUT
EVENT
OUT
Obsolete Product(s) - Obsolete Product(s)
Port &
Pin
Name
AF1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PC7
PC8
EVENTOUT
EVENTOUT
PC9 EVENTOUT
PC10 EVENTOUT
PC11 EVENTOUT
PC12 EVENTOUT
PC13
PC14
PC15
AF2
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
Table 14. Alternate functions for port C
AF3
COMP7_OUT
TSC_G3_IO1
AF4
TIM8_CH1
TIM8_CH2
TIM8_CH3
TIM8_CH4
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
TIM1_CH1N
AF5
TIM1_BKIN2
I2S2_MCK
I2S3_MCK
AF6
I2S_CKIN
UART4_TX
UART4_RX
UART5_TX
TIM8_BKIN2
SPI3_SCK, I2S3_CK
SPI3_MISO, I2S3ext_SD
SPI3_MOSI, I2S3_SD
AF7
USART1_TX
USART1_RX
COMP6_OUT
COMP5_OUT
COMP3_OUT
USART3_TX
USART3_RX
USART3_CK
Obsolete Product(s) - Obsolete Product(s)
Port &
Pin Name
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD4
PD5
PD6
PD7
PD0
PD1
PD2
PD3
AF1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
AF2
Table 15. Alternate functions for port D
AF3 AF4 AF5 AF6
TIM8_CH4
TIM8_BKIN UART5_RX
TIM8_BKIN2
TIM3_ETR
TIM2_CH1_ETR
TIM2_CH2
TIM2_CH4
TIM2_CH3
CAN_RX
AF7
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4 SPI2_NSS
Obsolete Product(s) - Obsolete Product(s)
Port &
Pin Name
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE4
PE5
PE6
PE7
PE0
PE1
PE2
PE3
AF0
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
AF1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
Table 16. Alternate functions for port E
AF2 AF3
TIM4_ETR
AF4
TIM16_CH1
TIM17_CH1
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
AF6
TIM1_BKIN2
AF7
USART1_TX
USART1_RX
USART3_RX
Obsolete Product(s) - Obsolete Product(s)
Port &
Pin Name
PF0
PF1
PF2
PF4
PF6
PF9
PF10
AF1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
AF2
COMP1_OUT
TIM4_CH4
Table 17. Alternate functions for port F
AF3 AF4 AF5
I2C2_SDA
I2C2_SCL
AF6
TIM1_CH3N
TIM15_CH1
TIM15_CH2
I2C2_SCL
SPI2_SCK
SPI2_SCK
AF7
USART3_RTS
Obsolete Product(s) - Obsolete Product(s)
Memory mapping STM32F31xx
48/124
0xFFFF FFFF
7
Cortex-M4 with FPU
Internal
Peripherals
0xE000 0000
Figure 7. STM32F31x memory map
0x5000
07FF
0x5000 0000
0x4800 1800
0x4800 0000
6
0x4002 43FF
0xC000 0000
0x4002 0000
5
0x4001 6C00
0xA000 0000
0x4001 0000
4
0x4000 A000
0x8000 0000
0x4000 0000
3
0x6000 0000
2
0x4000 0000
Peripherals
1
0
0x0000 0000
SRAM
CODE
Reserved
AHB3
Reserved
AHB2
Reserved
AHB1
Reserved
APB2
Reserved
APB1
0x1FFF FFFF
Option bytes
0x1FFF F800
System memory
0x1FFF D800
0x1000 2000
Reserved
CCM RAM
0x1000 0000
Reserved
0x0804 0000
Flash memory
0x0800 0000
Reserved
0x0004 0000
0x0000 0000
Flash, system memory or SRAM, depending on BOOT configuration
MSv30355V2
DocID024472 Rev 1
STM32F31xx Memory mapping
Bus
Table 18. STM32F31x memory map and peripheral register boundary addresses
Boundary address
Size
(bytes)
Peripheral
AHB3
AHB2
AHB1
0x5000 0400 - 0x5000 07FF
0x5000 0000 - 0x5000 03FF
0x4800 1800 - 0x4FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0800 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 4C00 - 0x4001 7FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
1 K
32 K
13 K
1 K
1 K
1 K
3 K
1 K
3 K
1 K
2 K
1 K
1 K
1 K
~132 M
1 K
1 K
1 K
1 K
1 K
1 K
~128 M
1 K
3 K
1 K
Reserved
Flash interface
Reserved
RCC
Reserved
DMA2
DMA1
Reserved
Reserved
TIM17
TIM16
TIM15
ADC3 - ADC4
ADC1 - ADC2
Reserved
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
TSC
Reserved
CRC
Obsolete Product(s) - Obsolete Product(s)
APB2
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
1 K
1 K
Reserved
USART1
0x4001 3400 - 0x4001 37FF 1 K TIM8
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 0800 - 0x4001 2BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
1 K
1 K
9 K
1 K
1 K
SPI1
TIM1
Reserved
EXTI
SYSCFG + COMP + OPAMP
DocID024472 Rev 1 49/124
Memory mapping STM32F31xx
Bus
Table 18. STM32F31x memory map and peripheral register boundary addresses (continued)
Boundary address
Size
(bytes)
Peripheral
APB1
0x4000 8000 - 0x4000 FFFF
0x4000 7800 - 0x4000 7FFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 5C00 - 0x4000 63FF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
2 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
32 K
2 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
4 K
1 K
1 K
1 K
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
1 K
1 K
TIM4
TIM3
0x4000 0000 - 0x4000 03FF 1 K TIM2
Reserved
Reserved
DAC (dual)
PWR
Reserved
Reserved bxCAN
Reserved
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3/I2S3
SPI2/I2S2
I2S2ext
IWDG
WWDG
RTC
Reserved
TIM7
TIM6
Reserved
50/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
6.1.1
Unless otherwise specified, all voltages are referenced to V
SS
.
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
A max (given by
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
= 1.8 V, V
They are given only as design guidelines and are not tested.
DDA
= 3.3 V.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
The loading conditions used for pin parameter measurement are shown in
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9
.
Figure 8. Pin loading conditions Figure 9. Pin input voltage
Obsolete Product(s) - Obsolete Product(s)
-#5PIN -#5PIN
C = 50 pF
6).
-36 -36
DocID024472 Rev 1 51/124
Electrical characteristics
6.1.6 Power supply scheme
Figure 10. Power supply scheme
VBAT
Po wer swi tch
Backup circuitry
(LSE,RTC,
Wake-up logic
Backup registers)
STM32F31xx
OUT
GP I/O s
VREF+
VREF-
ADC/
DAC
IO
Logic
VDD
4 × 100 nF
+ 1 × 4.7 μF
VDDA
10 nF
+ 1 μF
10 nF
+ 1 μF
VREF
4 × VDD
3 × VSS
VDDA
VSSA
IN
Regulator
Kernel logic
(CPU,
Digital
& Memories)
!NALOG2#S0,,
COMPARATORS/0!-0
MS31434V1
1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins.
Caution: Each power supply pair (V
DD
/V
SS
, V
DDA
/V
SSA
etc..) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device.
Figure 11. Current consumption measurement scheme
)$$
6$$
52/124 DocID024472 Rev 1
-36
STM32F31xx Electrical characteristics
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 19: Voltage characteristics
,
Table 20: Current characteristics
, and
Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 19. Voltage characteristics
(1)
Ratings Min Max Unit
V
|V
V
|
DD
V
DDA
V
Δ V
– V
IN
(3)
SSX
− V
SS
– V
SS
V
DD
– V
DDA
V
REF+
–V
DDA
(2)
DDx
|
SS
ESD(HBM)
|
External digital supply voltage
External analog supply voltage
Allowed voltage difference for V
DD
> V
DDA
Allowed voltage difference for V
REF+
> V
DDA
Input voltage on FT and FTf pins
Input voltage on TTa pins
Input voltage on any other pin
Input voltage on POR pins
Variations between different V
DD power pins
Variations between all the different ground pins
Electrostatic discharge voltage (human body model)
-0.3
-0.3
-
1.95
4.0
0.4
-
V
SS
− 0.3
V
SS
− 0.3
V
SS
− 0.3
V
SS
− 0.3
-
0.4
V
DD
+ 4.0
4.0
4.0
V
DDA
+ 4.0
50
50 see
Section 6.3.11: Electrical sensitivity characteristics
V mV
1. All main power (V
V
V
DDA
DDA
DD
, V
DDA
) and ground (V
SS
, V
SSA
) pins must always be connected to the external power supply, in the
must power on before or at the same time as V
must be greater than or equal to V
DD
.
DD
DDA
and V
in the power up sequence.
DD
:
2. V
REF+ must be always lower or equal than V
DDA
(V
REF+
≤ V
DDA)
. If unused then it must be connected to V
DDA
.
3. V
IN
maximum must always be respected. Refer to
Table 20: Current characteristics for the maximum allowed injected
current values.
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 53/124
Electrical characteristics STM32F31xx
Symbol
Table 20. Current characteristics
Ratings Max.
Unit
Σ
I
Σ I
VDD
Σ I
VSS
I
VDD
I
VSS
I
IO(PIN)
I
IO(PIN)
INJ(PIN)
Total current into sum of all VDD_x power lines (source)
Total current out of sum of all VSS_x ground lines (sink)
Maximum current into each V
DD_x power line (source)
(1)
Maximum current out of each V
SS _x
Output current sunk by any I/O and control pin
Output current source by any I/O and control pin
Total output current sunk by sum of all IOs and control pins
(2)
Total output current sourced by sum of all IOs and control pins
Injected current on FT, FTf, POR and B pins
(3)
Injected current on TC and RST pin (4)
Injected current on TTa pins
(5)
Total injected current (sum of all I/O and control pins)
(6)
−
160
160
100
− 100
25
−
−
25
80
80
-5/+0
± 5
± 5 mA
Σ I
INJ(PIN)
± 25
1. All main power (V permitted range.
DD
, V
DDA
) and ground (V
SS
and V
SSA
) pins must always be connected to the external power supply, in the
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
4. A positive injection is induced by V
> V
DD
while a negative injection is induced by V < V
SS
. I
INJ(PIN)
must never be
5. A positive injection is induced by V
> V
DDA
while a negative injection is induced by V
Table 19: Voltage characteristics
disturbs the analog performance of the device. See note (2) below
.
IN
< V
SS
. I
INJ
(PIN) must never be
for the maximum allowed input voltage values. Negative injection
6. When several inputs are submitted to a current injection, the maximum Σ I negative injected currents (instantaneous values).
INJ(PIN)
is the absolute sum of the positive and
Symbol
T
STG
T
J
Table 21. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Value
–65 to +150
150
Unit
°C
°C
Obsolete Product(s) - Obsolete Product(s)
54/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
6.3.1 General operating conditions
Table 22. General operating conditions
Parameter Conditions Min Symbol Max Unit f
HCLK f
PCLK1 f
PCLK2
V
DD
V
DDA
V
IN
P
D
T
A
T
J
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
Analog operating voltage
(OPAMP and DAC not used)
Analog operating voltage
(OPAMP and DAC used)
Analog operating voltage
(ADC used)
Must have a potential equal to or higher than
V
DD
I/O input voltage
Power dissipation at T
85 °C for suffix 6 or T
A
105 °C for suffix 7
(1) suffix version suffix version
A
=
=
Ambient temperature for 6
Ambient temperature for 7
Junction temperature range
0
0
0
1.65
1.65
2.4
1.8 V
72
36
72
1.95
3.6
3.6
3.6 V
TC I/O
TTa I/O
–0.3
V
DD
+0.3
–0.3
V
DDA
+0.3
FT, FTf and POR I/O pins –0.3
5.2
BOOT0 0 5.5
LQFP100
LQFP64
LQFP48
Maximum power dissipation
Low power dissipation
(2)
-
-
-
488
444
364
–40 85
–40 105
Maximum power dissipation
Low power dissipation
(2)
6 suffix version
7 suffix version
–40 105
–40 125
–40
–40
105
125
1. If T is lower, higher P
D
values are allowed as long as T
J
does not exceed T
Jmax
(see
Obsolete Product(s) - Obsolete Product(s)
2. In low power dissipation state, T
Table 21: Thermal characteristics
can be extended to this range as long as T
).
J
does not exceed T
Jmax
(see
MHz
V
V
V mW
°C
°C
°C
DocID024472 Rev 1 55/124
Electrical characteristics STM32F31xx
The parameters given in
Table 23 are derived from tests performed under the ambient
temperature condition summarized in
Symbol t
VDD t
VDDA
Table 23. Operating conditions at power-up / power-down
Parameter Conditions Min Max
V
DD
rise time rate
V
DD
fall time rate
V
DDA
rise time rate
V
DDA
fall time rate
0
20
0
20
∞
∞
∞
∞
Unit
µs/V
The parameters given in
Table 24 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Symbol
V
REFINT_CAL
Table 24. Embedded internal reference voltage
Parameter Conditions Min Typ Max
Raw data acquired at temperature of 30 °C
V
DDA
= 3.3 V
Unit
V
REFINT
Internal reference voltage
–40 °C < T
A
< +105 °C 1.16
1.2
1.25
–40 °C < T
A
< +85 °C 1.16
1.2
1.24
(1)
V
V
T
S_vrefint
V
RERINT
ADC sampling time when reading the internal reference voltage
Internal reference voltage spread over the temperature range
V
DD
= 1.8 V ±10 mV
2.2
-
-
10
(2)
µs mV
-
-
1.5
-
2.5
100
4.5
ppm/°C T
Coeff
Temperature coefficient
T
REFINT_RDY
(3)
Internal reference voltage temporization
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production
3. Guaranteed by design, not tested in production. Latency between the time when pin NPOR is set to 1 by the application and the time when V
REFINTRDYF
is set to 1 by the hardware.
Obsolete Product(s) - Obsolete Product(s)
Table 25. Internal reference voltage calibration values
Calibration value name Description Memory address ms
0x1FFF F7BA - 0x1FFF F7BB
56/124 DocID024472 Rev 1
STM32F31xx
6.3.4
Electrical characteristics
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in
Figure 11: Current consumption measurement scheme
.
All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the f
HCLK
frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
• When the peripherals are enabled f
PCLK2
= f
HCLK
and f
PCLK1
= f
HCLK/2
• When f
HCLK
> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
The parameters given in
are derived from tests performed under ambient temperature and supply voltage conditions summarized in
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 57/124
Electrical characteristics STM32F31xx
Table 26. Typical and maximum current consumption from V
DD at V
DD
= 1.94 V
supply
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions f
HCLK
Typ
Max @ T
A
(1)
25 °C 85 °C 105 °C
Typ
Max @ T
A
25 °C 85 °C 105 °C
Unit
I
DD
72 MHz 65.6
71.1
72.3
64 MHz 58.8
63.7
65.0
Supply current in
Run mode, executing from Flash
External clock (HSE bypass)
48 MHz 45.1
48.9
50.1
32 MHz 30.7
33.3
34.4
24 MHz 23.3
8 MHz
1 MHz
7.9
1.2
64 MHz 53.7
25.4
8.7
1.5
58.2
26.3
9.3
1.8
59.4
73.7
29.7
32.2
32.9
66.2
26.6
28.9
29.6
51.1
20.5
22.2
22.9
35.2
14.0
15.2
15.8
27.1
10.7
11.8
12.3
9.9
3.6
4.1
4.5
2.6
0.7
0.9
1.2
60.6
26.4
28.5
29.3
Internal clock (HSI)
Internal clock (HSI)
48 MHz 41.2
44.7
45.8
32 MHz 28.1
30.5
31.5
24 MHz 21.4
23.3
24.2
46.8
20.3
22.0
22.7
32.3
13.9
15.1
15.6
24.9
7.2
7.9
8.5
23.3
16.2
9.1
8 MHz 7.4
8.1
72 MHz 66.7 72.3
(2)
8.7
64 MHz 59.7
64.7
65.9
9.4
73.5
74.9
67.2
3.6
4.1
30.8 33.3
27.5
29.8
4.4
30.5
5.2
34.2
31.3
Supply current in
Run mode, executing from RAM
External clock (HSE bypass)
48 MHz 45.3
32 MHz 30.7
24 MHz 23.2
25.3
26.1
8 MHz
1 MHz
7.6
0.8
49.2
33.3
8.5
1.0
50.4
34.4
9.1
1.4
64 MHz 54.4
59.0
60.2
51.4
35.2
26.9
9.7
2.3
20.7
13.9
10.5
3.4
0.3
22.5
15.2
11.5
3.7
0.5
23.2
15.8
12.1
4.3
0.8
61.4
27.0
29.3
30.1
23.9
16.4
12.6
5.0
1.7
30.7
48 MHz 41.3
44.9
45.9
32 MHz 27.9
30.4
31.4
24 MHz 21.1
23.0
23.9
47.0
20.4
22.2
22.8
32.2
13.7
14.9
15.5
24.6
6.8
7.6
8.1
23.4
16.1
8.7
12.8
5.2
2.0
30.0
33.7
30.3
23.5
16.4
8 MHz 7.0
7.8
8.3
8.9
3.2
3.5
4.2
4.8
Obsolete Product(s) - Obsolete Product(s) mA
58/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Table 26. Typical and maximum current consumption from V
DD at V
DD
= 1.94 V (continued)
supply
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions f
HCLK
Max @ T
A
(1)
Typ
25 °C 85 °C 105 °C
72 MHz 48.0 52.4
53.7
64 MHz 42.9
46.8
48.1
54.9
49.1
I
DD
Supply current in
Sleep mode, executing from Flash or RAM
External clock (HSE bypass)
48 MHz 32.5
35.5
36.7
32 MHz 21.9
24.0
25.0
24 MHz 16.6
18.2
19.0
8 MHz 5.4
6.1
6.7
1 MHz 0.5
0.7
1.1
64 MHz 37.5
40.9
42.3
37.6
25.7
19.8
7.3
2.0
43.2
4.8
5.3
3.2
3.6
2.5
2.7
0.7
0.9
0.1
0.1
5.9
6.7
48 MHz 28.4
31.0
32.2
33.0
4.4
5.0
Internal clock (HSI)
32 MHz 19.1
21.0
22.0
24 MHz 14.5
15.9
16.7
22.7
17.4
2.9
3.3
1.5
1.7
8 MHz 4.8
5.4
5.9
6.6
0.5
0.7
1. Data based on characterization results, not tested in production unless otherwise specified
.
2. Data based on characterization results and tested in production with code executing from RAM.
Typ
7.1
7.9
6.4
7.1
Max @ T
A
(1)
25 °C 85 °C 105 °C
8.5
7.6
5.9
4.2
3.3
1.3
0.5
7.2
5.5
8.2
6.6
4.9
4.0
2.2
1.3
7.8
6.2
3.9
2.2
1.1
4.6
3.0
2.0
Unit mA
Table 27. Typical and maximum current consumption from the V
DDA
supply
V
DDA
= 2.4 V V
DDA
= 3.6 V
Symbol Parameter
Conditions
(1) f
HCLK
Typ
Max @ T
A
(2)
Typ
Max @ T
A
(2)
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
Unit
72 MHz 225 276
64 MHz 198 249
289
261
297 245 302
268 216 270
319
284
329
293
48 MHz 149 195 204 211 159 209 222 230
HSE
I
DDA
Supply current in
24 MHz 80
8 MHz 2
119
3
124
4
128
6
86
3
126
4
131
5
135 code
9
µA
1 MHz 2 3 5 7 3 4 6 9 executing bypass
32 MHz 102 145 152 157 110 154 162 169 from Flash or RAM
64 MHz 270 323 337 344 299 354 371 381
48 MHz 220 269 280 286 244 293 309 318
HSI clock 32 MHz 173 218
24 MHz 151 194
228
200
233 193 239
204 169 211
251
219
257
225
8 MHz 73 97 99 103 88 105 110 116
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Electrical characteristics STM32F31xx
1. Current consumption from the V
PLL is off, I
DDA
DDA
supply is independent of whether the peripherals are on or off. Furthermore when the
is independent from the frequency.
2. Data based on characterization results, not tested in production.
Table 28. Typical and maximum V
DD
consumption in Stop mode
Max
(1)
Symbol Parameter Conditions Typ@V
DD
(V
DD
=V
DDA
=1.8V)
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DD
Supply current in
Stop mode
All oscillators
OFF
6.6
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
31.1
(2) 560.5
1225.8
µA
Table 29. Typical and maximum V
DDA
consumption in Stop mode
Typ@V
DDA
(V
DD
= 1.8V) Max
(1)
Symbol Parameter Conditions
1.8 V 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DDA
Supply current in
Stop mode
All oscillators
OFF
0.76 0.78 0.80 0.83 0.87 0.94 1.01
1. Data based on characterization results and tested in production.
3.2
5.3
7.9
µA
Typical current consumption
The MCU is placed under the following conditions:
• V
DD
= 1.8 V, V
DDA
= 3.3 V
• All I/O pins available on each package are in analog input configuration
• The Flash access time is adjusted to f
HCLK
frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON
• When the peripherals are enabled, f
APB1
= f
AHB/2
, f
APB2
= f
AHB
• PLL is used for frequencies greater than 8 MHz
• AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
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STM32F31xx Electrical characteristics
Table 30. Typical current consumption in Run mode, code with data processing running from
Flash
Typ
Symbol Parameter Conditions f
HCLK Peripherals enabled
Peripherals disabled
Unit
I
DD
Supply current in
Run mode from
V
DD
supply
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
58.6
52.6
40.6
27.6
21.1
14.3
7.2
4.1
2.3
1.5
1.0
0.7
26.5
6.8
3.5
2.1
1.3
23.7
18.5
12.7
9.9
0.9
0.7
0.5
mA
I
DDA
(1) (2)
Supply current in
Run mode from
V
DDA
supply
Running from HSE crystal clock 8 MHz, code executing from
Flash
239.0
210.3
157.0
108.1
84.4
60.8
1.0
1.0
1.0
1.0
1.0
1.0
µA
1. V
DDA
monitoring is ON.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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Electrical characteristics STM32F31xx
Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ
Symbol Parameter Conditions f
HCLK Peripherals enabled
Peripherals disabled
Unit
I
DD
Supply current in
Sleep mode from
V
DD
supply
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
42.5
9.8
4.8
2.9
1.7
1.2
38.0
28.8
19.4
14.6
0.9
0.7
6.5
1.6
0.8
0.6
0.5
0.5
5.8
4.4
3.0
2.3
0.5
0.5
mA
I
DDA
(1) (2)
Supply current in
Sleep mode from
V
DDA
supply
Running from HSE crystal clock 8 MHz, code executing from
Flash or RAM
239.0
210.3
157.0
108.1
84.4
60.8
1.0
1.0
1.0
1.0
1.0
1.0
µA
1. V
DDA
monitoring is ON
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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STM32F31xx Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in
Table 49: I/O static characteristics .
For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.
I/O dynamic current consumption
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:
I
SW
=
V
DD
× f
SW
× C where
I
SW
is the current sunk by a switching I/O to charge/discharge the capacitive load
V
DD
is the MCU supply voltage f
SW
is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = C
INT
+ C
EXT
+C
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
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Electrical characteristics STM32F31xx
Symbol
I
SW
Table 32. Switching output I/O current consumption
Parameter Conditions
(1)
I/O toggling frequency (f
SW
)
2 MHz
I/O current consumption
V
DD
= 1.8 V
C ext
C = C
INT
= 0 pF
+ C
EXT
+ C
S
V
DD
C ext
C = C
INT
= 1.8 V
= 10 pF
+ C
EXT
+C
S
V
DD
C ext
C = C
INT
= 1.8 V
= 22 pF
+ C
EXT
+C
S
V
DD
C ext
C = C
INT
= 1.8 V
= 33 pF
+ C
EXT
+ C
S
V
DD
C ext
C = C
INT
= 1.8 V
= 47 pF
+ C
EXT
+ C
S
4 MHz
8 MHz
18 MHz
36 MHz
48 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
48 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
Typ
0.94
1.97
3.62
0.28
0.55
1.15
2.42
0.36
0.75
1.59
3.25
0.23
0.45
0.25
0.57
1.16
2.45
3.03
0.19
0.10
0.17
0.40
0.78
1.51
2.06
0.14
Unit
1. CS = 5 pF (estimated value). Obsolete Product(s) - Obsolete Product(s) mA
64/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
On-chip peripheral current consumption
The MCU is placed under the following conditions:
• all I/O pins are in analog input configuration
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• ambient operating temperature at 25°C and V
DD
= 1.8 V, V
DDA
= 3.3 V.
Table 33. Peripheral current consumption
Typical consumption (1)
Peripheral
BusMatrix
(2)
DMA1
DMA2
CRC
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
3.3
3.0
TSC 5.5
ADC1&2 17.3
ADC3&4 18.8
APB2-Bridge (3)
3.6
SYSCFG 7.3
TIM1
SPI1
10.0
10.3
2.2
8.8
40.0
8.8
I
DD
5.6
15.3
12.5
2.1
Unit
µA/MHz
TIM8 36.4
USART1
TIM15
23.3
Obsolete Product(s) - Obsolete Product(s)
TIM16 10.1
11.0
TIM17
APB1-Bridge
6.1
TIM2
TIM3
TIM4
49.1
38.8
38.3
DocID024472 Rev 1 65/124
Electrical characteristics STM32F31xx
Table 33. Peripheral current consumption (continued)
Typical consumption (1)
Peripheral
I
DD
TIM6
TIM7
WWDG
SPI2
SPI3
USART2
USART3
UART4
UART5
I2C1
I2C2
CAN
PWR
DAC
40.2
36.5
30.8
10.5
9.7
12.1
6.4
40.4
40.0
41.9
10.4
33.4
5.7
15.4
Unit
µA/MHz
1. The power consumption of the analog part (I
DDA
) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
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STM32F31xx
6.3.5
Electrical characteristics
Wakeup time from low-power mode
The wakeup times given in Table 34
are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:
• For Stop or Sleep mode: the wakeup event is WFE.
• WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V
DD voltage conditions summarized in
supply
Symbol t
WUSTOP t
WUSLEEP
Table 34. Low-power mode wakeup timings
Parameter
Wakeup from Stop mode
Typ @V
DD
= 1.8 V, V
DDA
= 3.3V Max
3.8
5.3
Wakeup from Sleep mode 6
Unit
µs
CPU clock cycles
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Electrical characteristics STM32F31xx
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.13
. However, the
recommended clock input waveform is shown in Figure 12 .
Symbol
Table 35. High-speed external user clock characteristics
Parameter f
HSE_ext
User external clock source frequency
(1)
V
HSEH
V
HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
(1)
(1)
1. Guaranteed by design, not tested in production.
Conditions Min
1
0.7V
DD
V
SS
15
-
Typ Max Unit
8
-
-
-
-
32
V
DD
0.3V
DD
-
20
MHz
V ns
Figure 12. High-speed external clock source AC timing diagram
T7(3%(
6(3%(
6(3%,
TR(3%
T7(3%,
T
4(3%
TF(3%
-36
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STM32F31xx Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.13
. However, the
recommended clock input waveform is shown in Figure 13
Symbol
Table 36. Low-speed external user clock characteristics
Parameter f
LSE_ext
V
LSEH
User External clock source frequency
(1)
OSC32_IN input pin high level voltage
V
LSEL
OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)
OSC32_IN high or low time
OSC32_IN rise or fall time
(1)
(1)
1. Guaranteed by design, not tested in production.
Conditions Min
0.7V
DD
V
SS
450
-
-
Typ
32.768
-
-
-
-
Max
1000
V
DD
0.3V
DD
-
50
Unit kHz
V ns
Figure 13. Low-speed external clock source AC timing diagram
T7,3%(
6,3%(
6,3%,
TR,3%
4,3%
TF,3%
T7,3%,
-36
Obsolete Product(s) - Obsolete Product(s)
T
DocID024472 Rev 1 69/124
Electrical characteristics STM32F31xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in
application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Symbol
Table 37. HSE oscillator characteristics
Parameter Conditions
(1)
Min
(2)
Typ Max
Unit f
OSC_IN
R
F
Oscillator frequency
Feedback resistor
4
-
8
200
32 MHz k Ω
I
DD
HSE current consumption
During startup
(3)
V
DD
=1.8 V, Rm= 30 Ω ,
CL=10 pF@8 MHz
V
DD
=1.8 V, Rm= 45 Ω ,
CL=10 pF@8 MHz
V
DD
=1.8 V, Rm= 30 Ω ,
CL=10 pF@32 MHz
-
-
-
-
0.4
0.5
0.8
8.5
-
-
mA
V
DD
=1.8 V, Rm= 30 Ω ,
CL=10 pF@32 MHz
V
DD
=1.8 V, Rm= 30 Ω ,
CL=10 pF@32 MHz
-
1
1.5
-
g m t
SU(HSE)
(4)
Oscillator transconductance
Startup time
Startup
V
DD
is stabilized
10
-
-
2 -
mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the t
SU(HSE)
startup time
4. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
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STM32F31xx
Note:
Electrical characteristics
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see
). C
L1
and C
L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
.
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 14. Typical application with an 8 MHz crystal
2ESONATORWITH
INTEGRATEDCAPACITORS
#,
/3#?).
F(3%
-( Z
RESONATOR
2&
"IAS
CONTROLLED
GAIN
#,
2%84
/3#?/5 4
-36
1. R
EXT
value depends on the crystal characteristics.
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DocID024472 Rev 1 71/124
Electrical characteristics STM32F31xx
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in
application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Symbol
Table 38. LSE oscillator characteristics (f
LSE
= 32.768 kHz)
Parameter Conditions
(1)
Min
(2)
Typ Max
(2)
Unit
I
DD
LSE current consumption
LSEDRV[1:0]=00 lower driving capability
LSEDRV[1:0]=01 medium low driving capability
LSEDRV[1:0]=10 medium high driving capability
LSEDRV[1:0]=11 higher driving capability
LSEDRV[1:0]=00 lower driving capability
-
-
-
-
5
0.5
-
-
-
-
0.9
1
1.3
1.6
-
µA g m
Oscillator transconductance
LSEDRV[1:0]=01 medium low driving capability
LSEDRV[1:0]=10 medium high driving capability
8
15 -
-
-
-
µA/V
LSEDRV[1:0]=11 higher driving capability
25 t
SU(LSE)
(3)
Startup time V
DD
is stabilized 2 s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.
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STM32F31xx
Note:
Electrical characteristics
Figure 15. Typical application with a 32.768 kHz crystal
2ESONATORWITH
INTEGRATEDCAPACITORS
#,
/3#?).
F,3%
K( Z
RESONATOR
$RIVE
PROGRAMMABLE
AMPLIFIER
/3#?/5 4
#,
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 73/124
Electrical characteristics
6.3.7 Internal clock source characteristics
STM32F31xx
The parameters given in
Table 39 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22
.
High-speed internal (HSI) RC oscillator
Symbol
Table 39. HSI oscillator characteristics (1)
Parameter Conditions f
HSI
TRIM
DuCy
(HSI)
Frequency
HSI user trimming step
Duty cycle
ACC
HSI
Accuracy of the HSI oscillator (factory calibrated)
T
A
= –40 to 105 °C
T
A
= –10 to 85 °C
T
A
= 0 to 70 °C
T
A
= 25 °C
I t su(HSI)
DD(HSI)
HSI oscillator startup time
HSI oscillator power consumption
1. V
DDA
= 3.3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Min
-
-
45
(2)
–3.8
(3)
–2.9
(3)
-
–1
1
(2)
-
Typ
-
80
-
-
-
-
-
8
-
Figure 16. HSI oscillator accuracy characterization results
!##
(3)
Max
-
1
(2)
55
(2)
4.6
(3)
2.9
(3)
-
1
2
(2)
100
(2)
Unit
MHz
%
%
%
%
%
%
µs
µA
-!8
-).
4!; #=
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1. The above curves are based on characterisation results, not tested in production
DocID024472 Rev 1
-36
STM32F31xx Electrical characteristics
Low-speed internal (LSI) RC oscillator
Symbol
Table 40. LSI oscillator characteristics
(1)
Parameter Min f
LSI t su(LSI)
(2)
I
DD(LSI)
(2)
Frequency 30
LSI oscillator startup time
LSI oscillator power consumption
1. V
DDA
= 3.3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
-
-
Typ
40
-
0.75
Max
50
85
1.2
Unit kHz
µs
µA
The parameters given in
Table 41 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22
.
Table 41. PLL characteristics
Value
Symbol f
PLL_IN
Parameter
PLL input clock
(1)
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
Cycle-to-cycle jitter
Min
1
(2)
40 (2)
16
(2)
-
-
Typ
-
-
-
-
-
Unit f
PLL_OUT t
LOCK
Jitter
Max
24
(2)
60 (2)
72
200
(2)
300
(2)
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f
PLL_OUT
.
2. Guaranteed by design, not tested in production.
MHz
%
MHz
µs ps
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Electrical characteristics STM32F31xx
Flash memory
The characteristics are given at T
A
= –40 to 105 °C unless otherwise specified.
Symbol
Table 42. Flash memory characteristics
Parameter Conditions t t
I prog
ERASE t
ME
DD
16-bit programming time T
A
= –40 to +105 °C
Page (2 KB) erase time T
A
= –40 to +105 °C
Mass erase time T
A
= –40 to +105 °C
Write mode
Supply current
Erase mode
1. Guaranteed by design, not tested in production.
Min
40
20
20
-
-
Typ Max
(1)
53.5
-
-
-
-
60
40
40
10
12
Unit
µs ms ms mA mA
Symbol
Table 43. Flash memory endurance and data retention
Value
Parameter Conditions
Min
(1)
N t
END
RET
Endurance
Data retention
T
A
= –40 to +85 °C (6 suffix versions)
T
A
= –40 to +105 °C (7 suffix versions)
1 kcycle (2) at T
A
= 85 °C
1 kcycle
(2)
at T
A
= 105 °C
10 kcycles (2) at T
A
= 55 °C
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
10
30
10
20
Unit kcycles
Years
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STM32F31xx Electrical characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V
DD
V
SS compliant with the IEC 61000-4-4 standard.
and
through a 100 pF capacitor, until a functional disturbance occurs. This test is
A device reset allows normal operations to be resumed.
The test results are given in
. They are based on the EMS levels and classes defined in application note AN1709.
Symbol
Table 44. EMS characteristics
Parameter Conditions
Level/
Class
V
FESD
V
EFTB
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V pins to induce a functional disturbance
SS
V
DD
= 1.8 V, LQFP100, T
A f
HCLK
= 72 MHz
= +25°C, conforms to IEC 61000-4-2
V
DD
= 1.8 V, LQFP100, T
A f
HCLK
= 72 MHz
= +25°C, conforms to IEC 61000-4-4
2B
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
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• Critical Data corruption (control registers...)
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Electrical characteristics STM32F31xx
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 45. EMI characteristics
Symbol Parameter
S
EMI
Conditions
Monitored frequency band
Peak level
V
DD
= 1.8 V, T
A
= 25 °C,
LQFP100 package compliant with IEC
61967-2
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
Max vs. [f
HSE
/f
HCLK
]
8/72 MHz
7
16
23
4
Unit dBµV
-
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.
Symbol
Table 46. ESD absolute maximum ratings
Ratings Conditions Class
Maximum value (1)
Unit
2 2000 voltage (human body model)
V
ESD(CDM)
Electrostatic discharge voltage (charge device model)
T
A
= +25 °C, conforming to JESD22-C101
1. Data based on characterization results, not tested in production.
II 500
V
78/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Symbol
LU
Parameter
Table 47. Electrical sensitivities
Conditions
Static latch-up class T
A
= +105 °C conforming to JESD78A
Class
II level A
As a general rule, current injection to the I/O pins, due to external voltage below V
SS above V
DD
or
(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation).
The test results are given in
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Electrical characteristics
Note:
STM32F31xx
Symbol
I
INJ
Table 48. I/O current injection susceptibility
Functional susceptibility
Description
Negative injection
Positive injection
Unit
Injected current on BOOT0
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5 with induced leakage current on other pins from this group less than -50 µA
Injected current on PB0, PB1, PE7, PE8, PE9, PE10,
PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14,
PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than -50 µA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13,
PE14, PE15, PB12, PB13, PB14, PB15, PD8, PD9,
PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than 400 µA
Injected current on any other FT and FTf pins
Injected current on any other pins
– 0
– 5
– 5
-
– 5
– 5
NA
-
-
+5
NA
+5 mA
It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
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STM32F31xx Electrical characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49
are derived from tests
performed under the conditions summarized in Table 22
. All I/Os are CMOS and TTL compliant.
Symbol Parameter
Table 49. I/O static characteristics
Conditions Min Typ Max Unit
V
IL
V
IH
V hys
Low level input voltage
High level input voltage
Schmitt trigger hysteresis
TC and TTa I/O
FT and FTf I/O
BOOT0
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
-
-
-
-
0.445 V
DD
+0.398
(1)
0.5 V
DD
+0.2
(1)
0.2 V
DD
+0.95
(1)
0.7 V
DD
(2)
-
-
-
-
-
-
-
-
200
(1)
100
(1)
300
(1)
0.3 V
DD
+0.07
(1)
0.475 V
DD
-0.2 (1)
0.3 V
DD
–0.3
(1)
0.3 V
DD
(2)
-
-
-
-
-
-
mV
I lkg
Input leakage current
(3)
TC, FT, FTf and POR I/O
TTa I/O in digital mode
V
SS
≤ V
IN
≤ V
DD
TTa I/O in digital mode
V
DD
≤ V
IN
≤ V
DDA
TTa I/O in analog mode
V
SS
≤ V
IN
≤ V
DDA
FT and FTf I/O
(4)
V
DD
≤ V
IN
≤ 5 V
V
DDA
POR
≤ V
IN
≤ 5 V
-
-
-
-
-
-
-
-
-
±0.1
1
±0.2
10
10
µA
R
PU
R
PD
Weak pull-up equivalent resistor
Weak pull-down equivalent resistor
(5)
(5)
V
IN
= V
SS
V
IN
= V
DD
25
25
40
40
55
Obsolete Product(s) - Obsolete Product(s)
55 k Ω k Ω
C
IO
I/O pin capacitance 5 -
1. Data based on design simulation.
2. Tested in production.
.
4. To sustain a voltage higher than V
DD
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
pF
V
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Electrical characteristics STM32F31xx
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters.
Figure 17. TC and TTa I/O input characteristics
V
IL
/V
IH
(V)
V
IHmin
2.0
1.3
Tested in production
CMOS standard requirements V
IHmin
= 0.7 V
DD
V
IHmin
= 0.445V
DD
+0.398
Based on design simulations
DD
+0.07
V ILmax
= 0.3V
Based on design simulations
Area not determined
CMOS standard requirements V
ILmax
= 0.3V
DD V
ILmax
0.7
0.6
Tested in production
V
DD
(V)
2.0
2.7
3.0
3.3
3.6
MS30255V2
Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics
V
IL
/V
IH
(V)
2.0
1.0
0.5
2.0
Tested in production
CMOS standard requirements V
IHmin
= 0.7 V DD
Area not determined
V IHmin
= 0.5V
DD
+0.2
Based on design simulations
DD
-0.2
V
ILmax
= 0.475V
Based on design simulations
CMOS standard requirements V
ILmax
= 0.3V
DD
Tested in production
V
DD
(V)
3.6
MS30257V2
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STM32F31xx Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V
OL/
V
OH
).
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in
:
• The sum of the currents sourced by all the I/Os on V
DD, consumption of the MCU sourced on V
Σ I
VDD
DD, plus the maximum Run cannot exceed the absolute maximum rating
• The sum of the currents sunk by all the I/Os on V
SS consumption of the MCU sunk on V
Σ I
VSS
(see
SS
plus the maximum Run
cannot exceed the absolute maximum rating
Output voltage levels
Unless otherwise specified, the parameters given in Table 50
are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 22 . All I/Os (FT, TTa and Tc unless otherwise specified) are CMOS and TTL
compliant.
Symbol
Table 50. Output voltage characteristics
Parameter Conditions Min Max Unit
V
V
V
OL
(1)
OH
(2)
OLFM+
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
I
IO
= +4 mA
1.65 V < V
DD
< 1.95 V
I
IO
= -4 mA
1.65 V < V
DD
< 1.95 V
Output low level voltage for an FTf I/O pin in
FM+ mode V
DD
I
IO
= +10 mA
= 1.65 V to 1.95 V
V
DD
-
-
– 0.4
0.4
-
0.4
1. The I
I
IO
IO
(I/O ports and control pins) must not exceed Σ I
IO(PIN)
.
2. The I of I
IO
IO
(I/O ports and control pins) must not exceed Σ I
IO(PIN)
.
3. Guaranted by Design, not tested in production.
V
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Electrical characteristics STM32F31xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in
Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in
.
Table 51. I/O AC characteristics (1)
OSPEEDRy [1:0] value
(1)
Symbol Parameter Conditions Min Max Unit x0
01
11
FM+ configuration
(4)
f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out t
EXTIpw
Maximum frequency (2)
Output high to low level fall time
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V -
-
1
125
(3)
Output low to high level rise time
Maximum frequency
Output high to low level fall time
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V -
-
125
4
(3)
62.5
(3)
(3)
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V
Output low to high level rise time
Maximum frequency
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V -
Output high to low level fall time
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V -
62.5
(3)
10
25
(3)
(3)
MHz ns
MHz ns
MHz
Output low to high level rise time
Maximum frequency
Output high to low level fall time
Output low to high level rise time
Pulse width of external signals detected by the
EXTI controller
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V -
C
L
= 50 pF, V
DD
= 1.65 V to 1.95 V
-
-
-
10
25
0.5
16
44
(3)
(4)(3)
ns
MHz ns ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 19 .
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4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F30x and STM32F31x reference manual
RM0316 for a description of FM+ I/O mode configuration.
84/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Figure 19. I/O AC characteristics definition
10%
50%
90% 10%
50%
90%
EXT ERNAL
OUTPUT
ON 50pF tr(IO)out
T tr(IO)out
Maximum fr equency is achieved if (tr + tf) £ 2/3) T and if the duty cycle is (45-55%) when loaded by 50pF ai14131
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R
PU
(see
Unless otherwise specified, the parameters given in Table 52
are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in
Symbol
Table 52. NRST pin characteristics
Parameter Conditions Min Typ Max
V
IL(NRST)
(1)
NRST Input low level voltage -
0.3V
0.07
V
IH(NRST)
(1)
NRST Input high level voltage
0.445V
0.398
+
-
V hys(NRST)
R
PU
V
F(NRST)
(1)
V
NF(NRST)
(1)
NRST Schmitt trigger voltage hysteresis
Weak pull-up equivalent resistor
(2)
NRST Input filtered pulse
NRST Input not filtered pulse
V
IN
= V
SS
-
25
-
700
(1)
200
40
-
-
55
100
(1)
-
-
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)
.
+
Unit
V mV k Ω ns ns
Figure 20. Recommended NRST pin protection
%XTERNAL
RESETCIRCUIT
.234
6$$ Obsolete Product(s) - Obsolete Product(s)
205
)NTERNAL2ESET
&ILTER
&
-36
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
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Electrical characteristics
Table 52 . Otherwise the reset will not be taken into account by the device.
STM32F31xx
The NPOR pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, Rpu (see
DDA
supply.
Unless otherwise specified, the parameters given in Table 53
are derived from tests performed under ambient temperature and V
DDA
supply voltage conditions summarized in
Symbol (1)
Table 53. NPOR pin characteristics
Parameter Conditions Min Typ Max Unit
V
IL(NPOR)
NPOR Input low level voltage
0.475V
DDA
- 0.2
V
IH(NPOR)
NPOR Input high level voltage
V
0.5V
DDA
+ 0.2
V hys(NPOR)
NPOR Schmitt trigger voltage hysteresis
Weak pull-up equivalent resistor
(2)
100 mV
R
PU
V
IN
= V
SS
25 40 55
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).
k Ω
The parameters given in
Table 54 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Symbol Parameter
Table 54. TIMx (1)(2) characteristics
Conditions Min Max Unit
1 t
TIMxCLK ns t res(TIM)
Timer resolution time
f
TIMxCLK
= 72 MHz f
TIMxCLK x= 1.8
= 144 MHz,
13.9
6.95
-
ns f
TIMxCLK
= 72 MHz f
TIMxCLK
/2 f
EXT
Timer external clock
TIMx (except TIM2)
0
0
-
36
16
MHz
MHz
Res
TIM
Timer resolution bit
TIM2 32
1 65536 t
TIMxCLK
µs t
COUNTER
16-bit counter clock period
f
TIMxCLK
= 72 MHz 0.0139
f
TIMxCLK x= 1.8
= 144 MHz,
0.0069
910
455 µs
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STM32F31xx Electrical characteristics
Symbol
Table 54. TIMx (1)(2) characteristics (continued)
Parameter Conditions Min Max Unit t
MAX_COUNT
Maximum possible count with 32-bit counter f
TIMxCLK
= 72 MHz f
TIMxCLK x= 1.8
= 144 MHz,
-
-
-
65536 × 65536 t
TIMxCLK
59.65
29.825
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, TIM16 and TIM17 timers.
2. Guaranteed by design, not tested in production.
s s
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Electrical characteristics STM32F31xx
Table 55. IWDG min/max timeout period at 40 kHz (LSI) (1)
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4
/8
/16
/32
/64
/128
/256
0
1
2
3
4
5
7
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1638.4
3276.8
6553.6
13107.2
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler
Table 56. WWDG min-max timeout value @72 MHz (PCLK)
(1)
WDGTB Min timeout value Max timeout value
1
2
4
8
0
1
2
3
1. Guaranteed by design, not tested in production.
0.05687 3.6409
0.1137 7.2817
0.2275 14.564
0.4551 29.127
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STM32F31xx Electrical characteristics
I
2
C interface characteristics
The I
2
C interface meets the requirements of the standard I
2
C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V
DD disabled, but is still present.
is
The I
2
C characteristics are described in
. Refer also to
and SCL).
Symbol
Table 57. I2C timings specification (see I2C specification, rev.03, June 2007) (1)
Standard mode Fast mode Fast Mode Plus
Parameter
Min Max Min Max Min Max
Unit t t f
SCL
LOW
HIGH t r
SCL clock frequency
Low period of the SCL clock
High Period of the SCL clock
Rise time of both SDA and SCL signals t f
Fall time of both SDA and SCL signals t
HD;DAT
Data hold time t
VD;DAT
Data valid time t
VD;ACK
Data valid acknowledge time t
SU;DAT
Data setup time t
HD:STA
Hold time (repeated) START condition
0
4.7
4
-
-
0
-
-
250
4.0
100
-
1000
300
-
3.45
(2)
-
-
-
-
0
-
-
100
0
1.3
0.6
0.6
400
-
300
300
-
-
-
0
0.5
0.26
-
-
0
-
-
50
0.26
1000 KHz
µs
µs
120
120
-
-
t
SU:STA t
SU:STO t
BUF
Set-up time for a repeated START condition
Set-up time for STOP condition
Bus free time between a
STOP and START condition
4.7
4.0
4.7
-
-
0.6
0.6
1.3
-
-
0.26
0.26
0.5
-
-
Capacitive load for each bus line 400 400 550 C b
Obsolete Product(s) - Obsolete Product(s) production.
pF
2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time.
µs
µs
µs ns ns
µs
µs
µs ns
µs
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Electrical characteristics
Symbol
Table 58. I2C analog filter characteristics (1)
Parameter t
SP
Pulse width of spikes that are suppressed by the analog filter
1. Guaranteed by design, not tested in production.
Min
50
Max
260
Figure 21. I
2
C bus AC waveforms and measurement circuit
VDD_I2C VDD_I2C
STM32F31xx
Unit ns
Rp Rp
MCU
I2C bus
Rs
Rs
SDA
1. Rs: Series protection resistors, Rp: Pull-up resistors, VDD_I2C: I2C bus supply
.
Obsolete Product(s) - Obsolete Product(s)
90/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
SPI/I
2
S characteristics
Unless otherwise specified, the parameters given in Table 59
for SPI or in
2 S are derived from tests performed under ambient temperature, f
supply voltage conditions summarized in Table 22 .
PCLKx frequency and V
DD
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I 2 S).
Symbol
Table 59. SPI characteristics (1)
Parameter Conditions Min Max Unit
1/t f
SCK c(SCK)
SPI clock frequency
Master mode, C = 30pF
Slave mode -
18
18
MHz t t r(SCK) f(SCK)
DuCy(SCK)
SPI clock rise and fall time
SPI slave input clock duty cycle
Capacitive load: C = 30 pF
Slave mode
-
30
8
70 ns
% t su(NSS) t h(NSS) t w(SCKH) t w(SCKL)
NSS setup time
NSS hold time
SCK high and low time
Slave mode
Slave mode
Master mode, f presc = 4
PCLK
= 36 MHz,
2Tpclk
4Tpclk
Tpclk/2
- 3
-
-
Tpclk/2
+ 3 t su(MI) t su(SI)
Data input setup time
Master mode 5.5
-
Slave mode 6.5
t h(MI) t h(SI) t a(SO)
(2) t dis(SO)
(3) t v(SO) t v(MO) t h(SO) t h(MO)
Data input hold time
Master mode
Slave mode
Data output access time Slave mode, f
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
PCLK
= 24 MHz
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
5
5
0
0
-
-
15
4 -
-
-
-
4Tpclk
24
39
3
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
ns
DocID024472 Rev 1 91/124
Electrical characteristics
Figure 22. SPI timing diagram - slave mode and CPHA = 0
NSS input tc(SCK) tSU(NSS)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1 tw(SCKH) tw(SCKL) ta(SO)
MISO
OUT P UT tsu(SI)
MOSI
I NPUT tv(SO)
MS B O UT
M SB IN th(SI) th(SO)
BI T6 OUT
B I T1 IN th(NSS) tr(SCK) tf(SCK)
LSB OUT tdis(SO)
LSB IN
Figure 23. SPI timing diagram - slave mode and CPHA = 1
(1)
STM32F31xx ai14134c
NSS input tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 tw(SCKH) tw(SCKL) tc(SCK) th(NSS)
MISO
OUT P UT ta(SO) tsu(SI)
MOSI
I NPUT tv(SO)
MS B O UT th(SI)
M SB IN th(SO)
BI T6 OUT
B I T1 IN tr(SCK) tf(SCK) tdis(SO)
LSB OUT
LSB IN ai14135
1. Measurement points are done at 0.5V
DD
and with external C
L
= 30 pF.
Obsolete Product(s) - Obsolete Product(s)
92/124 DocID024472 Rev 1
STM32F31xx
Figure 24. SPI timing diagram - master mode (1)
Electrical characteristics
.33INPUT
(IGH
#0(!
#0/,
#0(!
#0/,
TC3#+
#0(!
#0/,
#0(!
#0/,
-)3/
).0 54
-/3)
/54054
TSU-)
TW3#+(
TW3#+,
-3 ").
TH-)
- 3"/54
TV-/
") 4).
" ) 4/54
TH-/
TR3#+
TF3#+
,3").
,3"/54
AI6
1. Measurement points are done at 0.5V
DD
and with external C
L
= 30 pF.
Table 60. I
2
S characteristics
(1)
Symbol Parameter Conditions Min Max
1/t t t f
CK c(CK) t r(CK) t f(CK) w(CKH) w(CKL)
I
2
I
I
2
I
S clock frequency
S clock rise and fall
2
2 time
S clock high time
S clock low time
Master data: 16 bits, audio freq=48 kHz
Slave
Capacitive load
C
L
= 30 pF
Master f
PCLK
= 36 MHz, audio frequency =
48 kHz
1.496
0
-
331
332
1.503
12.288
8
-
t v(WS)
WS valid time Master mode 4 t su(WS) t t h(WS) h(WS)
WS hold time
WS setup time
WS hold time
Master mode
Slave mode
Slave mode
4
4
0 -
-
-
Duty Cycle
I 2 S slave input clock duty cycle
Slave mode 30 70
Unit
MHz ns
%
DocID024472 Rev 1 93/124
Electrical characteristics STM32F31xx
Symbol
Table 60. I 2 S characteristics (1) (continued)
Parameter Conditions t t t t t t t su(SD_MR) t su(SD_SR) h(SD_MR) h(SD_SR) v(SD_ST) h(SD_ST) v(SD_MT) h(SD_MT)
Data input setup time
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
1. Data based on characterization results, not tested in production.
Min
12
2
0
0
9
2
Figure 25. I
2
S slave timing diagram (Philips protocol)
(1) tc(CK)
Max
29
3
CPOL = 0
Unit ns
CPOL = 1 th(W
S ) tw(CKH) tw(CKL)
W S inp u t t su (W S )
S Dtr a n s mit
L S B tr a n s mit
(2) t su ( S D_ S R)
L S B receive
(2)
M S B tr a n s mit
M S B receive tv(
S D_ S T)
Bitn tr a n s mit th(
S D_ S R)
Bitn receive th(
S D_ S T)
L S B tr a n s mit
L S B receive S Dreceive a i14881 b
1. Measurement points are done at 0.5V
DD
and with external C
L
=30 pF
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Obsolete Product(s) - Obsolete Product(s)
94/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Figure 26. I 2 S master timing diagram (Philips protocol) (1) tf(CK) tr(CK) tc(CK)
CPOL = 0 tw(CKH)
CPOL = 1 tv(W
S ) tw(CKL) th(W
S )
S Dtr a n s mit L S B tr a n s mit
(2) t su ( S D_MR)
L S B receive
(2)
M S B tr a n s
M S B receive mit tv(
S D_MT)
Bitn tr a n s mit th(
S D_MR)
Bitn receive th(
L S
S D_MT)
B tr a n s
L S B receive mit
S Dreceive a i14884 b
1. Measurement points are done at 0.5V
DD
and with external C
L
=30 pF
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
CAN (controller area network) interface
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
Unless otherwise specified, the parameters given in
are guaranteed by design, with conditions summarized in
Symbol Parameter
Table 61. ADC characteristics
Conditions Min Typ Max Unit
V
DDA
Analog supply voltage for Obsolete Product(s) - Obsolete Product(s)
ADC clock frequency 0.14
72
V
MHz f
ADC
DocID024472 Rev 1 95/124
Electrical characteristics STM32F31xx
Symbol Parameter
Table 61. ADC characteristics (continued)
Conditions Min Typ Max Unit f
S
(1) f
TRIG
(1)
Sampling rate
External trigger frequency
Resolution = 12 bits,
Fast Channel
Resolution = 10 bits,
Fast Channel
Resolution = 8 bits,
Fast Channel
Resolution = 6 bits,
Fast Channel
f
ADC
= 72 MHz
Resolution = 12 bits
Resolution = 12 bits
0.01
0.012
0.014
0.0175
-
-
-
-
5.14
6
7.2
9
5.14
MSPS
MHz
V
AIN
R
AIN
(1)
C
ADC
(1)
Conversion voltage range
External input impedance
Internal sample and hold capacitor
-
0
-
-
-
-
-
5
14
V
DDA
100
-
1/f
ADC
V k Ω pF t
CAL
(1) t latr
(1) t latrinj
(1)
Trigger conversion latency
Regular and injected channels without conversion abort
Trigger conversion latency
Injected channels aborting a regular conversion f
ADC
= 72 MHz
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
-
-
-
2.5
-
-
-
1.56
-
-
-
3
-
-
-
µs
Calibration time
CKMODE = 00 f
ADC
= 72 MHz
1.5
0.021
112
2
-
2.5
2
2.25
1/f
ADC
1/f
ADC
1/f
ADC
1/f
ADC
2.125
1/f
ADC
3.5
1/f
ADC
3
3.25
1/f
ADC
1/f
ADC
3.125
1/f
ADC
8.35
µs t
S
(1)
Sampling time
1.5
601.5
1/f
ADC
ADC Voltage Regulator
Start-up time
10 µs
_STUP
Total conversion time f
ADC
= 72 MHz
Resolution = 12 bits
0.19
3.5
µs t
CONV
(1)
(including sampling time)
Obsolete Product(s) - Obsolete Product(s)
1. Data guaranteed by design
14 to 252 (t
S
for sampling + 12.5 for successive approximation)
1/f
ADC
96/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Table 62. Maximum ADC R
AIN
(1)
Resolution
Sampling cycle @
72 MHz
Sampling time [ns] @
72 MHz Fast channels
(2)
R
AIN
max (k Ω )
Slow channels
Other channels
(3)
12 bits
10 bits
1.5
2.5
4.5
7.5
19.5
61.5
181.5
1.5
2.5
4.5
7.5
19.5
61.5
181.5
601.5
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
8354.17
0.082
0.270
0.560
1.20
3.30
10.0
33.0
0.018
0.150
0.470
0.820
2.70
8.20
22.0
82.0
NA
0.082
0.390
0.82
2.70
8.2
27.0
NA
NA
0.220
0.560
1.80
6.80
18.0
68.0
8 bits
601.5
1.5
2.5
4.5
7.5
19.5
61.5
181.5
601.5
1.5
8354.17
20.83
34.72
62.50
104.17
270.83
854.17
2520.83
8354.17
20.83
100.0
0.150
0.390
0.820
1.50
3.90
12.00
39.00
100.00
0.270
82.0
NA
0.180
0.560
1.20
3.30
12.00
33.00
100.00
0.100
2.5
4.5
34.72
62.50
0.560
1.200
0.390
0.820
0.330
0.820
7.5 104.17
2.20 1.80 1.50
6 bits
19.5 270.83
5.60
3.90
61.5
181.5
854.17
2520.83
601.5 8354.17
1. Data based on characterization results, not tested in production
.
2. All fast channels, expect channels on PA2, PA6, PB1, PB12.
18.0
56.0
100.00
15.0
47.0
100.0
12.0
39.0
100.0
68.0
0.039
0.180
0.470
1.00
2.70
8.20
27.00
82.00
0.150
NA
0.100
0.330
0.68
2.20
6.8
22.0
NA
0.022
0.180
0.470
1.50
4.70
15.0
47.0
DocID024472 Rev 1 97/124
Electrical characteristics STM32F31xx
3. Channels available on PA2, PA6, PB1 and PB12.
Table 63. ADC accuracy - limited test conditions 1)
(1)(2)
Symbol Parameter Conditions
Min
(3)
Typ
Max
(3)
Unit
ET
EO
EG
ED
EL
ENOB
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
Effective number of bits
ADC clock freq. ≤
Sampling freq. ≤
V
DDA
= V
REF+
= 3.3 V
25°C
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Fast channel 5.1 Ms - ± 3.5
± 6
Slow channel 4.8 Ms - ± 4.5
± 7
Fast channel 5.1 Ms - ± 3.5
± 6
Slow channel 4.8 Ms - ± 3.5
± 6
Fast channel 5.1 Ms - ± 1 ± 5
Slow channel 4.8 Ms - ± 1 ± 5
Fast channel 5.1 Ms - ± 1 ± 3
Slow channel 4.8 Ms - ± 1 ± 3
Fast channel 5.1 Ms - ± 3 ± 6
Slow channel 4.8 Ms - ± 4 ± 6
Fast channel 5.1 Ms - ± 1 ± 2
Slow channel 4.8 Ms - ± 1.5
± 3
Fast channel 5.1 Ms - ± 1 ± 1
Slow channel 4.8 Ms - ± 1 ± 1.5
Fast channel 5.1 Ms - ± 1 ± 1
Slow channel 4.8 Ms - ± 1 ± 1
Fast channel 5.1 Ms - ± 1.5
± 3
Slow channel 4.8 Ms - ± 2 ± 3
Fast channel 5.1 Ms - ± 1 ± 2
Slow channel 4.8 Ms - ± 1 ± 2
Fast channel 5.1 Ms 10.3 10.7
-
Slow channel 4.8 Ms 10.4 10.7
-
Fast channel 5.1 Ms 10.9 11.3
-
Slow channel 4.8 Ms 10.9 11.3
-
LSB bits
Obsolete Product(s) - Obsolete Product(s)
SINAD
Signal-tonoise and distortion
Single ended
Fast channel 5.1 Ms 64 66
Slow channel 4.8 Ms 65 66
dB
Fast channel 5.1 Ms 67 70 ratio Differential
Slow channel 4.8 Ms 67 70 -
98/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Table 63. ADC accuracy - limited test conditions 1) (1)(2) (continued)
Symbol Parameter Conditions
Min
(3)
Typ
Max
(3)
Unit
SNR
THD
Signal-tonoise ratio
Total harmonic distortion
ADC clock freq.
Sampling freq
V
DDA
25°C
≤
= V
REF+
≤ 72 MHz
5 Msps
= 3.3 V
Single ended
Fast channel 5.1 Ms 64 67
Slow channel 4.8 Ms 65 67
Fast channel 5.1 Ms 68 70
Differential
-
Slow channel 4.8 Ms 69 70
Fast channel 5.1 Ms - -75
-
-72
Single ended
-
-
Slow channel 4.8 Ms - -72 -70
Fast channel 5.1 Ms - -80 -74
Differential
Slow channel 4.8 Ms - -76 -71 dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
does not affect the ADC
3. Data based on characterization results, not tested in production.
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 99/124
Electrical characteristics STM32F31xx
Symbol Parameter
Table 64. ADC accuracy - limited test conditions 2) (1)(2)(3)
Conditions Min
(4)
ET
Total unadjusted error
EO Offset error
EG Gain error
ED
EL
ENOB
Differential linearity error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
2 V ≤ V
DDA
, V
REF+
≤ 3.6 V
Integral linearity error
Effective number of bits
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms 10.2
Slow channel 4.8 Ms 10.2
Fast channel 5.1 Ms 10.8
Slow channel 4.8 Ms 10.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
(4)
± 3
± 3
± 1.5
± 1.5
± 4
± 7
± 7
± 7
± 5
± 5
± 4
± 7
± 7
± 7
± 1.5
± 1
± 3
± 3
± 2
± 2
-
-
-
-
Unit
LSB bits
Obsolete Product(s) - Obsolete Product(s)
100/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Table 64. ADC accuracy - limited test conditions 2) (1)(2)(3) (continued)
Symbol Parameter Conditions Min (4) Max (4) Unit
SINAD
SNR
THD
Signal-tonoise and distortion ratio
Signal-tonoise ratio
Total harmonic distortion
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps,
2 V ≤ V
DDA
, V
REF+
≤ 3.6 V
Single
Ended
Differential
Single
Ended
Differential
Single
Ended
Differential
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
64
64
67
67
-
-
-
- dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
does not affect the ADC
3. Better performance may be achieved in restricted V
DDA
, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
-
-
-
-
63
63
67
67
-71
-69
-73
-70
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 101/124
Electrical characteristics STM32F31xx
Symbol Parameter
Table 65. ADC accuracy (1)(2)(3)
Conditions Min
(4)
Max
Unit
ET
EG
ED
EL
ENOB
Total unadjusted error
EO Offset error
Gain error
Differential linearity error
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
1.8 V ≤ V
DDA
, V
REF+
≤ 3.6 V
Integral linearity error
Effective number of bits
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms 10.2
Slow channel 4.8 Ms 10.2
Fast channel 5.1 Ms 10.8
Slow channel 4.8 Ms 10.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
± 3
± 3
± 1.5
± 1.5
± 4
± 7
± 7
± 7
± 7
± 7
± 4
± 8
± 8
± 7
± 1.5
± 1
± 3
± 3
± 2
± 2
-
-
-
-
LSB bits
Fast channel 5.1 Ms 63
Signal-to Single ended noise and
Slow channel 4.8 Ms 63
SINAD distortion ratio Differential
Fast channel 5.1 Ms -
-
67
Obsolete Product(s) - Obsolete Product(s) dB
102/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Symbol Parameter
Table 65. ADC accuracy (1)(2)(3) (continued)
Conditions Min (4) Max (4) Unit
SNR
THD
Signal-tonoise ratio
Total harmonic distortion
ADC clock freq. ≤ 72 MHz,
Sampling freq ≤ 5 Msps,
1.8 V ≤ V
DDA
, V
REF+
≤ 3.6 V
Single ended
Differential
Single ended
Differential
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
64
64
67
67
-
-
-
-
-
-
-
-
-70
-69
-72
-70 dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I accuracy.
INJ(PIN)
and Σ I
INJ(PIN)
in
3. Better performance may be achieved in restricted V
DDA
, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
3
2
5
4
1
7
6
4095
4094
4093
Figure 27. ADC accuracy characteristics
[1LSB
IDEAL
=
V
REF+
4096
V
(or depending on package)]
4096
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
(2)
E
O
E
T
E
L
E
D
(3)
(1)
E
T
=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
1 LSB
IDEAL
0
V
SSA
1 2 3 4 5 6 7 4093 4094 4095 4096
V
DDA ai14395b
DocID024472 Rev 1 103/124
Electrical characteristics
Figure 28. Typical connection diagram using the ADC
VAIN
RAIN(1)
AINx
Cparasitic
6$$!
VT
0.6 V
VT
0.6 V
IL±1 μA
Sample and hold ADC converter
RADC
12-bit converter
CADC
STM32F31xx
-36
1. Refer to Table 61 for the values of R
AIN
.
2. C parasitic this, f
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
ADC
should be reduced.
parasitic
value will downgrade conversion accuracy. To remedy
General PCB design guidelines
Power supply decoupling should be performed as shown in
. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.
Symbol Parameter
Table 66. DAC characteristics
Min Typ Max Unit Comments
V
DDA
R
LOAD
(1)
R
O
(1)
C
LOAD
(1)
Analog supply voltage for
DAC ON
2.4
Resistive load with buffer ON 5
Impedance output with buffer
OFF
Capacitive load -
-
-
-
-
-
3.6 V
-
15
50 k Ω k Ω pF
When the buffer is OFF, the Minimum resistive load between DAC_OUT and V
SS
1.5 M Ω
to have a 1% accuracy is
Maximum capacitive load at
DAC_OUT pin (when the buffer is
ON).
DAC_OUT min
(1)
Obsolete Product(s) - Obsolete Product(s) max
(1)
Lower DAC_OUT voltage with buffer ON
Higher DAC_OUT voltage with buffer ON
0.2 -
-
V
V
DDA
– 0.2
V
It gives the maximum output excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at V
DDA
= 3.6 V and (0x155) and (0xEAB) at V
DDA
2.4 V
=
DAC_OUT min
(1)
Lower DAC_OUT voltage with buffer OFF
DAC_OUT max
(1)
Higher DAC_OUT voltage with buffer OFF
-
0.5
-
mV
It gives the maximum output excursion of the DAC.
V
DDA
– 1LSB V
104/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Symbol
I
DDA
(3)
Parameter
Table 66. DAC characteristics (continued)
DAC DC current consumption in quiescent mode (Standby mode)
(2)
Min Typ
-
-
-
-
Max
380
480
Unit Comments
µA
With no load, middle code (0x800) on the input
µA
With no load, worst code (0xF1C) on the input
DNL
(3)
Differential non linearity
Difference between two consecutive code-1LSB)
±0.5 LSB Given for a 10-bit input code
-
-
-
±2
±1
LSB Given for a 12-bit input code
LSB Given for a 10-bit input code
INL
(3)
Integral non linearity
(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)
±4 LSB Given for a 12-bit input code
Offset
(3)
Offset error
(difference between measured value at Code
(0x800) and the ideal value =
V
DDA
/2) -
-
-
-
-
-
±10
±3
±12 mV
LSB
Given for a 10-bit input code at V
DDA
= 3.6 V
LSB
Given for a 12-bit input code at V
DDA
= 3.6 V
Gain error
(3)
Update rate
(3)
Gain error t
SETTLING
(3)
Settling time (full scale: for a
10-bit input code transition between the lowest and the highest input codes when
DAC_OUT reaches final value ±1LSB
Max frequency for a correct
DAC_OUT change when small variation in the input code (from code i to i+1LSB)
-
-
-
3
-
±0.5
4
1
% Given for a 12-bit input code
µs C
LOAD
≤
LOAD
≥ 5 k Ω
MS/s C
LOAD
≤
LOAD
≥ 5 k Ω t
WAKEUP
(3)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
6.5
10 µs
C
LOAD
≤
LOAD
≥ 5 k Ω input code between lowest and highest possible ones.
PSRR+
(1)
Power supply rejection ratio
(to V
DDA
) (static DC measurement
–67 –40 dB No , C
LOAD
= 50 pF Obsolete Product(s) - Obsolete Product(s)
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved.
3. Data based on characterization results, not tested in production.
DocID024472 Rev 1 105/124
Electrical characteristics STM32F31xx
Figure 29. 12-bit buffered /non-buffered DAC
B u ffered/Nonbu ffered DAC
B u ffer(1)
R
LOAD
12b it digit a l to a n a log converter
DACx_OUT
C
LOAD a i17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
Symbol Parameter
Table 67. Comparator characteristics (1)
Conditions Min Typ Max Unit
V
DDA
V
IN
V
BG
V
SC t
S_SC
Analog supply voltage
Comparator input voltage range
Scaler input voltage
Scaler offset voltage
Scaler startup time from power down
1.65
0
-
-
-
-
-
1.2
±5
-
3.6
V
DDA
-
±10 mV
0.1
ms t
START
Comparator startup time
Startup time to reach propagation delay specification
Ultra-low power mode
-
-
-
2
60
4.5
µs
-
0.7
0.3
1.5
0.6
µs
Propagation delay for
200 mV step with 100 mV overdrive
Low power mode
Medium power mode
High speed mode
V
DDA
≥ 2.7 V
V
DDA
< 2.7 V -
50 100
100 240 ns t
D
Ultra-low power mode 2 7
Low power mode 0.7
2.1
Propagation delay for full
Medium power mode
V
DDA
≥ 2.7 V
V
DDA
< 2.7 V
-
-
0.3
1.2
range step with 100 mV
Obsolete Product(s) - Obsolete Product(s)
High speed mode
90 180
110 300 ns
µs
V offset dV offset
/dT
Comparator offset error
Offset error temperature coefficient
-
± 4
18
± 10 mV
-
µV/°
C
V
106/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Symbol
Table 67. Comparator characteristics (1) (continued)
Parameter Conditions
I
DD(COMP)
V hys
COMP current consumption
Comparator hysteresis
Ultra-low power mode
Low power mode
Medium power mode
High speed mode
No hysteresis
(COMPxHYST[1:0]=00)
Low hysteresis
(COMPxHYST[1:0]=01)
High speed mode
All other power modes
Medium hysteresis
(COMPxHYST[1:0]=10)
High speed mode
All other power modes
High hysteresis
(COMPxHYST[1:0]=11)
High speed mode
All other power modes
1. Data based on characterization results, not tested in production.
Min Typ Max Unit
-
-
-
-
-
3
5
7
9
18
19
1.2
3
10
75
0
8
15
31
1.5
5
15
100
-
13
10
26
19
49
40
µA mV
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 107/124
Electrical characteristics STM32F31xx
Table 68. Operational amplifier characteristics (1)
Parameter Condition Min Typ Symbol Max Unit
V
DDA
CMIR
Analog supply voltage
Common mode input range
2.4
0 -
3.6
V
DDA
V
V
VI
OFFSET
Input offset voltage
Maximum calibration range
After offset calibration
25°C, No Load on output.
All voltage/Temp.
25°C, No Load on output.
All voltage/Temp.
-
-
-
-
-
-
-
4
6
1.6
3 mV
Δ VI
OFFSET
I
LOAD
Input offset voltage drift
Drive current -
5
-
-
500
µV/°C
µA
IDDOPAMP Consumption
No load, quiescent mode
690 1450 µA
CMRR
PSRR
GBW
Common mode rejection ratio
Power supply rejection ratio
Bandwidth
DC
-
73
-
90
117
8.2
-
-
dB dB
MHz
SR
R
LOAD
C
LOAD
Slew rate
Resistive load
Capacitive load
-
4
-
4.7
-
-
-
-
50
V/µs k Ω pF
VOH
SAT
High saturation voltage
R load
= min,
Input at V
DDA
.
R load
= 20K,
Input at V
DDA
.
Rload = min, input at 0V
-
-
-
-
-
100
20
100 mV
VOL
SAT
Low saturation voltage
Rload = 20K, input at 0V.
20 ϕ m Phase margin
Offset trim time: during calibration, minimum time needed between two
-
-
62
-
-
Obsolete Product(s) - Obsolete Product(s)
2
° ms t
OFFTRIM steps to have 1 mV accuracy t
WAKEUP
Wake up time from OFF state.
C
LOAD
R
LOAD
≤
≥
50 pf,
4 k
Follower
Ω, configuration
2.8
5 µs
108/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
Symbol
R network
Table 68. Operational amplifier characteristics (1)
Parameter Condition Min Typ
PGA gain Non inverting gain value
R2/R1 internal resistance values in
PGA mode
(2)
PGA gain error PGA gain error
I bias
OPAMP input bias current
Gain=2
Gain=4
Gain=8
Gain=16 -
-
-
-
-
-
-
-
-1%
-
5.4/5.4
16.2/5.4
37.8/5.4
40.5/2.7
-
-
8
16
2
4
PGA BW
PGA bandwidth for different non inverting gain
PGA Gain = 2,
Cload = 50pF,
Rload = 4 K Ω
PGA Gain = 4,
Cload = 50pF,
Rload = 4 K Ω
PGA Gain = 8,
Cload = 50pF,
Rload = 4 K Ω
PGA Gain = 16,
Cload = 50pF,
Rload = 4 K Ω
@ 1KHz, Output loaded with
4 K Ω
-
-
-
-
4
2
1
0.5
109
Max
-
-
-
-
1%
± 0.2
(3)
-
-
-
-
-
-
-
-
en Voltage noise density
@ 10KHz,
Output loaded with 4 K Ω
43 -
Unit k Ω
µA
MHz
Hz
1. Guaranteed by design, not tested in production.
2. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
Obsolete Product(s) - Obsolete Product(s)
3. Mostly TTa I/O leakage, when used in analog mode.
DocID024472 Rev 1 109/124
Electrical characteristics
Figure 30. OPAMP Voltage Noise versus Frequency
STM32F31xx
Obsolete Product(s) - Obsolete Product(s)
110/124 DocID024472 Rev 1
STM32F31xx Electrical characteristics
6.3.22 Temperature sensor characteristics
Symbol
T
L
(1)
Avg_Slope
(1)
V
25 t
START
(1)
T
S_temp
(1)(2)
Table 69. TS characteristics
Parameter
V
SENSE
linearity with temperature
Average slope
Voltage at 25 °C
Startup time
ADC sampling time when reading the temperature
Min
2.2
-
4.0
1.34
4
Typ
-
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
± 1
4.3
1.43
-
Max
± 2
4.6
1.52
10
-
Table 70. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C,
V
DDA
= 3.3 V
TS ADC raw data acquired at temperature of 110 °C
V
DDA
= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
0x1FFF F7C2 - 0x1FFF F7C3
Unit
°C mV/°C
V
µs
µs
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 111/124
Package characteristics STM32F31xx
7.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Obsolete Product(s) - Obsolete Product(s)
112/124 DocID024472 Rev 1
STM32F31xx Package characteristics
Figure 31. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
C
CCC #
$
$
$
MM
'!5'%0,!.%
,
, +
0).
)$%.4)&)#!4)/.
E
,?-%?6
1. Drawing is not to scale.
Table 71. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
A 1.60
0.063
A1
A2
0.05
1.35
1.40
0.15
1.45
0.002
0.0531
0.0551
0.0059
0.0571
b 0.17
0.22
0.27
0.0067
0.0087
0.0106
c
D
D1
D3
E
0.09
15.80
13.80
15.80
16.00
14.00
12.00
16.00
0.2
16.2
14.2
16.2
0.0035
0.622
0.5433
0.622
0.6299
0.5512
0.4724
0.6299
0.0079
0.6378
0.5591
0.6378
DocID024472 Rev 1 113/124
Package characteristics STM32F31xx
Table 71. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data (continued) inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
0.5433
0.5591
L1
K ccc
E1
E3 e
L
13.80
0.45
14.00
12.00
0.50
0.60
1.00
3.5°
14.2
0.75
0° 7°
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.0177
0°
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.0295
7°
0.0031
Figure 32. Recommended footprint
75 51
76 50
0.5
0.
3
16.7
14.
3
100 26
1.2
1 25
12.
3
16.7
a i14906 b
1. Dimensions are in millimeters.
Obsolete Product(s) - Obsolete Product(s)
114/124 DocID024472 Rev 1
STM32F31xx Package characteristics
Figure 33. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline
3%!4).'
0,!.%
#
C
MM
'!5'%0,!.%
CCC #
+
$
$
$
,
,
B
0).
)$%.4)&)#!4)/.
1. Drawing is not to scale.
E
7?-%?6
Obsolete Product(s) - Obsolete Product(s) millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
A
A1
A2 b
0.05
1.350
0.17
1.40
0.22
1.60
0.15
1.45
0.27
0.0020
0.0531
0.0067
0.0551
0.0087
0.0630
0.0059
0.0571
0.0106
DocID024472 Rev 1 115/124
Package characteristics STM32F31xx
Table 72. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max
D3
E
E1
E3 c
D
D1
L1
K e
L ccc
0.09
11.80
9.80
11.80
9.80
0.20
12.00
10.00
12.20
10.20
7.50
12.00
10.00
7.50
12.20
10.20
0.45
0.50
0.60
1.00
0° 3.5°
0.75
0.0035
0.4646
0.3858
0.4646
0.3858
0.0177
7° 0°
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
0.0236
0.0394
3.5°
0.0079
0.4803
0.4016
0.4803
0.4016
0.0295
7°
0.0031
Figure 34. Recommended footprint
Obsolete Product(s) - Obsolete Product(s)
AIB
1. Dimensions are in millimeters.
116/124 DocID024472 Rev 1
STM32F31xx Package characteristics
Figure 35. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
CCC #
$
$
$
MM
'!5'%0,!.%
+
,
,
B
0).
)$%.4)&)#!4)/.
1. Drawing is not to scale.
E
"?-%?6
Table 73. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
A
Min Typ Max
1.60
Min Typ Max
0.0630
A1 0.05
0.15
0.0020
0.0059
A2 b c
D
D1
D3
1.35
0.17
0.09
8.80
6.80
1.40
0.22
7.00
5.50
1.45
0.27
0.20
9.00
9.20
7.20
0.0531
0.0067
0.0035
0.3465
0.2677
0.0551
0.0087
0.3543
0.2756
0.2165
0.0571
0.0106
0.0079
0.3622
0.2835
DocID024472 Rev 1 117/124
Package characteristics STM32F31xx
Table 73. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data (continued) inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
E
E1
E3 e
L
L1
K ccc
8.80
6.80
9.00
7.00
5.50
0.50
0.45
0.60
1.00
0° 3.5°
9.20
7.20
0.75
7°
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
0.3465
0.2677
0.0177
0°
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
0.3622
0.2835
0.0295
7°
0.0031
Figure 36. Recommended footprint
AID
1. Dimensions are in millimeters.
Obsolete Product(s) - Obsolete Product(s)
118/124 DocID024472 Rev 1
STM32F31xx Package characteristics
The maximum chip junction temperature (T
J max) must never exceed the values given in
Table 22: General operating conditions on page 55 .
The maximum chip-junction temperature, T
J using the following equation:
max, in degrees Celsius, may be calculated
T
J
max = T
A
max + (P
D
max x Θ
JA
)
Where:
• T
A
max is the maximum ambient temperature in °C,
• Θ
JA
is the package junction-to-ambient thermal resistance, in ° C/W,
• P
D
max is the sum of P
INT
max and P
I/O max (P
D
max = P
INT
max + P
I/O max),
• P
INT
max is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max = Σ (V
OL
× I
OL
) + Σ ((V
DD
– V
OH
) × I
OH
), taking into account the actual V
OL application.
/ I
OL
and V
OH
/ I
OH of the I/Os at low and high level in the
Symbol
Θ
JA
Table 74. Package thermal characteristics
Parameter Value
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
45
55
41
Unit
°C/W
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Obsolete Product(s) - Obsolete Product(s)
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Package characteristics STM32F31xx
7.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering .
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F31x at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
Amax
I
DDmax
= 50 mA, V
DD
= 82 °C (measured according to JESD51-2),
= 3.5 V, maximum 3 I/Os used at the same time in output at low level with I
OL
= 8 mA, V
OL
= 0.4 V and maximum 2 I/Os used at the same time in output at low level with I
OL
= 20 mA, V
OL
= 1.3 V
P
INTmax
= 50 mA × 3.5 V= 175 mW
P
IOmax
= 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW
This gives: P
INTmax
= 175 mW and P
IOmax
= 61.6 mW:
P
Dmax
= 175 + 61.6 = 236.6 mW
Thus: P
Dmax
= 236.6 mW
Using the values obtained in Table 74
T
Jmax
is calculated as follows:
– For LQFP64, 45°C/W
T
Jmax
= 82 °C + (45°C/W × 236.6 mW) = 82 °C + 10.65 °C = 92.65 °C
This is within the range of the suffix 6 version parts (–40 < T
J
< 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T
J specified range.
remains within the
Assuming the following application conditions:
Obsolete Product(s) - Obsolete Product(s)
I
DDmax
= 20 mA, V
DD level with I
OL
= 8 mA, V
OL
= 0.4 V
= 115 °C (measured according to JESD51-2),
= 3.5 V, maximum 9 I/Os used at the same time in output at low
P
INTmax
= 20 mA × 3.5 V= 70 mW
P
IOmax
= 9 × 8 mA × 0.4 V = 28.8 mW
This gives: P
INTmax
= 70 mW and P
IOmax
= 28.8 mW:
P
Dmax
= 70 + 28.8 = 98.8 mW
Thus: P
Dmax
= 98.8 mW
120/124 DocID024472 Rev 1
STM32F31xx Package characteristics
Using the values obtained in Table 74
T
Jmax
is calculated as follows:
– For LQFP100, 41°C/W
T
Jmax
= 115 °C + (41°C/W × 98.8 mW) = 115 °C + 4.05 °C = 119.05 °C
This is within the range of the suffix 7 version parts (–40 < T
J
< 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
).
Obsolete Product(s) - Obsolete Product(s)
DocID024472 Rev 1 121/124
Part numbering STM32F31xx
Table 75. Ordering information scheme
STM32F313 R Example:
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
313 = STM32F313xx
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
B = 128 Kbytes of Flash memory (medium density)
C = 256 Kbytes of Flash memory (high density)
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options xxx = programmed parts
TR = tape and reel
B T 6xxx
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STM32F31xx
Date
08-Apr-2013
Revision
Table 76. Document revision history
1
Revision history
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STM32F31xx
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
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