STMicroelectronics M40SZ100W Datasheet
जाहिरात
जाहिरात
M40SZ100W
16
1
SO16
Features
Convert low power SRAMs into NVRAMs
3 V operating voltage
Precision power monitoring and power switching circuitry
Automatic write-protection when V
CC tolerance
is out-of-
Choice of supply voltage and power-fail deselect voltage:
– V
CC
= 2.7 to 3.6 V; 2.55 V V
PFD
2.70 V
Reset output (RST) for power on reset
1.25 V reference (for PFI/PFO)
Less than 15 ns chip enable access propagation delay
Battery low pin (BL)
RoHS compliant
– Lead-free second level interconnect
3 V NVRAM supervisor for LPSRAM
Datasheet
-
production data
Description
The M40SZ100W NVRAM controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the V
CC condition.
input for an out-of-tolerance
When an invalid V
CC
condition occurs, the conditioned chip enable output (E
CON)
is forced inactive to write protect the stored data in the
SRAM. During a power failure, the SRAM is switched from the V
CC
pin to the external battery to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains write-protected until a valid power condition returns.
December 2013
This is information on a product in full production.
DocID007528 Rev 4 1/20 www.st.com
Contents
Contents
M40SZ100W
Data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/20 DocID007528 Rev 4
M40SZ100W
List of tables
List of tables
DocID007528 Rev 4 3/20
20
List of figures
List of figures
M40SZ100W
Figure 1.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4.
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5.
Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6.
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7.
RSTIN timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8.
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9.
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.
SO16 – 16-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4/20 DocID007528 Rev 4
M40SZ100W Device overview
Figure 1. Logic diagram
VCC VBAT
E
E
CON
RST
RSTIN
BL
V
OUT
V
CC
V
BAT
PFI
PFO
V
SS
NC
E
PFI
RSTIN
M40SZ100W
VOUT
BL
ECON
PFO
RST
VSS
Table 1. Signal names
Chip enable input
Conditioned chip enable output
Reset output (open drain)
Reset input
Battery low output (open drain)
Supply voltage output
Supply voltage
Backup supply voltage
Power fail input
Power fail output
Ground
Not connected internally
AI03933
DocID007528 Rev 4 5/20
20
Device overview
Figure 2. Pin connections
NC
NC
RST
NC
RSTIN
PFO
VBAT
VSS
1
2
3
4
5
6
7
8
16
15
14
M40SZ100W 13
12
11
10
9
VCC
NC
VOUT
NC
PFI
BL
E
ECON
Figure 3. Block diagram
VCC
VBAT
VBL= 2.5V
COMPARE
VSO = 2.5V
COMPARE
VPFD= 2.65
V COMPARE POR
RSTIN
E
PFI
1.25V
1. Open drain output
COMPARE
M40SZ100W
VOUT
AI03935
BL
(1)
RST(1)
ECON
PFO
AI04766
6/20 DocID007528 Rev 4
M40SZ100W
Unregulated
Voltage
R1
R2
Regulator
VIN VCC
Figure 4. Hardware hookup
3.0V, 3.3V
VCC VOUT
0.1
μ F
M40SZ100W
E
From Microprocessor
RSTIN ECON
PFI PFO
VSS
VBAT
RST
BL
Device overview
0.1
μ F
VCC
1Mb or 4Mb
LPSRAM
E
To Microprocessor NMI
To Microprocessor Reset
To Battery Monitor Circuit
AI04767
DocID007528 Rev 4 7/20
20
Operation
2 Operation
M40SZ100W
The M40SZ100W, as shown in
Figure 4 on page 7 , can control one (two, if placed in
parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E
CON
) output pin follows the chip enable (E) input pin with timing shown in
Table 2 on page 10 . An internal switch connects V
drop of less than 0.3 V (I
OUT1
).
CC
to V
OUT
. This switch has a voltage
When V
CC
degrades during a power failure, E
CON
is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as V tolerance threshold (V with V
PFD
PFD
is shown in Table 7 on page 16 .
CC
falls below an out-of-
). For the M40SZ100W the power fail detection value associated
If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time t
WPT
, E
CON
is unconditionally driven high, write protecting the SRAM.
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below V
PFD
(min), the user can be assured the memory will be write protected within the Write Protect Time (t
WPT provided the V
CC
fall time does not exceed t
F
(see
).
)
As V
CC
continues to degrade, the internal switch disconnects V battery to V
OUT
. This occurs at the switchover voltage (V provides a voltage V
).
OHB
CC
and connects the internal
SO
). Below the V
to the SRAM and can supply current I
OUT2
SO
, the battery
(see
When V
CC
rises above V held inactive for t
CER
SO
, V
OUT
is switched back to the supply voltage. Output E
(120 ms maximum) after the power supply has reached V
PFD
CON
,
is
independent of the E input, to allow for processor stabilization (see Figure 6 on page 10 ).
2.1 Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40SZ100W NVRAM controller. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40SZ100W and SRAMs to be “Don't care” once V
CC
falls below V
PFD
(min) (see Figure 5 on page 9 ). The SRAM should
also guarantee data retention down to V
CC
= 2.0 V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included.
If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the I
CCDR the M40SZ100W to determine the total current requirements for data retention.
value of
Caution: Take care to avoid inadvertent discharge through V
OUT attached.
and E
CON
after battery has been
8/20 DocID007528 Rev 4
M40SZ100W Operation
For a further more detailed review of lifetime calculations, please see application note
AN1012.
Figure 5. Power-down timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO tF tFB
E
ECON
RST tWPT
VOHB
PFO
VALID
AI03936
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Operation M40SZ100W
Figure 6. Power-up timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO tR tCER
E
ECON
RST tRB
VOHB tREC tEPD tEPD
PFO
VALID
AI03937
Symbol t
F
(2) t
FB
(3) t
PFD t
R t
EPD t
RB t
CER t
REC t
WPT
V
PFD
V
PFD
V
PFD
(min) to V
SS
V
PFD
(min) to V
PFD
Write protect time
Table 2. Power-down/up AC characteristics
(max) to V
PFD
(min) V
CC
V
CC
V
SS
to V
PFD
(min) V
Chip enable recovery
(max) to RST high
Parameter
(1)
fall time
PFI to PFO propagation delay
fall time
(max) V
CC
rise time
Chip enable propagation delay (low or high)
CC
rise time
Min
300
10
15
10
1
40
40
40
Max
25
15
120
200
200
Unit
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 3.6 V (except where noted).
2. V
PFD
V
CC
(max) to V
PFD
passes V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200 μ s after
(min).
3. V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
μ s
μ s
μ s
μ s ns
μ s ms ms
μ s
10/20 DocID007528 Rev 4
M40SZ100W
2.2
Operation
Power-on reset output
All microprocessors have a reset input which forces them to a known state when starting.
The M40SZ100W has a reset output (RST) pin which is guaranteed to be low by V
PFD
Table 7 on page 16 ). This signal is an open drain configuration. An appropriate pull-up
(see resistor to V
CC
should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when V
CC
equals V
SS
(with valid battery voltage).
Once V
CC for t
REC
exceeds the power failure detect voltage V
to allow the power supply to stabilize.
PFD
, an internal timer keeps RST low
2.3 Reset input (RSTIN)
The M40SZ100W provides one independent input which can generate an output reset. The duration and function of this reset is identical to a reset generated by a power cycle.
Table 3 and Figure 7 illustrate the AC reset characteristics of this function. Pulses shorter than t
RLRH will not generate a reset condition. RSTIN is internally pulled up to V
CC resistor.
through a 100 k
Figure 7. RSTIN timing waveform
2.4
RSTIN tRLRH
RST
(1) tR1HRH
AI04768
1. With pull-up resistor
Symbol t
RLRH
(2) t
R1HRH
(3)
Table 3. Reset AC characteristics
Parameter
(1)
RSTIN low to RSTIN high
RSTIN high to RST high
Min
200
40
Max
200
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 3.6 V (except where noted).
2. Pulse width less than 50 ns will result in no RESET (for noise immunity).
3. C
L
= 50 pF (see
Unit ns ms
Battery low pin
The M40SZ100W automatically performs battery voltage monitoring upon power-up, and at factory-programmed time intervals of at least 24 hours. The Battery Low (BL) pin will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL pin will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval.
DocID007528 Rev 4 11/20
20
Operation M40SZ100W
If a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5 V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V
CC
is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced.
The M40SZ100W only monitors the battery when a nominal V
CC
is applied to the device.
Thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL pin is an open drain output and an appropriate pull-up resistor to V
CC
should be chosen to control the rise time.
The power-fail input (PFI) is compared to an internal reference voltage (independent from the V
PFD
comparator). If PFI is less than the power-fail threshold (V
PFI
), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider
) to either the unregulated DC input (if it is available) or the regulated output of the V
CC
regulator. The voltage divider can be set up such that the voltage at PFI falls below V
PFI
several milliseconds before the regulated V
CC
input to the
M40SZ100W or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator turns off and PFO goes (or remains) low.
This occurs after V
CC
drops below V
PFD
(min). When power returns, PFO is forced high, irrespective of V
PFI for the write protect time (t
REC
), which is the time from V
PFD
(max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and
PFO follows PFI. If the comparator is unused, PFI should be connected to V
SS unconnected.
and PFO left
2.6 V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 μ F (as shown in
Figure 8 on page 13 ) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
SS
). recommended for surface mount.
12/20 DocID007528 Rev 4
M40SZ100W
Figure 8. Supply voltage protection
VCC
VCC
0.1µF DEVICE
VSS
Operation
AI00622
DocID007528 Rev 4 13/20
20
Maximum ratings M40SZ100W
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 4. Absolute maximum ratings
Parameter Value Unit
T
STG
T
SLD
(1)
V
IO
V
CC
I
O
P
D
Storage temperature (V
CC
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
Output current
Power dissipation
off) –55 to 125
260
–0.3 to V
CC
1
+0.3
–0.3 to 4.6
20
1. For SO package, Lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
°C
°C
V
V mA
W
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
14/20 DocID007528 Rev 4
M40SZ100W
4 DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Table 5:
DC and AC measurement conditions . Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 5. DC and AC measurement conditions
Parameter
V
CC
supply voltage
Ambient operating temperature
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
Value
2.7 to 3.6 V
–40 to 85 °C
50 pF
5 ns
0.2 to 0.8V
CC
0.3 to 0.7V
CC
Figure 9. AC testing load circuit
333
DEVICE
UNDER
TEST
CL = 50pF
1.73V
CL includes JIG capacitance
Figure 10. AC testing input/output waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
Symbol
C
IN
C
OUT
(3)
Input capacitance
Output capacitance
1. Sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Table 6. Capacitance
Parameter
(1)(2)
Min
-
-
Max
7
10
AI02393
AI02568
Unit pF pF
DocID007528 Rev 4 15/20
20
DC and AC parameters M40SZ100W
Sym Parameter
Table 7. DC characteristics
Test condition
(1)
Min Typ Max Unit
I
CC
I
CCDR
Supply current
Data retention mode current
(2)
I
LI
(3)
V
PFI
Input leakage current
Input leakage current (PFI)
I
LO
(4)
I
OUT1
(5)
I
OUT2
V
BAT
V
IH
V
IL
V
OH
V
OHB
Output leakage current
V
OUT
current (active)
V
OUT
current (battery backup)
Battery voltage
Input high voltage
Input low voltage
Output high voltage
(6)
V
OH
battery backup
(7)
Output low voltage
V
OL
V
PFD
Output low voltage (open drain)
(8)
Power-fail deselect voltage
PFI input threshold
PFI hysteresis
V
SO
Battery backup switchover voltage
V
V
I
Outputs open
0 V
OUT
OUT
I
OH
> V
> V
= –1.0 mA
OUT2
I
I
OL
OL
V
V
0 V V
CC
IN
V
OUT
V
CC
BAT
– 0.3
– 0.3
= –1.0
CC
μ
= 3.0 mA
= 10 mA
= 3 V
PFI rising
CC
A
–25
2.5
0.7V
CC
–0.3
2.4
2.5
2.55
50
2
3.0
2.9
2.60
20
2.5
0.4
2.70
1.225
1.250
1.275
70
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 3.6 V (except where noted).
2. Measured with V
OUT
and E
CON
open.
3. RSTIN internally pulled-up to V
CC
through 100 k resistor.
4. Outputs deselected.
5. External SRAM must match SUPERVISOR chip V
CC
specification.
6. For PFO pin (CMOS).
7. Chip enable output (E
CON
) can only sustain CMOS leakage currents in the battery backup mode. Higher leakage currents will reduce battery life.
8. For RST & BL pins (open drain).
V
V
V mV
V
±1
100
100
3.5
(6)
0.5
200
±1
25
V
CC
+ 0.3
V
0.3V
CC
V
V
3.5
V
0.4
V
μ A mA
μ A
V mA nA
μ A nA
16/20 DocID007528 Rev 4
M40SZ100W
5 Package mechanical data
Note:
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
Figure 11. SO16 – 16-lead plastic small package outline
A2 A
C
B e
CP
D
N
E H
1
A1
α
L
Drawing is not to scale.
Table 8. SO16 – 16-lead plastic small outline package mechanical data mm
Symbol inches
Typ.
Min.
Max.
Typ.
Min.
Max.
L a
N
CP e
H
D
E
A
A1
A2
B
C
1.27
0.10
0.35
0.19
9.80
3.80
–
5.80
0.40
0°
16
10.00
4.00
–
6.20
1.27
8°
1.75
0.25
1.60
0.46
0.25
0.10
0.050
0.004
0.014
0.007
0.386
0.150
–
0.228
0.016
0°
16
0.069
0.010
0.063
0.018
0.010
0.394
0.158
–
0.244
0.050
8°
0.004
SO-b
DocID007528 Rev 4 17/20
20
Part numbering M40SZ100W
Table 9. Ordering information scheme
Example:
Device type
M40SZ
Supply voltage and write protect voltage
100W = V
CC
= 2.7 to 3.6 V; V
PFD
= 2.6 to 2.7 V
Package
MQ = SO16
M40SZ 100W MQ
Temperature range
6 = –40 to 85 °C
Shipping method
F = Lead-free ECOPACK
® package, tape & reel
6 F
For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the ST sales office nearest to you.
18/20 DocID007528 Rev 4
M40SZ100W Revision history
Date
Dec-2001
13-May-2002
01-Aug-2002
Revision
1.0
1.1
1.2
15-Sep-2003
20-Nov-2007
25-Oct-2010
16-Dec-2013
1.3
2
3
4
Table 10. Document revision history
Changes
First issue
Modify reflow time and temperature footnote (
)
Add marketing status (cover page;
Remove reference to M68xxx (obsolete) part (
); update disclaimer
Reformatted document; added lead-free second level interconnect information to cover page and
Section 5: Package mechanical data
; updated
Updated cover page,
® text in
Section 5 ; reformatted document; minor textual changes.
Removed SNAPHAT and SOH28 package option as well as 5 V part
(M40SZ100Y) from datasheet
Removed shipping option in tubes from Table 9
DocID007528 Rev 4 19/20
20
M40SZ100W
Please Read Carefully:
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All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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20/20 DocID007528 Rev 4
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