STMicroelectronics RF5L1214750CB4 Datasheet
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RF5L1214750CB4
Datasheet
750 W, 50 V, 1200 to 1400 MHz RF power LDMOS transistor
1
3
4
5
Pin
1
2
2
5
4
3
D4E
Pin connection
Connection
Drain A
Drain B
Source (bottom side)
Gate B
Gate A
Features
Order code
RF5L1214750CB4
Frequency
1300 MHz
V
DD
P
OUT
Gain
50 V 750 W 15 dB
Efficiency
53%
• High efficiency and linear gain operations
• Integrated ESD protection
• Internally matched pair transistors in push-pull configuration
• Large positive and negative gate-source voltage range for improved class C operation
• Excellent thermal stability, low HCI drift
• In compliance with the European directive 2002/95/EC
Applications
• L-Band radar
• From 1300 to 1500 MHz particle accelerator
Description
The RF5L1214750CB4 is a 750 W, 50V high performance LDMOS FET, designed for
L-Band radar and particle accelerator in the frequency range from 1300 to 1500 MHz.
Product status link
RF5L1214750CB4
Product summary
Order code RF5L1214750CB4
Marking
Package
5L1214750
D4E
Packing
Base/bulk quantity
Tray
20/100
DS13650 - Rev 2 - September 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
RF5L1214750CB4
Electrical ratings
Electrical ratings
Symbol
V
DS
V
GS
V
DD
T
STG
T
J
Table 1. Absolute maximum ratings (T
C
= 25 °C)
Parameter
Drain-source voltage
Gate-source voltage
Maximum operating voltage
Storage temperature range
Maximum junction temperature
Table 2. Thermal data
Symbol
R thJC
Parameter
Thermal resistance, junction-to-case
1. T
C
= 80 °C , P
OUT
= 1kW, pulse width = 100 µs, duty cycle = 10%.
Symbol
HBM
CDM
Table 3. ESD protection
Test methodology
Human body model (according to ANSI/ESDA/JEDEC JS001-2017)
Charge device mode (according to ANSI/ESDA/JEDEC JS002-2014)
Value
110
-8 to 10
55
-65 to 150
200
V
°C
°C
Unit
V
V
Value
0.02
Class
2
C3
Unit
°C/W
DS13650 - Rev 2 page 2/12
RF5L1214750CB4
Electrical characteristics
2
Note:
Electrical characteristics
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
V
GS(Q)
V
DS(on)
I
DS(on)
R
DS(on)
Table 4. Static (per side)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
DS
= 100 µA
Zero gate voltage drain leakage current
V
GS
= 0 V, V
DS
= 50 V
V
GS
= 0 V, V
DS
= 90 V
Gate-source leakage current
Gate threshold voltage
Gate quiescent voltage
Static drain-source on-voltage
V
GS
= -8/10 V, V
DS
= 0 V
I
D
= 600 µA
V
DS
= 1 V, I
DS
= 100 mA
V
GS
= 10 V, I
DS
= 10 A
Static drain-source on-current V
GS
= 10 V, V
DS
= 100 mV
Drain-source on-state resistance V
GS
= 10 V, V
DS
= 100 mV
Symbol
P
OUT
G
PS
η
D
VSWR
Parameter
Output power
Power gain
Drain efficiency
Load mismatch
Table 5. Dynamic f = 1300 MHz
Test conditions
P
OUT
= 750 W, all phases
V
DD
= 50 V, I
DQ
= 150 mA, pulse CW = 100 μs, duty cycle = 10%.
Min.
Typ.
Max.
Unit
110 V
-
-
10 μA
-
1
2
-
-
-
±100
3
5 nA
V
V
-
-
-
1.2
2.5
1
V
A
Ω
Min.
Typ.
Max.
Unit
-
-
750
15
53
W dB
%
10:1
DS13650 - Rev 2 page 3/12
3
Note:
RF5L1214750CB4
Typical performances
Typical performances
Figure 1. Power gain and drain efficiency vs output power (over 1200 - 1400 MHz frequency band)
15.0
14.5
14.0
16.0
15.5
13.5
13.0
12.5
12.0
52 53 54 55
1200MHz GPS
1200MHz ηD
56
P
OUT
(dbm)
57
1300MHz GPS
1300MHz ηD
58
1400MHz GPS
1400MHz ηD
59
V
DD
= 50 V, I
DQ
= 150 mA, pulsed CW, pulse width = 100 μs.
Figure 2. Small signal gain and return loss (S21 and S11)
60
50
45
40
60
55
25
61
20
35
30
Note: V
DD
= 50 V, I
DQ
= 400 mA, pin = 0 dBm.
DS13650 - Rev 2 page 4/12
4
Test circuits
Figure 3. Test circuit layout
RF5L1214750CB4
Test circuits
DS13650 - Rev 2
C1, C2
Component
C3, C4, C5
C6, C7, C8
C9, C10
R1
R2
PCB
Table 6. Components list
Value
47 pF
47 pF
10 µF
1000 µF
Size
0805
0805
1210
Reference
ATC600F
ATC800B
50 V ceramic multilayer capacitor
63 V aluminum electrolytic capacitor
15 Ω
5.1 Ω
0805
0805
0.508 mm (0.020'') thick, ɛr = 3.48, Rogers RO4350B, 1 oz. copper page 5/12
Figure 4. Test circuit photo
RF5L1214750CB4
Test circuits
DS13650 - Rev 2 page 6/12
5
5.1
RF5L1214750CB4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
D4E package information
Figure 5. D4E package outline
DS13650 - Rev 2
DM00666713_2 page 7/12
DS13650 - Rev 2
Symbol
P
Q
R
S
T
V
R1
CH1
G
H
L
M
N
A
B
C
E
F
Min.
10.04
5.72
16.11
1.51
0.10
35.44
11.56
1.92
3.06
9.25
4.17
30.96
1.55
2.09
41.08
13.60
Table 7. D4E package mechanical data
Millimeters
Typ.
4.55
31.24
1.62
2.16
41.22
13.72
1.59
1.19
10.16
5.85
16.62
1.78
0.13
35.56
11.68
2.04
3.18
9.40
RF5L1214750CB4
D4E package information
Max.
10.28
3.48
17.13
2.05
0.16
35.68
11.80
2.16
3.30
9.50
4.93
31.52
1.69
2.23
13.84
page 8/12
5.2
RF5L1214750CB4
Marking information
Marking information
PACKAGE FACE : TOP
C
E
D
A B
F G H
Figure 6. Marking composition
LEGEND
Unmarkable Surface
Marking Composition Field
A - STANDARD ST LOGO
B - ECO level
(e4)
C
D
- MARKING AREA
- ADDITIONAL
INFORMATION
(MAX CHAR ALLOWED = 7)
E - COUNTRY OF ORIGIN
(MAX CHAR ALLOWED = 3)
F - Assy Plant
(PP)
G - Assy Year
(Y)
H - Assy Week
(WW)
GADG040220211644GT
DS13650 - Rev 2 page 9/12
Revision history
Date
16-Feb-2021
22-Sep-2021
Revision
1
2
Table 8. Document revision history
Changes
First release.
Updated Table 3. ESD protection
.
Updated Table 4. Static (per side) .
Minor text changes.
RF5L1214750CB4
DS13650 - Rev 2 page 10/12
RF5L1214750CB4
Contents
Contents
DS13650 - Rev 2 page 11/12
RF5L1214750CB4
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DS13650 - Rev 2 page 12/12
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