STMicroelectronics TS4990 Datasheet
إعلان
إعلان
TS4990
TS4990EIJT - Flip-chip 9 bumps
TS4990IST - MiniSO-8
STANDBY 1
BYPASS 2
VIN+
3
VIN– 4
1.2 W audio power amplifier with active-low standby mode
TS4990IQT - DFN8
8
7
VOUT2
GND
6
5
VCC
VOUT1
Datasheet
-
production data
Features
Operating range from V
CC
1.2 W output power at V
CC
F = 1 kHz, with 8
load
= 2.2 V to 5.5 V
= 5 V, THD = 1%,
Ultra-low consumption in standby mode
(10 nA)
62 dB PSRR at 217 Hz in grounded mode
Near-zero pop and click
Ultra-low distortion (0.1%)
Unity gain stable
Available in 9-bump flip-chip, miniSO-8 and
DFN8 packages
Applications
Mobile phones (cellular / cordless)
Laptop / notebook computers
PDAs
Portable audio devices
Description
The TS4990 is designed for demanding audio applications such as mobile phones to reduce the number of external components.
This audio power amplifier is capable of delivering
1.2 W of continuous RMS output power into an
8
load at 5 V.
An externally controlled standby mode reduces the supply current to less than 10 nA. It also includes an internal thermal shutdown protection.
The unity-gain stable amplifier can be configured by external gain setting resistors.
TS4990IDT - SO-8
January 2019
This is information on a product in full production.
DocID9309 Rev 14 1/33 www.st.com
Contents
Contents
TS4990
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low and high frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power dissipation and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application example: differential input, BTL power amplifier . . . . . . . . . . 23
Flip-chip package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/33 DocID9309 Rev 14
TS4990
1
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Symbol
V
CC
V in
T oper
T stg
T j
Table 1. Absolute maximum ratings (AMR)
Parameter
Supply voltage
(1)
Input voltage
(2)
Operating free-air temperature range
Value
6
GND to V
CC
-40 to + 85
Storage temperature
Maximum junction temperature
-65 to +150
150
R thja
Thermal resistance junction to ambient
Flip-chip
(3)
MiniSO-8
DFN8
250
215
120
Unit
°C/W
P diss
ESD
Power dissipation
HBM: Human body model
(4)
MM: Machine model
(5)
Latch-up immunity
Internally limited
2
200
200 kV
V mA
Lead temperature (soldering, 10 sec)
Lead temperature (soldering, 10 sec) for lead-free version
250
260
°C
1.
All voltage values are measured with respect to the ground pin.
2.
The magnitude of the input signal must never exceed V
CC
+ 0.3 V / GND - 0.3 V.
3.
The device is protected in case of over temperature by a thermal shutdown active at 150° C.
4.
Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 k
resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.
5.
Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5
). This is done for all couples of connected pin combinations while the other pins are floating.
V
V
°C
°C
°C
Symbol
Table 2. Operating conditions
Parameter
V
CC
V icm
Supply voltage
Common mode input voltage range
V
STBY
Standby voltage input:
Device ON
Device OFF
R
L
T
SD
Load resistor
Thermal shutdown temperature
R thja
Thermal resistance junction to ambient
Flip-chip
(1)
MiniSO-8
DFN8
(2)
1.
This thermal resistance is reached with a 100 mm
2
copper heatsink surface.
2.
When mounted on a 4-layer PCB.
Value
2.2 to 5.5
1.2V to V
CC
1.35
V
STBY
GND
V
STBY
V
CC
0.4
4
150
100
190
40
DocID9309 Rev 14
Unit
V
V
V
°C
°C/W
3/33
33
Typical application schematics
2 Typical application schematics
Figure 1. Typical application schematics
Rfeed
Cfeed Vcc
Audio In
Cin
Rin
Vin-
-
Vin+
+
Cs
TS4990
Vout 1
Speaker
8 Ohms
-
AV = -1
+
Vout 2
Standby
Control
Cb
Bypass
Standby
Bias
TS4990
Component
R in
C in
R feed
C s
C b
C feed
A
V
Exposed pad
Table 3. Component descriptions
Functional description
Inverting input resistor that sets the closed loop gain in conjunction with R feed
. This resistor also forms a high pass filter with C in
(F c
= 1 / (2 x Pi x R in
x C in
)).
Input coupling capacitor that blocks the DC voltage at the amplifier input terminal.
Feed back resistor that sets the closed loop gain in conjunction with R in
.
Supply bypass capacitor that provides power supply filtering.
Bypass pin capacitor that provides half supply filtering.
Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency 1/ (2 x Pi x R feed
x C feed
)).
Closed loop gain in BTL configuration = 2 x (R feed
/ R in
).
4/33 DocID9309 Rev 14
TS4990 Electrical characteristics
Table 4. Electrical characteristics when V
CC
= +5 V, GND = 0 V, T amb otherwise specified)
= 25°C (unless
Symbol Parameter Min.
Typ.
Max.
Unit
I
I
STBY
V
P
CC oo out
THD + N
PSRR
Supply current
No input signal, no load
Standby current
(1)
No input signal, V
STBY
= GND, R
L
= 8
Output offset voltage
No input signal, R
L
= 8
Output power
THD = 1% max, F = 1 kHz, R
L
= 8
Total harmonic distortion + noise
P out
= 1W rms
, A
V
= 2, 20 Hz
F
20 kHz, R
L
= 8
Power supply rejection ratio
(2)
R
L
= 8
A
V
= 2
V ripple
= 200mV pp
, input grounded
F = 217 Hz
F = 1 kHz
0.9
3.7
10
1
1.2
0.2
6
1000
10 mA nA mV
W
% dB
55
55
62
64 t
WU t
STBY
V
STBYH
V
STBYL
Wake-up time (C
Standby time (C b b
= 1 µF)
= 1 µF)
Standby voltage level high
Standby voltage level low
90
10
130
1.3
0.4
ms
µs
V
V
M
Phase margin at unity gain
R
L
= 8
, C
L
= 500 pF
GM
Gain margin
R
L
= 8
, C
L
= 500 pF
GBP
R
OUT-GND
Gain bandwidth product
R
L
= 8
Resistor output to GND (V
STBY
V
STBYL
)
V out1
V out2
65
15
1.5
3
43
Degrees dB
MHz k
1.
Standby mode is active when V
STBY
is tied to GND.
2.
All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(V
V
CC
.
out
)/rms(V ripple
)). V ripple
is the sinusoidal signal superimposed upon
DocID9309 Rev 14 5/33
33
Electrical characteristics TS4990
Table 5. Electrical characteristics when V
CC
= +3.3 V, GND = 0 V, T amb otherwise specified)
= 25°C (unless
Symbol Parameter Min.
Typ.
Max.
Unit
I
I
STBY
V
P
CC oo out
THD + N
PSRR
Supply current
No input signal, no load
Standby current
(1)
No input signal, V
STBY
= GND, R
L
= 8
Output offset voltage
No input signal, R
L
= 8
Output power
THD = 1% max, F = 1 kHz, R
L
= 8
Total harmonic distortion + noise
P out
R
L
= 400 mW
= 8
rms
, A
V
= 2, 20 Hz
F
20 kHz,
Power supply rejection ratio
(2)
R
L
= 8
A
V
= 2
V ripple
= 200mV pp
, input grounded
F = 217 Hz
F = 1 kHz
375
3.3
10
1
500
0.1
6
1000
10 mA nA mV mW
% dB
55
55
61
63 t
WU t
STBY
V
STBYH
V
STBYL
Wake-up time (C
Standby time (C b b
= 1 µF)
= 1 µF)
Standby voltage level high
Standby voltage level low
M
GM
GBP
R
OUT-GND
Phase margin at unity gain
R
L
= 8
, C
L
= 500 pF
Gain margin
R
L
= 8
, C
L
= 500 pF
Gain bandwidth product
R
L
= 8
Resistor output to GND (V
STBY
V
STBYL
)
V out1
V out2
110
10
65
15
1.5
4
44
140
1.2
0.4
ms
µs
Degrees dB
MHz k
V
V
1.
Standby mode is active when V
STBY
is tied to GND.
2.
All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(V
V
CC
.
out
)/rms(V ripple
)). V ripple
is the sinusoidal signal superimposed upon
6/33 DocID9309 Rev 14
TS4990 Electrical characteristics
Table 6. Electrical characteristics when V
CC
= 2.6V, GND = 0V, T amb
= 25°C (unless otherwise specified)
Symbol Parameter Min.
Typ.
Max.
Unit
I
I
STBY
V
P
CC oo out
THD + N
PSRR
Supply current
No input signal, no load
Standby current
(1)
No input signal, V
STBY
= GND, R
L
= 8
Output offset voltage
No input signal, R
L
= 8
Output power
THD = 1% max, F = 1 kHz, R
L
= 8
Total harmonic distortion + noise
P out
R
L
= 200 mW
= 8
rms
, A
V
= 2, 20 Hz
F
20 kHz,
Power supply rejection ratio
(2)
R
L
= 8
A
V
= 2
V ripple
= 200 mV pp
, input grounded
F = 217 Hz
F = 1 kHz
220
3.1
10
1
300
0.1
6
1000
10 mA nA mV mW
% dB
55
55
60
62 t
WU t
STBY
V
STBYH
V
STBYL
Wake-up time (C
Standby time (C b b
= 1 µF)
= 1 µF)
Standby voltage level high
Standby voltage level low
M
GM
GBP
R
OUT-GND
Phase margin at unity gain
R
L
= 8
, C
L
= 500 pF
Gain margin
R
L
= 8
, C
L
= 500 pF
Gain bandwidth product
R
L
= 8
Resistor output to GND (V
STBY
V
STBYL
)
V out1
V out2
125
10
65
15
1.5
6
46
150
1.2
0.4
ms
µs
Degrees dB
MHz k
V
V
1.
Standby mode is active when V
STBY
is tied to GND.
2.
All PSRR data limits are guaranteed by production sampling tests.
Dynamic measurements - 20*log(rms(V
V
CC
.
out
)/rms(V ripple
)). V ripple
is the sinusoidal signal superimposed upon
DocID9309 Rev 14 7/33
33
Electrical characteristics
Figure 2. Open loop frequency response
V
CC
= 5 V
60
40
20
0
Phase
Gain
-20
-40
-60
0.1
Vcc = 5V
RL = 8 Ω
Tamb = 25
°
C
1 10 100
Frequency (kHz)
0
-40
-80
-120
-160
1000
-200
10000
Figure 4. Open loop frequency response
V
CC
= 2.6 V
60
Gain
40
20
Phase
0
-20
-40
-60
0.1
Vcc = 2.6V
RL = 8
Ω
Tamb = 25 ° C
1 10 100
Frequency (kHz)
0
-40
-80
-120
-160
1000
-200
10000
Figure 6. Open loop frequency response
V
CC
= 3.3 V, C
L
560 PF
100
80
Gain
60
40
Phase
20
0
Vcc = 3.3V
-20
-40
0.1
CL = 560pF
Tamb = 25
°
C
1 10 100
Frequency (kHz)
0
-40
-80
-120
-160
1000
-200
10000
TS4990
Figure 3. Open loop frequency response
V
CC
= 3.3 V
60
40
Gain
20
0
Phase
-20
-40
-60
0.1
Vcc = 3.3V
RL = 8 Ω
Tamb = 25
°
C
1 10 100
Frequency (kHz)
0
-40
-80
-120
-160
1000
-200
10000
Figure 5. Open loop frequency response
C
L
= 560 pF
100
80
60
Gain
40
20
Phase
0
Vcc = 5V
-20
-40
0.1
CL = 560pF
Tamb = 25 ° C
1 10 100
Frequency (kHz)
0
-40
-80
-120
-160
1000
-200
10000
Figure 7. Open loop frequency response
V
CC
= 2.6 V, C
L
560 PF
100
80
Gain
60
40
Phase
20
0
Vcc = 2.6V
-20
-40
0.1
CL = 560pF
Tamb = 25
°
C
1 10 100
Frequency (kHz)
0
-40
-80
-120
-160
1000
-200
10000
8/33 DocID9309 Rev 14
TS4990
Figure 8. PSRR vs. power supply Av = 2
0
-10
-20
-30
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = Cin = 1 μ F
RL >= 4 Ω
Tamb = 25 ° C
-40
-50
-60
-70
100
Vcc :
2.2V
2.6V
3.3V
5V
1000 10000
Frequency (Hz)
100000
Electrical characteristics
Figure 9. PSRR vs. power supply Av = 10
0
-10
-20
Vripple = 200mVpp
Av = 10
Input = Grounded
Cb = Cin = 1 μ F
RL >= 4 Ω
Tamb = 25 ° C
-30
Vcc :
2.2V
2.6V
3.3V
5V
-40
-50
100 1000 10000
Frequency (Hz)
100000
Figure 10. PSRR vs. power supply
-50
-60
-70
-80
0
-10
-20
-30
Vripple = 200mVpp
Rfeed = 22k Ω
Input = Floating
Cb = 1 μ F
RL >= 4 Ω
Tamb = 25 ° C
-40
100
Vcc = 2.2, 2.6, 3.3, 5V
1000 10000
Frequency (Hz)
100000
Figure 11. PSRR vs. power supply Av = 5
0
-10
-20
Vripple = 200mVpp
Av = 5
Input = Grounded
Cb = Cin = 1 μ F
RL >= 4 Ω
Tamb = 25 ° C
-30
Vcc :
2.2V
2.6V
3.3V
5V
-40
-50
-60
100 1000 10000
Frequency (Hz)
100000
Figure 12. PSRR vs. power supply Cb = 0.1 µF,
Cin = 1 µF
0
-10
-20
-30
-40
-50
-60
100
Vripple = 200mVpp
Av = 2
Input = Grounded
Cb = 0.1
μ F, Cin = 1 μ F
RL >= 4 Ω
Tamb = 25 ° C
Vcc = 5, 3.3, 2.5 & 2.2V
1000 10000
Frequency (Hz)
100000
Figure 13. PSRR vs. power supply
Rfeed = 22 k
0
-10
-20
-30
Vripple = 200mVpp
Rfeed = 22k Ω
Input = Floating
Cb = 0.1
μ F
RL >= 4 Ω
Tamb = 25 ° C
-40
-50
-60
-70
-80
100
Vcc = 2.2, 2.6, 3.3, 5V
1000 10000
Frequency (Hz)
100000
DocID9309 Rev 14 9/33
33
Electrical characteristics TS4990
Figure 14. PSRR vs. DC output voltage Av = 2 Figure 15. PSRR vs. DC output voltage Av = 10
0
-10
-20
-30
Vcc = 5V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 2
Tamb = 25 ° C
-40
-50
-60
-70
-5 -4 -3 -2 -1 0 1 2 3
Differential DC Output Voltage (V)
4 5
0
-10
-20
Vcc = 5V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 10
Tamb = 25 ° C
-30
-40
-50
-5 -4 -3 -2 -1 0 1 2 3
Differential DC Output Voltage (V)
4 5
Figure 16. PSRR vs. DC output voltage Av = 5
0
-10
-20
-30
Vcc = 3.3V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 5
Tamb = 25 ° C
-40
-50
-60
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Differential DC Output Voltage (V)
Figure 17. PSRR vs. DC output voltage
0
-10
-20
-30
-40
Vcc = 5V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 5
Tamb = 25 ° C
-50
-60
-5 -4 -3 -2 -1 0 1 2 3
Differential DC Output Voltage (V)
4 5
Figure 18. PSRR vs. DC output voltage
Cb = 1 µF
0
-10
-20
-30
-40
Vcc = 3.3V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 2
Tamb = 25 ° C
-50
-60
-70
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Differential DC Output Voltage (V)
Figure 19. PSRR vs. DC output voltage
Vcc = 3.3 V
0
-10
-20
Vcc = 3.3V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 10
Tamb = 25 ° C
-30
-40
-50
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Differential DC Output Voltage (V)
10/33 DocID9309 Rev 14
TS4990
Figure 20. PSRR vs. DC output voltage
Vcc = 2.6 V
0
-10
-20
-30
-40
-50
Vcc = 2.6V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 2
Tamb = 25 ° C
-60
-70
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
2.5
Differential DC Output Voltage (V)
Electrical characteristics
Figure 21. PSRR vs. DC output voltage
Tamb = 25 °C
0
-10
-20
Vcc = 2.6V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 10
Tamb = 25 ° C
-30
-40
-50
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
2.5
Differential DC Output Voltage (V)
Figure 22. Output power vs. power supply voltage
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
RL = 4 Ω
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
2.5
3.0
THD+N=10%
3.5
4.0
Vcc (V)
THD+N=1%
4.5
5.0
5.5
Figure 23. PSRR vs. DC output voltage
0
-10
-20
-30
Vcc = 2.6V
Vripple = 200mVpp
RL = 8 Ω
Cb = 1 μ F
AV = 5
Tamb = 25 ° C
-40
-50
-60
-2.5 -2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
2.5
Differential DC Output Voltage (V)
Figure 24. PSRR at F = 217 Hz vs. bypass capacitor
-30
-40
-50
-60
-70
Av=2
Vcc:
2.6V
3.3V
5V
-80
0.1
Av=10
Vcc:
2.6V
3.3V
5V
Av=5
Vcc:
2.6V
3.3V
5V
1
Bypass Capacitor Cb ( F)
Tamb=25 ° C
Figure 25. Output power vs. power supply voltage R
L
= 8
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
RL = 8 Ω
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
1.2
1.0
2.5
3.0
THD+N=10%
3.5
4.0
Vcc (V)
THD+N=1%
4.5
5.0
5.5
DocID9309 Rev 14 11/33
33
Electrical characteristics
Figure 26. Output power vs. power supply voltage R
L
= 16
1.2
1.0
RL = 16 Ω
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
0.8
0.6
0.4
0.2
0.0
2.5
3.0
THD+N=10%
3.5
4.0
Vcc (V)
THD+N=1%
4.5
5.0
5.5
TS4990
Figure 27. Output power vs. load resistor
Vcc = 5 V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
4
2.2
2.0
1.8
1.6
1.4
THD+N=1%
THD+N=10%
Vcc = 5V
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
8 12 16 20
Load Resistance ( )
24 28 32
Figure 28. Output power vs. load resistor
Vcc = 2.6 V
0.6
0.5
0.4
0.3
0.2
0.1
0.0
4
THD+N=1%
THD+N=10%
Vcc = 2.6V
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
8 12 16 20
Load Resistance ( )
24 28 32
Figure 29. Output power vs. power supply voltage
0.6
0.5
RL = 32 Ω
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
0.4
THD+N=10%
0.3
0.2
0.1
0.0
2.5
3.0
3.5
4.0
Vcc (V)
THD+N=1%
4.5
5.0
5.5
Figure 30. Output power vs. load resistor
Vcc = 3.3 V
0.6
0.4
0.2
1.0
0.8
0.0
THD+N=10%
8
THD+N=1%
16
Load Resistance ( )
24
Vcc = 3.3V
F = 1kHz
BW < 125kHz
Tamb = 25 ° C
32
12/33
Figure 31. Power dissipation vs. P out
,
Vcc = 5 V
0.8
0.6
0.4
0.2
1.4
1.2
Vcc=5V
F=1kHz
THD+N<1%
1.0
0.0
0.0
0.2
0.4
RL=4
RL=8 Ω
Ω
RL=16 Ω
0.6
0.8
1.0
Output Power (W)
1.2
1.4
1.6
DocID9309 Rev 14
TS4990
Figure 32. Power dissipation vs. P out
Vcc = 3.3 V
0.6
0.5
Vcc=3.3V
F=1kHz
THD+N<1%
0.4
0.3
0.2
0.1
0.0
0.0
0.1
RL=16 Ω
0.2
0.3
0.4
0.5
Output Power (W)
RL=4
RL=8 Ω
0.6
Ω
0.7
Electrical characteristics
Figure 33. Power derating curves
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
Heat sink surface
(See demoboard)
≈ 100mm
2
No Heat sink
25 50 75 100
Ambiant Temperature ( C)
125 150
Figure 34. Clipping voltage vs. power supply voltage and load resistor
0.4
0.3
0.2
0.1
0.7
Tamb = 25 ° C
0.6
0.5
0.0
2.5
RL = 4
RL = 8
Ω
Ω
3.0
3.5
4.0
RL = 16 Ω
4.5
Power supply Voltage (V)
5.0
Figure 35. Power dissipation vs. P out
,
Vcc = 2.6 V
0.20
0.15
0.10
0.05
0.40
0.35
Vcc=2.6V
F=1kHz
THD+N<1%
0.30
0.25
RL=16 Ω
0.00
0.0
0.1
RL=8 Ω
0.2
Output Power (W)
0.3
RL=4 Ω
0.4
Figure 36. Clipping voltage vs. power supply voltage and load resistor Tamb = 25 °C
0.3
0.2
0.1
0.0
0.6
Tamb = 25 ° C
0.5
0.4
2.5
RL = 4 Ω
RL = 8 Ω
3.0
3.5
4.0
RL = 16 Ω
4.5
Power supply Voltage (V)
5.0
Figure 37. Current consumption vs. power supply voltage
4.0
3.5
No load
Tamb=25 ° C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0 1 2 3
Power Supply Voltage (V)
4 5
DocID9309 Rev 14 13/33
33
Electrical characteristics TS4990
Figure 38. Current consumption vs. standby voltage @ V
CC
= 5 V
2.0
1.5
1.0
0.5
0.0
0
4.0
3.5
3.0
2.5
1 2 3
Standby Voltage (V)
Vcc = 5V
No load
Tamb=25 ° C
4 5
Figure 39. Current consumption vs. standby voltage @ V
CC
= 2.6 V
4.0
3.5
Vcc = 2.6V
No load
Tamb=25 ° C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
Standby Voltage (V)
2.0
2.5
Figure 40. THD + N vs. output power
R
L
= 4
10
1
RL = 4 Ω
F = 20Hz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
1E-3
Vcc=3.3V
Vcc=5V
0.01
0.1
Output Power (W)
1
Figure 41. Current consumption vs. standby voltage @ V
CC
= 3.3 V
4.0
3.5
Vcc = 3.3V
No load
Tamb=25 ° C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
Standby Voltage (V)
2.5
3.0
Figure 42. Current consumption vs. standby voltage @ V
CC
= 2.2 V
4.0
3.5
Vcc = 2.2V
No load
Tamb=25 ° C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
Standby Voltage (V)
2.0
14/33 DocID9309 Rev 14
Figure 43. THD + N vs. output power
R
L
= 8
10
1
RL = 8 Ω
F = 20Hz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
0.01
1E-3
Vcc=3.3V
0.01
0.1
Output Power (W)
Vcc=5V
1
TS4990 Electrical characteristics
Figure 44. THD + N vs. output power R
L
= 16
10
1
RL = 16 Ω
F = 20kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
Figure 45. THD + N vs. output power Av = 2
10
1
RL = 8 Ω
F = 1kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
0.01
1E-3
Vcc=3.3V
Vcc=5V
0.01
Output Power (W)
0.1
1
0.01
1E-3
Vcc=3.3V
0.01
0.1
Output Power (W)
Vcc=5V
1
Figure 46. THD + N vs. output power F = 20 kHz Figure 47. THD + N vs. output power F = 1 kHz
10
1
RL = 4 Ω
F = 20kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
10
1
RL = 4 Ω
F = 1kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
1E-3
Vcc=3.3V
0.01
0.1
Output Power (W)
Vcc=5V
1
0.1
1E-3
Vcc=3.3V
Vcc=5V
0.01
0.1
Output Power (W)
1
Figure 48. THD + N vs. output power Cb = 1 µF
10
1
RL = 16 Ω
F = 1kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
0.1
Vcc=2.2V
Vcc=2.6V
Vcc=3.3V
0.01
1E-3 0.01
Output Power (W)
0.1
Vcc=5V
1
Figure 49. THD + N vs. output power
10
1
RL = 8 Ω
F = 20kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
1E-3
Vcc=3.3V
Vcc=5V
0.01
0.1
Output Power (W)
1
DocID9309 Rev 14 15/33
33
Electrical characteristics
Figure 50. THD + N vs. output power
10
1
RL = 16 Ω
F = 20kHz
Av = 2
Cb = 1 μ F
BW < 125kHz
Tamb = 25 ° C
Vcc=2.2V
Vcc=2.6V
0.1
0.01
1E-3
Vcc=3.3V
Vcc=5V
0.01
Output Power (W)
0.1
1
Figure 51. THD + N vs. frequency
0.1
RL=8 Ω
Av=2
Cb = 1 μ F
Bw < 125kHz
Tamb = 25 ° C Vcc=5V, Po=1W
TS4990
0.01
20
Vcc=2.2V, Po=130mW
100 1000
Frequency (Hz)
10000 20k
16/33
Figure 52. SNR vs. power supply with unweighted filter (20 Hz to 20 kHz)
110
105
RL=16 Ω
100
95 RL=8
RL=4 Ω
90
85
Av = 2
Cb = 1 μ F
THD+N < 0.7%
Tamb = 25 ° C
80
2.5
3.0
3.5
4.0
Power Supply Voltage (V)
Ω
4.5
5.0
Figure 54. THD + N vs. frequency
Po = 1.3 W
0.1
RL=16 Ω
Av=2
Cb = 1 μ F
Bw < 125kHz
Tamb = 25 ° C
Vcc=5V, Po=0.55W
Vcc=2.2V, Po=100mW
0.01
20 100 1000
Frequency (Hz)
10000 20k
Figure 53. THD + N vs. frequency
Po = 1.3 W
1
RL=4 Ω
Av=2
Cb = 1 μ F
Bw < 125kHz
Tamb = 25 ° C
Vcc=5V, Po=1.3W
Vcc=2.2V, Po=150mW
0.1
20 100 1000
Frequency (Hz)
10000 20k
Figure 55. SNR vs. power supply with unweighted filter (20 Hz to 20 kHz)
95
RL=16 Ω
90
85
RL=8 Ω
80
RL=4 Ω
75
70
Av = 10
Cb = 1 μ F
THD+N < 0.7%
Tamb = 25 ° C
2.5
3.0
3.5
4.0
Power Supply Voltage (V)
4.5
5.0
DocID9309 Rev 14
TS4990 Electrical characteristics
Figure 56. Signal to noise ratio vs. power supply with a weighted filter Av = 2
110
RL=16 Ω
105
100
RL=8 Ω
95
RL=4 Ω
90
85
Av = 2
Cb = 1 μ F
THD+N < 0.7%
Tamb = 25 ° C
80
2.5
3.0
3.5
4.0
Power Supply Voltage (V)
4.5
5.0
Figure 57. Output noise voltage device ON
25
20
15
10
2
45
40
35
Vcc=2.2V to 5.5V
Cb=1 μ F
RL=8 Ω
Tamb=25 ° C
30 Unweighted Filter
4
A Weighted Filter
6
Closed Loop Gain
8 10
Figure 58. Signal to noise ratio vs. power supply with a weighted filter Av = 10
100
95
RL=16 Ω
90
RL=8 Ω
85
RL=4 Ω
80
75
70
Av = 10
Cb = 1 μ F
THD+N < 0.7%
Tamb = 25 ° C
2.5
3.0
3.5
4.0
Power Supply Voltage (V)
4.5
5.0
Figure 59. Output noise voltage device in standby
2.0
1.8
1.6
1.4
Unweighted Filter
1.2
1.0
0.8
A Weighted Filter
0.6
0.4
0.2
0.0
2
Vcc=2.2V to 5.5V
Cb=1 μ F
RL=8 Ω
Tamb=25 ° C
4 6
Closed Loop Gain
8 10
DocID9309 Rev 14 17/33
33
Application information TS4990
4.1
4.2
4.3
18/33
BTL configuration principle
The TS4990 is a monolithic power amplifier with a BTL output type. BTL (bridge tied load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have:
Single-ended output 1 = V out1
= V out
(V)
Single-ended output 2 = V out2
= -V out
(V) and V out1
- V out2
= 2V out
(V)
The output power is:
P out
=
2V out
L
RMS
2
------------------------------
R
For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single-ended configuration.
Gain in a typical application
The typical application schematics are shown in
.
In the flat region (no C in
effect), the output voltage of the first stage is (in Volts):
V out1
=
– V in
R
--------------
R in
For the second stage: V out2
= -V out1
(V)
The differential output voltage is (in Volts):
V out2
– V out1
= 2V in
R
--------------
R in
The differential gain named gain (G v
) for more convenience is:
G v
=
V – V
---------------------------------2
V in
=
R
--------------
R in
V out2
is in phase with V in
and V out1
is phased 180
with V terminal of the loudspeaker should be connected to V out2 in
. This means that the positive
and the negative to V out1
.
Low and high frequency response
In the low frequency region, C in
starts to have an effect. C in
forms with R in
a high-pass filter with a -3 dB cut-off frequency. F
CL
is in Hz.
F
CL
=
2
R in
C in
In the high frequency region, you can limit the bandwidth by adding a capacitor (C feed
) in parallel with R feed
. It forms a low-pass filter with a -3 dB cut-off frequency. F
CH
is in Hz.
F
CH
=
2
R feed
C feed
DocID9309 Rev 14
TS4990 Application information
The graph in Figure 60 shows an example of C
in
and C feed
influence.
Figure 60. Frequency response gain vs. C in
and C feed
10
5
0
-5
-10
-15
-20
-25
10
Cfeed = 330pF
Cfeed = 680pF
Cin = 470nF
Cfeed = 2.2nF
Cin = 22nF
Cin = 82nF
100
Frequency (Hz)
Rin = Rfeed = 22k Ω
Tamb = 25 ° C
1000 10000
4.4 Power dissipation and efficiency
Hypotheses:
Load voltage and current are sinusoidal (V out
and I out
).
Supply voltage is a pure DC source (V
CC
).
The load can be expressed as:
V out
= V
PEAK
sin t (V) and
I out
=
V
------------ (A)
R
L and
P out
=
V
2R
L
2
(W)
Therefore, the average current delivered by the supply voltage is:
I
CC
AVG
= 2
V
R
L
(A)
The power delivered by the supply voltage is:
P supply
= V
CC
I
CC
AVG
(W)
DocID9309 Rev 14 19/33
33
Application information
Note:
Therefore, the power dissipated by each amplifier is:
P diss
= P supply
- P out
(W)
P diss
=
2 2V
----------------------
R
L
P out
– P out and the maximum value is obtained when:
P
P diss out
----------------- = 0 and its value is:
P diss max
=
2
2V
-------------- (W)
2
R
L
This maximum value is only dependent on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
=
P
------------------ =
P supply
V
PEAK
-----------------------
4V
CC
The maximum theoretical value is reached when V
PEAK
= V
CC
, so:
= 78.5%
4
TS4990
4.5 Decoupling of the circuit
Two capacitors are needed to correctly bypass the TS4990: a power supply bypass capacitor C s
and a bias voltage bypass capacitor C b
.
C s
has particular influence on the THD+N in the high frequency region (above 7 kHz) and an indirect influence on power supply disturbances. With a value for C s of 1 µF, you can expect
THD+N levels similar to those shown in the datasheet.
In the high frequency region, if C s is lower than 1 µF, it increases THD+N and disturbances on the power supply rail are less filtered.
On the other hand, if C s more filtered.
is higher than 1 µF, those disturbances on the power supply rail are
C b
has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR (with input grounded and in the lower frequency region).
If C b
is lower than 1 µF, THD+N increases at lower frequencies and PSRR worsens.
If C b
is higher than 1 µF, the benefit on THD+N at lower frequencies is small, but the benefit to PSRR is substantial.
Note that C in
has a non-negligible effect on PSRR at lower frequencies. The lower the value of C in
, the higher the PSRR.
20/33 DocID9309 Rev 14
TS4990
4.6
Application information
Wake-up time (t
WU
)
When the standby is released to put the device ON, the bypass capacitor C b
is not charged immediately. Because C b
is directly linked to the bias of the amplifier, the bias will not work properly until the C b
voltage is correct. The time to reach this voltage is called wake-up time or t
WU
and specified in the electrical characteristics tables with C b
= 1 µF.
If C b
has a value other than 1 µF, refer to the graph in
Figure 61 to establish the wake-up
time.
Figure 61. Typical wake-up time vs. C b
600
Tamb=25 ° C
500 Vcc=3.3V
400
300
200
Vcc=2.6V
Vcc=5V
100
0
0.1
1 2 3
Bypass Capacitor Cb ( F)
4 4.7
Due to process tolerances, the maximum value of wake-up time is shown in
.
Figure 62. Maximum wake-up time vs. C b
600
Tamb=25 ° C
500
400
Vcc=2.6V
Vcc=3.3V
300
200
100
0
0.1
1 2 3
Vcc=5V
Bypass Capacitor Cb ( F)
4 4.7
Note: The bypass capacitor C b
also has a typical tolerance of +/-20%. To calculate the wake-up time with this tolerance, refer to the graph above (considering for example for C b
=1 µF in the range of 0.8 µF
C b
1.2 µF).
When the standby command is set, the time required to put the two output stages in high impedance and the internal circuitry in standby mode is a few microseconds. In standby mode, the bypass pin and V in pin are short-circuited to ground by internal switches. This allows a quick discharge of C b
and C in
capacitors.
DocID9309 Rev 14 21/33
33
Application information TS4990
Pop performance is intimately linked with the size of the input capacitor C in
and the bias voltage bypass capacitor C b
.
The size of C in
is dependent on the lower cut-off frequency and PSRR values requested.
The size of C b
is dependent on THD+N and PSRR values requested at lower frequencies.
Moreover, C b
determines the speed with which the amplifier turns ON. In order to reach near zero pop and click, the equivalent input constant time,
in
= (R in
+ 2 k
) x C in
(s) with R in
5 k
must not reach the
in
maximum value as indicated in
Figure 63.
in
max. versus bypass capacitor
160 Tamb=25
°
C
Vcc=3.3V
120 Vcc=2.6V
80
40 Vcc=5V
0
1 2 3
Bypass Capacitor Cb ( F)
4
By following the previous rules, the TS4990 can reach near zero pop and click even with high gains such as 20 dB.
Example:
With R in
= 22 k
and a 20 Hz, -3 dB low cut-off frequency, C in
= 361 nF. So, C in
= 390 nF with standard value which gives a lower cut-off frequency equal to 18.5 Hz. In this case,
(R in
+ 2k
) x C in
= 9.36 ms. By referring to the previous graph, if C b
= 1 µF and V
CC
= 5 V, we read 20 ms max. This value is twice as high as our current value, thus we can state that pop and click will be reduced to its lowest value.
Minimizing both C in
and the gain benefits both the pop phenomenon, and the cost and size of the application.
22/33 DocID9309 Rev 14
TS4990 Application information
The schematics in
show how to configure the TS4990 to work in differential input mode. The gain of the amplifier is:
G
VDIFF
= 2
R
R
1
In order to reach the best performance of the differential function, R
1
and R
2
should be matched at 1% max.
Figure 64. Differential input amplifier configuration
R2
Vcc
Cs
Cin
R1
Neg. Input
Cin
R1
Vin-
-
Vin+
+
Vout 1
Speaker
8 Ohms
Pos. Input
R2 -
AV = -1
+
Vout 2
Standby
Control
Bypass
Standby
Bias
TS4990
Cb
Note:
The input capacitor C in
can be calculated by the following formula using the -3 dB lower frequency required. (F
L
is the lower frequency required).
C in
2
1
(F)
R
1
F
L
This formula is true only if:
F
CB
=
2
R
1
1
(Hz)
+ R
2
C
B is 5 times lower than F
L
.
DocID9309 Rev 14 23/33
33
Application information TS4990
Example bill of materials
The bill of materials in
Table 7 is for the example of a differential amplifier with a gain of 2
and a -3 dB lower cut-off frequency of about 80 Hz.
Table 7. Bill of materials for differential input amplifier application
Pin name Functional description
R
1
R
2
C in
C b
=C s
U1
20k / 1%
20k / 1%
100 nF
1 µF
TS4990
24/33 DocID9309 Rev 14
TS4990 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 65. Flip-chip pinout (top view)
Balls are underneath
Figure 66. Marking (top view)
ST logo
Symbol for lead-free
Product and assembly code:
XXX
A90 from Tours
90S from Shenzhen
Three-digit datecode: YWW
E symbol for lead-free only
DocID9309 Rev 14 25/33
33
Package information TS4990
Figure 67. Package mechanical data for 9-bump flip-chip package
Die size: 1.60 x 1.60 mm ±30µm
Die height (including bumps): 600µm
Bump diameter: 315µm ±50µm
Bump diameter before reflow: 300µm
±10µm
Bump height: 250µm ±40µm
Die height: 350µm ±20µm
Pitch: 500µm ±50µm
Coplanarity: 50µm max
Figure 68. Daisy chain mechanical data
The daisy chain sample features two-by-two pin connections. The schematics in
illustrate the way pins connect to each other. This sample is used to test continuity on your board. Your PCB needs to be designed the opposite way, so that pins that are unconnected in the daisy chain sample, are connected on your PCB. If you do this, by simply connecting an Ohmmeter between pin A1 and pin A3, the soldering process continuity can be tested.
26/33 DocID9309 Rev 14
TS4990 Package information
Figure 69. TS4990 footprint recommendations
500
m 500
m
=250
m
75µm min.
100
m max.
=400
m typ.
=340
m min.
150
m min.
Pad in Cu 18
m with Flash NiAu (2-6
m, 0.2
m max.)
Figure 70. Tape and reel specification (top view)
Device orientation
The devices are oriented in the carrier pocket with pin number A1 adjacent to the sprocket holes.
DocID9309 Rev 14 27/33
33
Package information
Figure 71. MiniSO-8 package mechanical drawing
TS4990
28/33
Ref.
e
L
L1
L2 k ccc c
D
E
E1
A
A1
A2 b
Min.
0
0.75
0.22
0.08
2.80
4.65
2.80
0.40
Table 8. MiniSO-8 package mechanical data
Dimensions
Millimeters
Typ.
Min.
0.85
3.00
4.90
3.00
0.65
0.60
0.95
0.25
Max.
0.23
3.20
5.15
3.10
1.1
0.15
0.95
0.40
0.80
0
0.030
0.009
0.003
0.11
0.183
0.11
0.016
Inches
Typ.
0.033
0.118
0.193
0.118
0.026
0.024
0.037
0.010
0° 8°
0.10
0° 8°
0.004
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0.031
DocID9309 Rev 14
TS4990
5.3
Note:
Package information
DFN8 package information
DFN8 exposed pad (E2 x D2) is connected to pin number 7. For enhanced thermal performance, the exposed pad must be soldered to a copper area on the PCB, acting as a heatsink. This copper area can be electrically connected to pin7 or left floating.
Figure 72. DFN8 3x3x0.90 mm package mechanical drawing (pitch 0.5 mm)
SEATING
PLANE
C
D e
0.15x45°
1 2 3 4
8 7 6 b
5
D2
BOTTOM VIEW
7426334_F
A3 b
D
D2
A
A1
A2
E
E2 e
L ddd
Ref.
Table 9. DFN8 3x3x0.90 mm package mechanical data (pitch 0.5 mm)
Dimensions
Millimeters Mils
Min.
0.80
0.55
0.18
2.85
2.20
2.85
1.40
Typ.
0.90
0.02
0.65
0.20
0.25
3.00
3.00
Max.
1.00
0.05
0.80
0.30
3.15
2.70
3.15
1.75
Min.
31.5
217
7.1
112.2
86.6
112.2
55.1
Typ.
35.4
0.8
25.6
7.9
9.8
118.1
118.1
0.30
0.50
0.40
0.50
0.08
11.8
19.7
15.7
Max.
39.4
2.0
31.5
11.8
124
106.3
124
68.9
19.7
3.1
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Package information
5.4 SO-8 package information
Figure 73. SO-8 package mechanical drawing
TS4990
30/33
Ref.
c
D
H
E1
A
A1
A2 b
L k e h ccc
Min.
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.25
0.40
1°
Table 10. SO-8 package mechanical data
Dimensions
Millimeters
Typ.
Min.
Max.
1.75
0.25
4.90
6.00
3.90
1.27
0.48
0.23
5.00
6.20
4.00
0.004
0.049
0.011
0.007
0.189
0.228
0.150
Inches
Typ.
0.193
0.236
0.154
0.050
0.50
1.27
8°
0.10
0.010
0.016
1°
DocID9309 Rev 14
Max.
0.069
0.010
0.019
0.010
0.197
0.244
0.157
0.020
0.050
8°
0.004
TS4990 Ordering information
Order code
TS4990EIJT
(1)
TS4990IST
TS4990IQT
TS4990IDT
Temp. range
-40°C, +85°C
1.
Lead-free Flip-chip part number
Table 11. Order codes
Package
Flip-chip, 9 bumps
MiniSO-8
DFN8
SO-8
Packing
Tape & reel
Tape & reel
Tape & reel
Tape & reel
Marking
90
K990
K990
TS4990I
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33
Revision history TS4990
Date
1-Jul-2002
4-Sep-2003
1-Oct-2004
2-Apr-2005
May-2005
1-Jul-2005
28-Sep-2005
14-Mar-2006
21-Jul-2006
11-May-2007
17-Jan-2008
21-May-2008
30-Aug-2011
17-Jan-2019
Revision
4
5
6
1
2
3
7
8
9
10
11
12
13
14
Table 12. Document revision history
Changes
First release.
Update mechanical data.
Order code for back coating on flip-chip.
Typography error on page 1: Mini-SO-8 pin connection.
New marking for assembly code plant.
Error on Table 4 on page 5. Parameters in wrong column.
Updated mechanical coplanarity data to 50 µm (instead of 60 µm) (see
Figure 67 on page 25).
SO-8 package inserted in the datasheet.
Update of Figure 66 on page 25. Disclaimer update.
Corrected value of PSRR in Table 5 on page 6 from 1 to 61 (typical value).
Moved Table 3: Component descriptions to Section 2: Typical application schematics on page 4.
Merged daisy chain flip-chip order code table into Table 11: Order codes on page 31.
Corrected pitch error in DFN8 package information. Actual pitch is 0.5mm.
Updated DFN8 package dimensions to correspond to JEDEC databook definition (in previous versions of datasheet, package dimensions were as in manufacturer’s drawing).
Corrected error in MiniSO-8 package information (L and L1 values were inverted).
Reformatted package information.
Corrected value of output resistance vs. ground in standby mode: removed from Table 2, and added in Table 4, Table 5, and Table 6.
Updated DFN8 package (Figure 72)
Updated ECOPACK® text in Section 5: Package information
Updated
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TS4990
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