STMicroelectronics LNBH23L Datasheet
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LNBH23L
LNB supply and control IC with step-up and I²C interface
Features
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Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5
A)
Selectable output current limit by external resistor
Compliant with main satellite receivers output voltage specification
Auxiliary modulation input (EXTM pin) facilitates DiSEqC™ 1.X encoding
Accurate built-in 22 kHz tone generator suits widely accepted standards
Low-drop post regulator and high efficiency step-up PWM with integrated power NMOS allow low power losses
Overload and over-temperature internal protections with I²C diagnostic bits
LNB short circuit dynamic protection
±
4 kV ESD tolerant on output power pins
Applications
■
■
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STB satellite receivers
TV satellite receivers
PC card satellite receivers
QFN32 (5 x 5 mm)
(Exposed pad)
Description
Intended for analog and digital satellite receivers, the LNBH23L is a monolithic voltage regulator and interface IC, assembled in QFN32 5 x 5 specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.
Table 1.
Device summary
Order code
LNBH23LQTR
November 2010
Package
QFN32 (5 x 5 mm) Exposed pad
Doc ID 15335 Rev 4
Packaging
Tape and reel
1/25 www.st.com
25
Contents
Contents
LNBH23L
DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DiSEqC™ 1.X implementation by EXTM pin . . . . . . . . . . . . . . . . . . . . . . . 5
DiSEqC™ 1.X implementation with VOTX and EXTM pin connection . . . . 5
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 6
Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LNBH23L software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17
2/25 Doc ID 15335 Rev 4
LNBH23L Contents
DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 15335 Rev 4 3/25
Block diagram
Figure 1.
Block diagram
22kHz
Oscill.
..
I I ² C interface
I I ² C OLF and OTF
+
LNBH23L
4/25 Doc ID 15335 Rev 4
LNBH23L Application information
Note:
2.1
2.2
2.3
This IC has a built-in DC-DC step-up converter that, from a single source from 8 V to 15 V, generates the voltages (V
UP
) that let the linear post-regulator to work at a minimum dissipated power of 0.55 W typ. @ 500 mA load (the linear post-regulator drop voltage is internally kept at V
UP
- V
OUT
= 1.1 V typ.). An under voltage lockout circuit will disable the whole circuit when the supplied V
CC
drops below a fixed threshold (6.7 V typically).
In this document the V
OUT
is intended as the voltage present at the linear post-regulator output (V oRX
pin).
DiSEqC™ data encoding
The internal 22 kHz tone generator is factory trimmed in accordance to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin
(DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the
22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) The
TTX function must be disabled setting TTX to LOW. Besides the internal 22 kHz tone generator, the auxiliary modulation pin (EXTM) can be driven by an external 22 kHz source and in this case TTX must be set to low.
DiSEqC™ 1.X implementation by EXTM pin
In order to improve design flexibility and reduce the total application cost, an analogic modulation input pin is available (EXTM) to generate the 22 kHz tone superimposed to the
V oRX
DC output voltage. An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. If the EXTM solution is used the output R-L filter
) saving the external components cost. If this configuration is used keep TTX set to low.
The pin EXTM modulates the V oRX
voltage through the series decoupling capacitor, so that:
V oRX(AC)
= V
EXTM(AC)
x G
EXTM
Where V oRX(AC)
and V
EXTM(AC)
are, respectively, the peak to peak voltage on the V oRX
and
EXTM pins while G
EXTM
is the voltage gain from EXTM to V oRX
.
DiSEqC™ 1.X implementation with V
OTX
and EXTM pin connection
If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz tone generator signal available through the V oTX
pin to drive the EXTM pin. The V oTX
pin internal circuit must be preventively set ON by setting the TTX function to High. This can be controlled both through the TTX pin or by I²C bit. By this way the V oTX
22 kHz signal will be superimposed to the V oRX
DC voltage to generate the LNB output 22 kHz tone (see
Figure 3 ). After TTX is set to High the internal 22 kHz tone generator available through the
V oTX
pin can be activated during the 22 kHz transmission either by DSQIN pin or by the TEN bit.The DSQIN internal circuit activates the 22 kHz tone on the V oTX
output with 0.5 cycles ±
25 µs delay from the TTL signal presence on the DSQIN pin, and it stops with 1 cycles ± 25
µs delay after the TTL signal is expired. As soon as the tone transmission is expired, the
Doc ID 15335 Rev 4 5/25
Application information LNBH23L
V oTX
internal circuits must be disabled by setting the TTX to LOW. The 13 / 18 V power supply will be always provided to the LNB from the V oRX
pin.
2.4 PDC optional circuit for DiSEQC™ 1.X applications using
V
OTX
signal on to EXTM pin
In some applications, at light output current (< 50 mA) having heavy LNB output capacitive load, the 22 kHz tone can be distorted. In this case it is possible to add the "Optional" external components shown in the typical application circuits (see
between V oRX
and PDC pin. This optional circuit acts as an active pull-down discharging the output capacitance only when the internal 22 kHz tone is activated. This optional circuit is not needed in standard applications having I
OUT
> 50 mA and capacitive load up to 250 nF.
2.6
2.7
2.8
6/25
The main functions of the IC are controlled via I²C bus by writing 6 bits on the system register (SR 8 bits in write mode). On the same register there are 5 bits that can be read back (SR 8 bits in read mode) to provide the diagnostic flags of two internal monitoring functions (OTF, OLF) and three output voltage register status (EN, VSEL, LLC) received by the IC (see below diagnostic functions section). In read mode there are 3 Test bits (test 1 - 2
- 3) that must be disregarded from the MCU. While, in write mode, 2 test bits (test 4 - 5) must be always set LOW.
Output voltage selection
When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the V
SEL
bit (voltage SELect). Additionally, the LNBH23L is provided with the LLC I²C bit that increases the selected voltage value to compensate possible voltage drop along the output line. The LNBH23L is also compliant to the USA LNB power supply standards. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating or to GND but the TTX bit must be set LOW during the stand-by condition).
Diagnostic and protection functions
The LNBH23L has two diagnostic internal functions provided via I²C bus by reading 2 bits on the system register (SR bits in read mode). the diagnostic bits are, in normal operation (no failure detected), set to LOW. The diagnostic bits are dedicated to the over-temperature and over-load protections status (OTF and OLF).
Over-current and short circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short circuit condition, the device is provided with a dynamic short circuit protection. It is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current protection circuit works dynamically: as soon as an overload is detected, the output is shut-
Doc ID 15335 Rev 4
LNBH23L Application information down for a time T
OFF
, typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the system register is set to "1". After this time has elapsed, the output is resumed for a time
T
ON
= 1/10 T
OFF
= 90 ms (typ.). At the end of T
ON
, if the overload is still detected, the protection circuit will cycle again through T
OFF
and T
ON
. At the end of a full T
ON
in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to
LOW. Typical T
ON
+ T
OFF
time is 990ms and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (PCL
= 1) and, then, switching to the dynamic mode (PCL = 0) after a chosen amount of time depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to
"1" when the current clamp limit is reached and returns LOW when the overload condition is cleared.
2.9 Thermal protection and diagnostic
The LNBH23L is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to
LOW when the junction is cooled down to 135 °C (typ.)
2.10 Output current limit selection
Note:
The linear regulator current limit threshold can be set by an external resistor connected to
ISEL pin. The resistor value defines the output current limit by the equation:
I
MAX
(A) = 10000 / R
SEL where R
SEL
is the resistor connected between I limit threshold shall be 0.65 A typ with R
SEL
SEL
and GND. The highest selectable current
= 15 k
Ω
. The above equation defines the typical threshold value.
External components are needed to comply DiSEqC™ bus hardware requirements. Full compliance of the whole application with DiSEqC™ specifications is not implied by the bare use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.
Doc ID 15335 Rev 4 7/25
Pin configuration
3 Pin configuration
Figure 2.
Pin connections (bottom view)
LNBH23L
Table 2.
Pin n°
19
18
4
27
21
22
6
9
12
14
29
11
13
5
Pin description
Symbol
V
CC
V
CC–
L
LX
V
UP
V oRX
V oTX
SDA
SCL
DSQIN
TTX
Reserved
PDC
EXTM
P-GND
Name Pin function
Supply input
Supply input
NMOS drain
8 to 15 V IC DC-DC power supply.
8 to 15 V analog power supply.
Integrated N-channel power MOSFET drain.
Step-up voltage
LDO output port
Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor.
Output of the integrated low drop linear regulator. See truth tables for voltage selections and description.
Output port for 22 kHz Tone TX
Serial data
Serial clock
TX Output to the LNB. See truth tables for selection.
Bi-directional data from/to I²C bus.
DiSEqC input
Clock from I²C bus.
This pin will accept the DiSEqC code from the main µController.
The LNBH23L will use this code to modulate the internally generated 22 kHz carrier. Set to ground if not used.
TTX enable
Reserved
This pin can be used, as well as the TTX I²C bit of the system register, to control the TTX function enable before to start the
22 kHz tone transmission. Set floating or to GND if not used.
To be connected to GND.
Pull down control
To be connected to the external NPN transistor Base to reduce the 22 kHz tone distortion in case of heavy capacitive load at light output current. If not used it can be left floating.
External modulation
External Modulation Input acts on V oRX
linear regulator output to superimpose an external 22 kHz signal. Needs DC decoupling to the AC source. If not used it can be left floating.
Power ground DC-DC converter power ground.
8/25 Doc ID 15335 Rev 4
LNBH23L Pin configuration
Table 2.
Pin n°
Epad
20
15
10
28
30
1, 2, 3, 7, 8,
16, 17, 23,
24, 25, 26,
31, 32
Pin description (continued)
Symbol
Epad
A-GND
BYP
ADDR
ISEL
Reserved
Name
Exposed pad
Analog ground
By-pass capacitor
Address setting
Current selection
Reserved
Pin function
To be connected with power grounds and to the ground layer through vias to dissipate the heat.
Analog circuits ground.
Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.
Two I²C bus addresses available by setting the Address pin level voltage. See address pin characteristics table.
The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold by the equation:
I
MAX
(typ.) = 10000 / RSEL.
To be left floating. Do not connect to GND.
N.C.
Not internally connected
Not internally connected pins. These pins can be connected to
GND to improve thermal performances.
Doc ID 15335 Rev 4 9/25
Maximum ratings LNBH23L
Table 3.
Symbol
Absolute maximum ratings
(1)
Parameter Value Unit
V
CC-L
, V
CC
V
UP
I
OUT
V oRX
V oTX
V
I
V
OH
V
EXTM
LX
V
BYP
ISEL
DC power supply input voltage pins
DC input voltage
Output current
DC output pin voltage
Tone output pin voltage
Logic input voltage (TTX, SDA, SCL, DSQIN, ADDR pins)
Logic high output voltage (PDC pin)
EXTM pin voltage
LX input voltage
Internal reference pin voltage
(2)
Current selection pin voltage
T
STG
T
J
Storage temperature range
Operating junction temperature range
ESD
ESD rating with human body model (HBM) for all pins unless 4, 21, 22
ESD rating with human body model (HBM) for pins 21, 22
ESD rating with human body model (HBM) for pin 4
-0.3 to 16
-0.3 to 24
Internally limited
-0.3 to 25
-0.3 to 25
-0.3 to 7
-0.3 to 7
-0.3 to 2
-0.3 to 24
-0.3 to 4.6
-0.3 to 4.6
-50 to 150
-25 to 125
2
4
0.6
1.
Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
2.
The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.
V
°C
°C kV
V
V
V
V
V
V
V
V
V mA
Table 4.
Symbol
R thJC
R thJA
Thermal data
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient with device soldered on 2s2p PC board
Value
2
35
Unit
°C/W
°C/W
10/25 Doc ID 15335 Rev 4
LNBH23L
5 Typical application circuit
Figure 3.
DiSEqC 1.x using internal 22 kHz tone generator
Typical application circuit
C4
470nF
C6
470nF
I I
Figure 4.
DiSEqC 1.x using internal 22 kHz tone generator and "optional" PDC circuit
C4
470nF
C6
470nF
I I
Doc ID 15335 Rev 4
Byp
*R8
150 Ohm
Diode
1N4148
*R5
2.2K Ohm *C14
1nF
*R7
22 Ohm
(*) OPTIONAL components.
To be used only in case of heavy capacitive load
C11
220nF
11/25
Typical application circuit
Figure 5.
DiSEqC 1.x using external 22 kHz tone generator source through EXTM pin
LNBH23L
C4
470nF
C6
470nF to LNB
500mA max
C10
220nF
Vin
12V
C8
220nF
I I I I
R2 (RSEL)
15kOhm
C15
220nF
Table 5.
BOM list
Component
R2, R9, R5
(1)
R7
(1)
, R8
(1)
Notes
1/16 W resistors. Refer to the typical application circuit for the relative values
1/2 W resistors. Refer to the typical application circuit for the relative values
C1
C3
25 V electrolytic capacitor, 100 µF or higher is suitable
25 V, 220 µF electrolytic capacitor, ESR in the 100 m
Ω
to 350 m
Ω
range
C4, C6, C8, C10, C11, C15,
C14
(1)
25 V ceramic capacitors. Refer to the typ. appl. circuit for the relative values
D1
D2
D3
TR1
(1)
STPS130A or any similar schottky diode with V
RRM
> 25 V and I
F(AV)
higher than:
I
F(AV)
> I
OUT_MAX
x (V
UP_MAX
/V
IN_MIN
)
BAT43, 1N5818, or any schottky diode with I
F(AV)
> 0.2 A, V
RRM
> 25 V, V
F
< 0.5 V. To be placed as close as possible to V oRX
pin
1N4001-07 or any similar general purpose rectifier
BC817 or similar NPN general-purpose transistor.
L1
22 µH inductor with I
SAT
> I
PEAK
where I
PEAK
is the boost converter peak current (see
Equation 1 )
1.
These components can be added to avoid any 22 kHz tone distortion due to heavy capacitive output loads. If not needed they can be removed leaving the PDC pin floating.
12/25 Doc ID 15335 Rev 4
LNBH23L Typical application circuit
To calculate the boost converter peak current (I
PEAK
) of L1, use the following formula:
Equation 1
Doc ID 15335 Rev 4 13/25
I²C bus interface
6 I²C bus interface
LNBH23L
Data transmission from main microprocessor to the LNBH23L and vice versa takes place through the 2 wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
6.2
As shown in
Figure 6 , the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and stop condition
As shown in
Figure 7 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
6.4 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see
). The peripheral (LNBH23L) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH23L won't generate acknowledge if the V
CC
supply is below the under voltage lockout threshold (6.7 V typ.).
6.5 Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH23L, the microprocessor can use a simpler transmission: simply it waits one clock cycle without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
14/25 Doc ID 15335 Rev 4
LNBH23L
Figure 6.
Data validity on the I²C bus
I²C bus interface
Figure 7.
Timing diagram of I²C bus
Figure 8.
Acknowledge on the I²C bus
Doc ID 15335 Rev 4 15/25
LNBH23L software description
7 LNBH23L software description
LNBH23L
The interface protocol comprises:
●
●
●
●
A start condition (S)
A chip address byte (the LSB bit determines read (=1)/write (=0) transmission)
A sequence of data (1 byte + acknowledge)
A stop condition (P)
S
MSB
0 0
Section address (A or B)
0 1 0 1
LSB
X R/W ACK
MSB
Data
LSB
ACK P
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, two addresses selectable by ADDR pin (see Table 10
)
7.2
Mode
Write
Read
System register (SR, 1 byte)
MSB
PCL
TEST1
TTX
TEST2
TEN
TEST3
LLC
LLC
Write = control bits functions in write mode
Read= diagnostic bits in read mode.
All bits reset to 0 at Power-on
VSEL
VSEL
7.3
EN
EN
TEST4
OTF
LSB
TEST5
OLF
Transmitted data (I²C bus write mode)
When the R/W bit in the chip address is set to 0, the main microprocessor can write on the system register (SR) of the LNBH23L via I²C bus. 6 bits are available and can be written by
the microprocessor to control the device functions as per the below truth table Table 6
.
16/25 Doc ID 15335 Rev 4
LNBH23L LNBH23L software description
Table 6.
Truth table
PCL TTX TEN LLC VSEL EN TEST4 TEST5
0
1
X
0
0
0
0
0
1
1
0
1
X
X
X
0
0
1
X
0
0
1
1
X
0
1
0
1
X
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
V oRX
= 13.4 V, V
UP
= 14.5 V, (V
UP
- V oRX
= 1.1 V)
V oRX
= 18.4 V, V
UP
= 19.5 V, (V
UP
- V oRX
= 1.1 V)
V oRX
= 14.4 V, V
UP
=15.5 V, (V
UP
-V oRX
=1.1 V)
V oRX
= 19.5V, V
UP
=20.6 V, (V
UP
-V oRX
=1.1 V)
Internal 22 kHz generator disabled, EXTM modulation enabled
Internal 22 kHz controlled by DSQIN pin (only if
TTX=1)
Internal 22 kHz tone output is always activated
V oRX
output is ON, V oTX
Tone generator output is
OFF
V oRX
output is ON, V oTX
Tone generator output is
ON
Pulsed (Dynamic) current limiting is selected
Static current limiting is selected
Power block disabled
X = don't care
All values are typical unless otherwise specified
Valid with TTX pin floating
LNBH23L can provide to the MCU master a copy of the diagnostic system register information via I²C bus in read mode. The read mode is master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH23L issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the
Master can:
● Acknowledge the reception, starting in this way the transmission of another byte from the LNBH23L
● No acknowledge, stopping the read mode communication
Three bits of the register are read back as a copy of the corresponding write output voltage register status (LLC, VSEL, EN), two bits convey diagnostic information about the overtemperature (OTF), output over-load (OLF) and three bit are for internal usage (TEST1-2-3) and must be disregarded by the MCU software. In normal operation the diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to one. At start-up all the bits are reset to zero.
Doc ID 15335 Rev 4 17/25
18/25
LNBH23L software description LNBH23L
Table 7.
Register
TEST1 TEST2 TEST3 LLC VSEL EN OTF OLF
X X X
These bits are read exactly the same as they were left after last write operation
0
1
Function
T
J
< 135°C, normal operation
T
J
> 150°C, power blocks disabled
0 I
O
< I
OMAX
, normal operation
1 I
O
> I
OMAX
, Overload protection triggered
These bits status must be disregarded by the
MCU.
7.5
Values are typical unless otherwise specified.
x = don’t care.
Power-on I²C interface reset
I²C interface built in LNBH23L is automatically reset at power-on. As long as the V
CC stays below the under voltage lockout (UVL) threshold (6.7 V), the interface does not respond to any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the V
CC
rises above 7.3 V typ. The I²C interface becomes operative and the SR can be configured by the main microprocessor. This is due to 500 mV of hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset circuit.
It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL
compatible and can be set as per address pin characteristics Table 10 .
LNBH23L helps system designer to implement DiSEqC 1.x protocol by allowing an easy
PWK modulation of the 22 kHz carrier through the EXTM and V oTX
pins. Full compliance of the system to the specification is thus not implied by the bare use of the LNBH23L (see
and
Doc ID 15335 Rev 4
LNBH23L Electrical characteristics
Refer to the typical application circuits, T
J
I
OUT
from 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=TEST4=TEST5=TTX=0, R
SEL
=15 k
Ω
, DSQIN=LOW, V
= 50 mA, unless otherwise stated. Typical values are referred to T
J
IN
=12 V,
= 25 °C. V
OUT
=
V oRX
pin voltage. See software description section for I²C access to the system register.
Table 8.
Symbol
Electrical characteristics
Parameter Test conditions
V
V
V
I
IN
IN
OUT
OUT
Supply voltage
Supply current
Output voltage
Output voltage
I
OUT
=500mA, VSEL=LLC=1
I
OUT
=0
EN=TEN=TTX=1, I
OUT
=0,
PDC circuit not connected
EN=0
VSEL=1
I
OUT
=500mA
VSEL=0
I
OUT
=500mA
LLC=0
LLC=1
LLC=0
LLC=1
F
V
V
T
A
D t
TONE r
, t f
V
PDC_OL
I
PDC_OZ
G
I
I
MAX
T
OUT
OUT
SC
OFF
ON
TONE
TONE
EXTM
Line regulation
Load regulation
Output current limiting thresholds
VSEL=0
V
IN
=8 to 15V
VSEL=1
VSEL=0 or 1 I
OUT
from 50 to 500mA
RSEL=15 k
Ω
RSEL= 22 k
Ω
VSEL=0/1, AUX=0/1 Output short circuit current
Dynamic overload protection
OFF time
PCL=0, output shorted
Dynamic overload protection
ON time
PCL=0, output shorted
Tone frequency
Tone amplitude
Tone duty cycle
Tone rise or fall time
PDC pin logic LOW
PDC pin leakage current
External modulation gain
DSQIN=HIGH or TEN=1, TTX=1
(Using internal tone generator)
DSQIN=HIGH or TEN=1, TTX=1,
DiSEqC 1.X configuration using internal generator, I
OUT
from 0 to
500mA, C
OUT
from 0 to 750nF, PDC
Optional circuit connected to V oRX
rail
DSQIN=HIGH or TEN=1, TTX=1
(Using internal tone generator)
DSQIN=HIGH or TEN=1, TTX=1
(Using internal tone generator)
I
PDC
=2mA
V
PDC
=5V
Δ
V
OUT
/
Δ
V
EXTM
, freq. from 10 kHz to
50 kHz
Min.
8
17.8
12.8
500
300
18
0.4
40
5
Typ.
Max.
Unit
12
7
15
15
V
20
2
18.4
19.5
13.4
14.4
5
5
1000
900
T
OFF
/10
22
0.650
50
8
0.3
1
1.8
40
19.2
14
40
60
200
800
600
26 mA
V mV mA mA ms kHz
0.9
V
PP
60
15
%
µs
V
µA
Doc ID 15335 Rev 4 19/25
Electrical characteristics LNBH23L
Table 8.
Symbol
Electrical characteristics (continued)
Parameter Test conditions
V
Z
EXTM
EXTM
Eff
DC-DC
F
SW
External modulation input voltage
External modulation impedance
EXTM AC coupling
DC-DC converter efficiency I
OUT
=500mA
DC-DC converter switching frequency
(1)
DSQIN,TTX, pin logic low
DSQIN,TTX, pin logic high
V
IL
V
IH
I
IH
I
OBK
T
SHDN
Δ
T
SHDN
DSQIN,TTX, pin input current V
IH
=5V
Output backward current EN=0, V
OBK
=21V
Thermal shut-down threshold
Thermal shut-down hysteresis
1.
External signal maximum voltage for which the EXTM function is guaranteed.
Min.
2
Table 9.
Symbol
I²C electrical characteristics
(1)
Parameter Test conditions
V
IL
V
IH
I
I
V
OL f
MAX
LOW level input voltage
HIGH level input voltage
Input current
Low level output voltage
SDA, SCL
SDA, SCL
SDA, SCL, V
I
= 0.4 to 4.5V
SDA (open drain), I
OL
= 6mA
Maximum clock frequency SCL
1.
T
J
from 0 to 85 °C, V
I
= 12 V.
Min.
Typ.
Max.
Unit
0.8
2
-10
400
10
0.6
V
V
µA
V kHz
Table 10.
Address pins characteristics
(1)
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
V
V
ADDR-1
ADDR-2
"0001010(R/W)" Address pin voltage range
R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)
"0001011(RW)" Address pin voltage range
R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)
V
ADDR-3
(2)
"0001000(RW)" Address pin voltage range
R/W bit determines the transmission mode: read (R/W=1) write (R/W=0)
0
2
0
0.8
5
5
1.
T
J
from 0 to 85 °C, V
I
= 12 V
2.
This I²C address is reserved only for internal usage. Do not use this address with other I²C peripherals to avoid address conflicts.
V
V
V
20/25 Doc ID 15335 Rev 4
LNBH23L
9 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Doc ID 15335 Rev 4 21/25
Package mechanical data
Table 11.
QFN32 (5 x 5 mm) mechanical data
Dim.
Min.
0.80
0
D
D2
E
E2
A
A1
A3 b e
L ddd
0.18
4.85
3.20
4.85
3.20
0.30
Figure 9.
QFN32 package dimensions
(mm.)
Typ.
0.90
0.02
0.20
0.25
5.00
5.00
0.50
0.40
Max.
1.00
0.05
0.30
5.15
3.70
5.15
3.70
0.50
0.08
LNBH23L
22/25 Doc ID 15335 Rev 4
7376875/E
Dim.
N
T
Ao
A
C
D
Bo
Ko
Po
P
LNBH23L
Min.
Min.
Package mechanical data
Tape & reel QFNxx/DFNxx (5x5 mm.) mechanical data
mm.
Typ.
inch.
Typ.
Max.
33 0
1 3 .2
Max.
12.
99 2
0.51
9 12.
8
20.2
99
0.504
0.7
9 5
3 .
898 101
14.4
3 .
9 76
0.567
5.25
5.25
1.1
4
8
0.207
0.207
0.04
3
0.157
0.
3 15
Doc ID 15335 Rev 4 23/25
Revision history
10 Revision history
LNBH23L
Table 12.
Document revision history
Date
27-Jan-2009
18-May-2009
09-Sep-2009
29-Nov-2010
Revision
1
2
3
4
Changes
Initial release.
Modified:
Figure 3 on page 11 , Figure 4 on page 11 and
.
Added: Z
EXTM
.
Modified: I
IN
, A
TONE
condition
.
Modified Table 10 on page 20 .
24/25 Doc ID 15335 Rev 4
LNBH23L
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