STMicroelectronics STH47N60DM6-7AG Datasheet

STH47N60DM6-7AG
Datasheet
Automotive N-channel 600 V, 70 mΩ typ., 36 A MDmesh™ DM6
Power MOSFET in an H²PAK-7 package
Features
TAB
7
Order code
VDS
RDS(on) max.
ID
STH47N60DM6-7AG
600 V
80 mΩ
36 A
1
Prerelease product(s)
H 2PAK-7
Drain(TAB)
•
•
•
Designed for automotive applications
Fast-recovery body diode
Lower RDS(on) x area vs previous generation
•
•
•
•
•
Low gate charge, input capacitance and resistance
100% avalanche tested
Extremely dv/dt ruggedness
Zener-protected
Excellent switching performance thanks to the extra driving source pin
Gate(1)
Applications
Driver
source (2)
Power
source (3, 4, 5, 6, 7)
N-chG1DS2PS34567DTABZ
•
Switching applications
Description
This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM6 fastrecovery diode series. Compared with the previous MDmesh fast generation, DM6
combines very low recovery charge (Qrr), recovery time (trr) and excellent
improvement in RDS(on) per area with one of the most effective switching behaviors
available in the market for the most demanding high-efficiency bridge topologies and
ZVS phase-shift converters.
Product status link
STH47N60DM6-7AG
Product summary
Order code
STH47N60DM6-7AG
Marking
47N60DM6
Package
H²PAK-7
Packing
Tape and reel
DS11677 - Rev 2 - March 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STH47N60DM6-7AG
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Value
Unit
Gate-source voltage
±25
V
ID
Drain current (continuous) at TC = 25 °C
36
A
ID
Drain current (continuous) at TC = 100 °C
23
A
ID (1)
Drain current (pulsed)
137
A
PTOT
Total power dissipation at TC = 25 °C
250
W
dv/dt(2)
Peak diode recovery voltage slope
50
dv/dt(3)
MOSFET dv/dt ruggedness
100
VGS
Prerelease product(s)
TJ
Parameter
Operating junction temperature range
Tstg
Storage temperature range
V/ns
-55 to 150
°C
Value
Unit
1. Pulse width limited by safe operating area
2. ISD ≤ 36 A, di/dt ≤ 800 A/μs, VDS (peak) < V(BR)DSS, VDD = 480 V
3. VDS ≤ 480 V
Table 2. Thermal data
Symbol
Rthj-case
Rthj-pcb
(1)
Parameter
Thermal resistance junction-case
0.5
Thermal resistance junction-pcb
30
°C/W
1. When mounted on FR-4 board of 1 inch², 2oz Cu.
Table 3. Avalanche characteristics
Symbol
IAR
EAS
DS11677 - Rev 2
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by Tjmax)
Single pulse avalanche energy
(starting Tj = 25°C, ID = IAR, VDD = 100 V)
Value
Unit
7
A
700
mJ
page 2/14
STH47N60DM6-7AG
Electrical characteristics
2
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 4. On/off state
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown voltage
VGS= 0 V, ID = 1 mA
Min.
Typ.
600
Zero gate voltage drain current
1
µA
100
µA
±1
µA
4
4.75
V
70
80
mΩ
Min.
Typ.
Max.
Unit
-
2350
-
pF
-
160
-
pF
-
2
-
pF
VGS = 0 V, VDS = 600 V,
TC = 125 °C(1)
Prerelease product(s)
IGSS
Gate body leakage current
VDS = 0 V, VGS = ±25 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 18 A
Unit
V
VGS = 0 V, VDS = 600 V
IDSS
Max.
3.25
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Coss eq.(1)
Equivalent output capacitance
VDS = 0 to 480 V, VGS = 0 V
-
416
-
pF
RG
Intrinsic gate resistance
f = 1 MHz open drain
-
1.6
-
Ω
Qg
Total gate charge
VDD = 480 V, ID = 36 A,
-
55
-
nC
Qgs
Gate-source charge
VGS = 0 to 10 V
-
12
-
nC
Qgd
Gate-drain charge
(see Figure 14. Test circuit for gate
charge behavior)
-
31
-
nC
VDS = 100 V, f = 1 MHz, VGS = 0 V
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS11677 - Rev 2
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Turn-on delay time
VDD= 300 V, ID = 18 A,
-
23
-
ns
Rise time
RG = 4.7 Ω, VGS = 10 V
-
5.5
-
ns
Turn-off delay time
(see Figure 13. Test circuit for
resistive load switching times
and Figure 18. Switching time
waveform)
-
57
-
ns
-
9
-
ns
Fall time
page 3/14
STH47N60DM6-7AG
Electrical characteristics
Table 7. Source-drain diode
Symbol
ISD
ISDM(1)
(2)
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
36
A
Source-drain current (pulsed)
-
137
A
1.6
V
Forward on voltage
ISD = 36 A, VGS = 0 V
-
trr
Reverse recovery time
ISD = 36 A, di/dt = 100 A/µs,
-
115
ns
Qrr
Reverse recovery charge
VDD = 60 V
-
0.54
µC
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
-
9.5
A
trr
Reverse recovery time
ISD = 36 A, di/dt = 100 A/µs,
-
210
ns
Qrr
Reverse recovery charge
VDD = 60 V, Tj = 150 °C
-
2.1
µC
IRRM
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
-
20.4
A
Min.
Typ.
Max.
Unit
±30
-
-
V
VSD
IRRM
Prerelease product(s)
Parameter
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 8. Gate-source Zener diode
Symbol
V(BR)GSO
Parameter
Gate-source breakdown voltage
Test conditions
IGS = ±1 mA, ID = 0 A
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for
additional external componentry.
DS11677 - Rev 2
page 4/14
STH47N60DM6-7AG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
GADG200220171036SOA
ID
(A) Operation in this area is
limited by R DS(on)
10 2
10 1
tp =10 µs
tp =100 µs
10 0
T j ≤ 150 °C
T c = 25°C
single pulse
Prerelease product(s)
10 -1
tp =1 ms
tp =10 ms
10 -2
10 -1
10 0
10 1
VDS (V)
10 2
Figure 3. Output characteristics
ID
(A)
Figure 4. Transfer characteristics
ID
(A)
GADG170220171018OCH
VGS = 10 V
VGS = 9 V
120
GADG170220171019TCH
120
VGS = 8 V
100
VDS = 20 V
100
80
80
VGS = 7 V
60
60
40
40
VGS = 6 V
20
0
0
4
8
12
16
20
VDS (V)
Figure 5. Gate charge vs gate-source voltage
0
4
RDS(on)
(mΩ)
12
76
10
74
400
8
72
300
6
70
200
4
68
100
2
66
GADG170220171019QVG VGS
VDD = 480 V
ID = 36 A
600
500
0
0
DS11677 - Rev 2
VDS
10
20
30
40
50
60
0
Qg (nC)
6
7
8
9
VGS (V)
Figure 6. Static drain-source on-resistance
(V)
VDS
(V)
5
64
0
GADG170220171016RID
VGS = 10 V
6
12
18
24
30
36
ID (A)
page 5/14
STH47N60DM6-7AG
Electrical characteristics (curves)
Figure 7. Capacitance variations
C
(pF)
Figure 8. Normalized gate threshold voltage vs
temperature
GADG170220171018CVR
VGS(th)
(norm.)
10 4
GADG191220180856VTH
1.1
CISS
10 3
1.0
0.9
10 2
f = 1 MHz
0.8
10 1
CRSS
Prerelease product(s)
10 0
10 -1
10 0
10 1
VDS (V)
10 2
Figure 9. Normalized on-resistance vs temperature
RDS(on)
(norm.)
GADG191220180856RON
0.7
0.6
-75
2.0
1.05
0.95
0.5
0.90
-25
25
75
125
Tj (°C)
Figure 11. Source-drain diode forward characteristics
VSD
(V)
75
125
Tj (°C)
GADG191220180856BDV
ID = 1 mA
1.00
1.0
0
-75
25
V(BR)DSS
(norm.)
1.10
VGS = 10 V
-25
Figure 10. Normalized V(BR)DSS vs temperature
2.5
1.5
ID = 250 µA
COSS
GADG170220171018SDF
1.2
TJ = -50 °C
TJ = 150 °C
0.8
-25
25
75
125
Tj (°C)
Figure 12. Output capacitance stored energy
EOSS
(µJ)
GIPD280120191305EOS
18
15
TJ = 25 °C
1
0.85
-75
12
9
0.6
6
0.4
0.2
0
DS11677 - Rev 2
3
6
12
18
24
30
36
ISD (A)
0
0
100
200
300
400
500
600
VDS (V)
page 6/14
STH47N60DM6-7AG
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
Prerelease product(s)
1 kΩ
AM01469v1
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
B
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Switching time waveform
Figure 17. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
VD
toff
td(off)
tr
tf
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS11677 - Rev 2
page 7/14
STH47N60DM6-7AG
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1
H²PAK-7 package information
Prerelease product(s)
Figure 19. H²PAK-7 package outline
DM00249216_4
DS11677 - Rev 2
page 8/14
STH47N60DM6-7AG
H²PAK-7 package information
Table 9. H²PAK-7 package mechanical data
Prerelease product(s)
Dim.
mm
Min.
Max.
A
4.30
4.80
A1
0.03
0.20
C
1.17
1.37
e
2.34
2.74
e1
4.88
5.28
e2
7.42
7.82
E
0.45
0.60
F
0.50
0.70
H
10.00
10.40
H1
7.40
7.60
L
14.75
15.25
L1
1.27
1.40
L2
4.35
4.95
L3
6.85
7.25
M
1.90
2.50
R
0.20
0.60
V
0°
8°
Figure 20. H²PAK-7 recommended footprint
footprint_DM00249216_4
Note:
DS11677 - Rev 2
Dimensions are in mm.
page 9/14
STH47N60DM6-7AG
Packing information
4.2
Packing information
Figure 21. Tape outline
10 pitches cumulative
tolerance on tape +/- 0.2 mm
T
P0
Top cover
tape
P2
D
E
F
K0
W
B0
A0
P1
D1
Prerelease product(s)
User direction of feed
R
Bending radius
User direction of feed
AM08852v2
DS11677 - Rev 2
page 10/14
STH47N60DM6-7AG
Packing information
Figure 22. Reel outline
T
REEL DIMENSIONS
40 mm min.
Access hole
At slot location
B
D
C
N
A
G measured
Prerelease product(s)
Tape slot
In core for
Full radius
At hub
Tape start
Table 10. Tape and reel mechanical data
Tape
Dim.
DS11677 - Rev 2
Reel
mm
mm
Dim.
Min.
Max.
Min.
Max.
A0
10.5
10.7
A
B0
15.7
15.9
B
1.5
D
1.5
1.6
C
12.8
D1
1.59
1.61
D
20.2
E
1.65
1.85
G
24.4
F
11.4
11.6
N
100
K0
4.8
5.0
T
P0
3.9
4.1
P1
11.9
12.1
Base quantity
1000
P2
1.9
2.1
Bulk quantity
1000
R
50
T
0.25
0.35
W
23.7
24.3
330
13.2
26.4
30.4
page 11/14
STH47N60DM6-7AG
Revision history
Table 11. Document revision history
Date
Revision
09-Aug-2017
1
Changes
Initial release.
Modified title and features on cover page.
06-Mar-2019
2
Modified Section 1 Electrical ratings, Section 2 Electrical characteristics and
Section 2.1 Electrical characteristics (curves).
Prerelease product(s)
Minor text changes.
DS11677 - Rev 2
page 12/14
STH47N60DM6-7AG
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
H²PAK-7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Prerelease product(s)
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS11677 - Rev 2
page 13/14
STH47N60DM6-7AG
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Prerelease product(s)
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS11677 - Rev 2
page 14/14
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