STLD110N10F7
Datasheet
N-channel 100 V, 5 mΩ typ., 107 A STripFET™ F7 Power MOSFET in a
PowerFLAT™ 5x6 dual side cooling package
G(4)
D(5, 6, 7, 8)
S(1, 2, 3)
AM15540v4
Features
Order code
STLD110N10F7
V
DS
100 V
• Among the lowest R
DS(on)
on the market
• Excellent FoM (figure of merit)
• Low C rss
/C iss
ratio for EMI immunity
• High avalanche ruggedness
R
DS(on)
max.
6 mΩ
I
D
107 A
Applications
• Switching applications
Description
This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
Product status link
STLD110N10F7
Package
Packing
Product summary
Order code
Marking
STLD110N10F7
110
PowerFLAT™ 5x6 dual side cooling
Tape and reel
DS11930 - Rev 4 - February 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STLD110N10F7
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
GS
Drain-source voltage
Gate-source voltage
Parameter
I
D
(1)
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed) I
DM
(2) (1)
P
I
TOT
D
(3)
(1)
(2)
Total power dissipation at T
C
= 25 °C
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
= 100 °C
Drain current (pulsed) I
DM
(2) (3)
P
TOT
(3)
T
J
T stg
Total power dissipation at T pcb
= 25 °C
Operating junction temperature range
Storage temperature range
1. This value is rated according to R thj-case
bottom side.
2. Pulse width limited by safe operating area
3. This value is rated according to R thj-pcb
Table 2. Thermal data
Symbol
R thj-c top side
R thj-c bottom side
R thj-pcb
(1)
Parameter
Thermal resistance junction-case top side
Thermal resistance junction-case bottom side
Thermal resistance junction-pcb
1. When mounted on 1 inch² 2 Oz. Cu board, t ≤ 10 s
Value
100
±20
107
80
428
150
21
14
84
4.8
- 55 to 175
A
A
A
Unit
V
V
A
A
W
A
W
°C
Value
2.8
1
31.3
Unit
°C/W
DS11930 - Rev 4 page 2/13
2
STLD110N10F7
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 3. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
Test conditions
= 0 V, I
D
= 250 μA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate body leakage current
Gate threshold voltage
Static drain-source onresistance
V
GS
= 0 V, V
DS
= 100 V
V
GS
= 0 V, V
DS
= 100 V,
Tj = 125 °C (1)
V
V
DS
V
DS
GS
1. Defined by design, not subject to production test.
= 0 V, V
= V
GS
GS
, I
D
= 20 V
= 250 μA
= 10 V, I
D
= 10 A
Min.
100
2.5
Typ.
Max.
5
1
10
100
4.5
6
µA nA
V mΩ
Unit
V
µA
Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
Table 4. Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
= 50 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 50 V, I
D
= 21 A,
V
GS
= 0 to 10 V (see
Figure 13. Test circuit for gate charge behavior )
-
-
-
-
Min.
-
-
39
72
30
17
Typ.
5117
992
-
-
-
-
Max.
-
pF nC nC nC
Unit pF pF
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 50 V, I
D
= 10 A, R
G
= 4.7 Ω,
V
GS
= 10 V (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform
)
Min.
-
-
-
-
Typ.
25
36
52
21
Max.
-
-
-
-
Unit ns ns ns ns
DS11930 - Rev 4 page 3/13
STLD110N10F7
Electrical characteristics
Table 6. Source-drain diode
Symbol
V
SD
(1)
I t rr
Q rr
RRM
Parameter
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
V
GS
= 0 V, I
SD
= 21 A
I
SD
= 21 A, di/dt = 100 A/µs,
V
DD
= 80 V, T j
= 150 °C
(see
Figure 14. Test circuit for inductive load switching and diode recovery times
)
1. Pulse test: pulse duration = 300 µs, duty cycle 1.5%
Min.
-
-
-
-
Typ.
Max.
1.2
77
150
4.3
Unit
V ns nC
A
DS11930 - Rev 4 page 4/13
STLD110N10F7
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GADG040420181116SOA
10 2
10 1
Operation in this area is limited by R
DS(on)
10 0
10 -1
10 -2
10 -1 10 0
T j
T
C
≤ 175 °C
= 25 °C single pulse
10 1 t p
= 100µs t p
= 1ms t p
= 10ms
V
DS
(V)
Figure 3. Output characteristics
80
60
40
I
D
(A)
V
GS
=8, 9, 10 V
140
120
100
V
GS
= 7 V
GADG040420181133OCH
V
GS
= 6 V
20
V
GS
= 5 V
0
0 1 2 3 4 5 6 7 8 9 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
AM16086v1 V
GS
(V)
12
V
DD
=50V
I D =21A
10
8
6
4
2
0
0 20 40 60 80 Q g
(nC)
Figure 2. Thermal impedance
K
δ=0.5
GADG040420181116ZTH
10 -1
0.2
0.1
0.05
0.02
0.01
Single pulse
10 -2
Z th
=k*R thj-c
10 -3
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
I
D
(A)
50
Figure 4. Transfer characteristics
V
DS
=6 V
GADG040420181134TCH
40
30
20
T j
T j
=25 °C
=175 °C
10
T j
=-55 °C
0
0 1 2 3 4 5 6 7 8 9 V
GS
(V)
Figure 6. Static drain-source on-resistance
AM16087v1
R
DS(on)
(m Ω )
5.06
V GS =10V
5.04
5.02
5.00
4.98
4.96
4.94
2 4 6 8 10 12 14 16 18 20 I
D
(A)
DS11930 - Rev 4 page 5/13
STLD110N10F7
Electrical characteristics (curves)
Figure 7. Capacitance variations
AM16088v1
C
(pF)
6000
5000 Ciss
4000
3000
2000
1000
0
0 10 20 30 40 50 60 70 80
Coss
Crss
V DS (V)
Figure 9. Normalized on-resistance vs temperature
AM16090v1
R DS(on)
(norm)
2
1.8
I D =10 A
V GS =10 V
1.6
1.4
1.2
1
0.8
0.6
0.4
-75 -50 -25 0 25 50 75 100 125 150 T J (°C)
Figure 11. Source-drain diode forward characteristics
AM16092v1
V
SD
(V)
T
J
=-55°C
0.9
T J =25°C
0.8
0.7
0.6
T J =175°C
0.5
0.4
2 4 6 8 10 12 14 16 18 20 I
SD
(A)
Figure 8. Normalized gate threshold voltage vs temperature
AM16089v1 V
GS(th)
(norm)
1.2
1.1
1
0.9
0.8
0.7
I
D
=250µA
0.6
0.5
0.4
-75 -50 -25 0 25 50 75 100 125 150 T
J
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm)
AM15955v1
I D =250µA
1.04
1.02
1.00
0.98
0.96
0.94
-75 -50 -25 0 25 50 75 100 125 150 T J (°C)
DS11930 - Rev 4 page 6/13
STLD110N10F7
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
3.3
µF
S
+
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V (BR)DSS
V D
I
DM
I D
V DD V DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 17. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11930 - Rev 4 page 7/13
4
4.1
STLD110N10F7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 dual side cooling package information
Figure 18. PowerFLAT™ 5x6 dual side cooling package outline
DS11930 - Rev 4
Plated Area
8548760_2 page 8/13
DS11930 - Rev 4
STLD110N10F7
PowerFLAT™ 5x6 dual side cooling package information
Dim.
e
I
L
L1
L2
ϑ
ϑ1 j
D2
D3
E
E1
E2
E3
E4 b c
A
A1
D
D1
Table 7. PowerFLAT™ 5x6 dual side cooling mechanical data
Min.
0.66
0.60
0.33
0.15
mm
Typ.
0.71
4.06
2.80
3.525
1.05
4.20
0.15
0.925
0.45
0.43
0.203
5.00 BSC
4.21
2.40 BSC
3.30
6.00 BSC
3.675
1.20
3.80 BSC
4.70
1.27 BSC
0.25
1.05
0.575
12° BSC
7° BSC
0.20 BSC
3.80
3.825
1.35
5.20
Max.
0.76
0.75
0.53
0.30
4.36
0.15
0.35
1.175
0.70
Figure 19. PowerFLAT™ 5x6 dual side cooling recommended footprint (dimensions are in mm) page 9/13
4.2
STLD110N10F7
PowerFLAT™ 5x6 dual side cooling packing information
PowerFLAT™ 5x6 dual side cooling packing information
Figure 20. PowerFLAT™ 5x6 dual side cooling tape (dimensions are in mm)
Figure 21. PowerFLAT™ 5x6 dual side cooling reel (dimensions are in mm)
8548087_REV1
DS11930 - Rev 4 page 10/13
STLD110N10F7
Revision history
Table 8. Document revision history
Date
16-Nov-2016
19-Dec-2016
09-Apr-2018
26-Feb-2019
Revision
1 First release
2
3
4
Changes
Updated title and features in cover page.
Minor text changes.
Removed maturity status indication from cover page. The document status is preliminary data.
Updated Table 6. Source-drain diode and inserted Section 2.1 Electrical characteristics (curves).
Inserted Section 4.2 PowerFLAT™ 5x6 dual side cooling packing information.
Modified Table 3. On/off states
.
Minor text changes.
DS11930 - Rev 4 page 11/13
STLD110N10F7
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
PowerFLAT™ 5X6 dual side cooling package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
PowerFLAT™ 5x6 dual side cooling packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DS11930 - Rev 4 page 12/13
STLD110N10F7
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DS11930 - Rev 4 page 13/13
