STLD125N4F6AG
Automotive-grade Nchannel 40 V, 2.4 mΩ typ., 120 A
STripFET™ F6 Power MOSFET in a PowerFLAT™ 5x6 DSC
Datasheet - production data
Figure 1: Internal schematic diagram
D(5, 6, 7, 8)
G(4)
Features
Order code V
DS
R
DS(on)
max.
STLD125N4F6AG 40 V 3.0 mΩ
AEC-Q101 qualified
Very low on-resistance
Very low gate charge
High avalanche ruggedness
Low gate drive power loss
Wettable flank package
I
D
120 A
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using the STripFET™ F6 technology with a new trench gate structure. The resulting
Power MOSFET exhibits very low R
DS(on)
in all packages.
Order code
STLD125N4F6AG
S(1, 2, 3)
Marking
125
AM15540V4
Table 1: Device summary
Package
PowerFLAT™ 5x6 dual side cooling
Packaging
Tape and reel
July 2017 DocID029009 Rev 4
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STLD125N4F6AG
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT™ 5x6 dual side cooling package information ................ 9
PowerFLAT™ 5x6 dual side cooling packing information ............... 11
5 Revision history ............................................................................ 12
2/13 DocID029009 Rev 4
STLD125N4F6AG
1 Electrical ratings
Symbol
V
DS
V
GS
I
D
(1)(2)
I
D
(2)
I
DM
(2)(3)
P
TOT
(2)
T
J
T stg
Table 2: Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Operating junction temperature range
Storage temperature range
Notes:
(1)
Limited by package.
(2)
The value is rated according to R thj-case bottom side
.
(3)
Pulse width limited by safe operating area.
Symbol
Table 3: Thermal data
Parameter
R thj-c top side
R thj-c bottom side
R
thj-pcb
(1)
Thermal resistance junction-case top side
Thermal resistance junction-case bottom side
Thermal resistance junction-pcb
Notes:
(1)
When mounted on 1 inch² 2 Oz. Cu board, t
≤ 10 s
Symbol
Table 4: Avalanche characteristics
Parameter
I
AV
E
AS
Avalanche current, repetitive or not repetitive (pulse width limited by maximum junction temperature)
Single pulse avalanche energy (T j
= 25 °C, I
C
= I
AV
, V
DD
= 16 V)
Electrical ratings
Value
40
±20
120
101
480
130
-55 to 175
Value
3.0
1.14
31.3
Unit
V
V
A
A
A
W
°C
Unit
°C/W
Value Unit
90 A
150 mJ
DocID029009 Rev 4 3/13
Electrical characteristics
2 Electrical characteristics
STLD125N4F6AG
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
I
GSS
V
GS(th)
Gate threshold voltage
V
GS
= 0 V, I
D
= 1 mA
Zero gate voltage Drain current
V
GS
= 0 V, V
DS
= 16 V
V
GS
= 0 V, V
DS
= 16 V,
Tj = 125 °C (1)
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
R
DS(on)
Static drain-source on-resistance
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 75 A
V
GS
= 6.5 V, I
D
= 75 A
Min. Typ. Max. Unit
40
2.5
V
1 µA
10 µA
±100 nA
3.5
2.4 3.0
V mΩ
3.0 4.0
Notes:
(1)
Defined by design. Not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 10 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 32 V, I
D
= 75 A,
V
GS
= 0 to 10 V (see Figure 14:
"Test circuit for gate charge behavior" )
Symbol Parameter
Table 7: Switching times
Test conditions
Min. Typ. Max. Unit
-
-
5600
890
-
- pF pF
-
-
-
-
560
91
28
27
-
-
-
- pF nC nC nC
Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off-delay time t f
Fall time
V
DD
= 30 V, I
D
= 75 A,
R
G
= 30 Ω, V
GS
= 10 V (see
Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
-
-
-
-
47
300
255
220
-
-
-
- ns ns ns ns
4/13 DocID029009 Rev 4
STLD125N4F6AG
Symbol Parameter
I
SD
(1)
Source-drain current
I
SDM
(2)
Source-drain current
(pulsed)
V
SD
(3)
Forward on voltage
I t rr
Q rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8: Source drain diode
Test conditions
I
V
GS
SD
= 0 V, I
SD
= 90 A
= 90 A, di/dt = 100 A/µs,
V
DD
= 20 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
40
41
2
120
480
1.2
A
A
V ns nC
A
Notes:
(1)
Limited by package
(2)
Pulse width is limited by safe operating area.
(3)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%
DocID029009 Rev 4 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STLD125N4F6AG
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/13 DocID029009 Rev 4
STLD125N4F6AG
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Source-drain diode forward characteristics
DocID029009 Rev 4 7/13
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STLD125N4F6AG
Figure 14: Test circuit for gate charge behavior
8/13
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID029009 Rev 4
STLD125N4F6AG
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 dual side cooling package information
Figure 19: PowerFLAT
™ 5x6 dual side cooling package outline
DocID029009 Rev 4 9/13
Package information
Dim.
E
E1
E2
E3
E4 e
I
L
L1
L2
ϑ
ϑ1 j
D
D1
D2
D3
A
A1 b c
STLD125N4F6AG
Table 9: PowerFLAT™ 5x6 dual side cooling mechanical data mm
Min. Typ. Max.
0.66
0.60
0.33
0.15
0.71 0.76
0.75
0.53
0.30
4.06
2.80
3.525
1.05
4.20
0.43
0.203
5.00 BSC
4.21
2.40 BSC
3.30
6.00 BSC
3.675
1.20
3.80 BSC
4.70
1.27 BSC
4.36
3.80
3.825
1.35
5.20
0.15
0.925
0.45
0.25
1.05
0.575
12° BSC
7° BSC
0.20 BSC
0.15
0.35
1.175
0.70
Figure 20:
PowerFLAT™ 5x6 dual side cooling recommended footprint (dimensions are in mm)
10/13 DocID029009 Rev 4
STLD125N4F6AG
4.2
Package information
PowerFLAT™ 5x6 dual side cooling packing information
Figure 21:
PowerFLAT™ 5x6 dual side cooling tape (dimensions are in mm)
8548087_REV1
Figure 22
: PowerFLAT™ 5x6 dual side cooling reel (dimensions are in mm)
DocID029009 Rev 4 11/13
Revision history
5
STLD125N4F6AG
Revision history
Date Revision
Table 10: Document revision history
Changes
16-Feb-2016
07-Feb-2017
23-Feb-2017
12-Jul-2017
1
2
3
4
First release.
Document status promoted from preliminary to production data.
Updated Table 3: "Thermal data" and Table 5: "On/off states" .
Minor text changes.
Updated features on cover page.
Updated Table 5: "On/off states" and Figure 9: "Normalized gate threshold voltage vs temperature" .
Minor text changes
Added Section 4.2: "PowerFLAT™ 5x6 dual side cooling packing information" .
12/13 DocID029009 Rev 4
STLD125N4F6AG
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DocID029009 Rev 4 13/13
