STMicroelectronics M48Z08 Datasheet
Annonce
Annonce
M48Z08, M48Z18
28
1
PDIP 28.7
Battery CAPHAT™
Features
•
Integrated, ultra low power SRAM and powerfail control circuit
•
Unlimited WRITE cycles
•
READ cycle time equals WRITE cycle time
•
Automatic power-fail chip deselect and WRITE protection
•
WRITE protect voltages
– (V
PFD
= power-fail deselect voltage):
– M48Z08: V
CC
4.5 V
≤
V
PFD
= 4.75 to 5.5 V;
≤
4.75 V
– M48Z18: V
CC
4.2 V
≤
V
PFD
= 4.5 to 5.5 V;
≤
4.5 V
•
Self-contained battery in the CAPHAT™ DIP package
•
Pin and function compatible with JEDEC standard 2 K x 8 SRAMs
•
RoHS compliant
– Lead-free second level interconnect
5 V, 16 kbit (2 Kb x 8) ZEROPOWER® SRAM
Datasheet production data
Description
The M48Z08/18 ZEROPOWER® RAM is a 8 K x
8 non-volatile static RAM which is pin and function compatible with the DS1225.
The monolithic chip provides a highly integrated battery-backed memory solution.
The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write timing or limitations on the number of writes that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the
M48Z08/18 silicon with a long-life lithium button cell in a single package.
September 2020
This is information on a product in full production.
DocID02424 Rev 9 1/18 www.st.com
Contents
Contents
M48Z08, M48Z18
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/18 DocID02424 Rev 9
M48Z08, M48Z18
1 Diagram
A0-A12
13
W
E
G
Figure 1. Logic diagram
VCC
8
DQ0-DQ7
M48Z08
M48Z18
A0-A12
DQ0-DQ7
E
G
W
V
CC
V
SS
NC
VSS
Table 1. Signal names
Address inputs
Data inputs / outputs
Chip enable
Output enable
WRITE enable
Supply voltage
Ground
Not connected internally
Diagram
AI01022
DocID02424 Rev 9 3/18
18
Pin connection
2 Pin connection
Figure 2. DIP connections
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
A12
A7
A6
A5
VSS
11
12
13
6
7
8
9
10
3
4
1
2
5
14
M48Z08
M48Z18
19
18
17
16
23
22
21
20
28
27
26
25
24
15
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 3. Block diagram
M48Z08, M48Z18
AI01183
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
VPFD
8K x 8
SRAM ARRAY
VCC VSS
A0-A12
DQ0-DQ7
E
W
G
AI01394
4/18 DocID02424 Rev 9
M48Z08, M48Z18
3 Operation modes
Note:
3.1
Operation modes
The M48Z08/18 also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When V
CC
is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below approximately 3 V, the control circuitry connects the battery which maintains data until valid power returns.
Mode V
CC
Deselect
WRITE
READ
4.75 to 5.5 V or
4.5 to 5.5 V
READ
Deselect V
SO
to V
PFD
(min)
(1)
Deselect
≤
V
SO
(1)
Table 2. Operating modes
E G W
V
IH
V
IL
V
IL
V
IL
X
X
X
X
V
IL
V
IH
X
X
X
V
IL
V
IH
V
IH
X
X
DQ0-
DQ7
Power
High Z
D
IN
D
OUT
High Z
High Z
Standby
Active
Active
Active
CMOS standby
High Z Battery backup mode
X = V
IH
or V
IL;
V
SO
= battery backup switchover voltage.
READ mode
The M48Z08/18 is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of
65,536 locations in the static storage array. Thus, the unique address specified by the 13
Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t
AVQV
) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t
ELQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (t
AXQX
) but will go indeterminate until the next address access.
DocID02424 Rev 9 5/18
18
Operation modes M48Z08, M48Z18
A0-A12
Figure 4. READ mode AC waveforms tAVAV
VALID tAVQV tELQV tAXQX tEHQZ
E tELQX tGLQV tGHQZ
G tGLQX
DQ0-DQ7 VALID
AI01385
Note: WRITE enable (W) = high.
Symbol
Table 3. READ mode AC characteristics
M48Z02/M48Z12
Parameter
(1)
Min.
Max.
t
AVAV t
AVQV t
ELQV t
GLQV t
ELQX
(2) t
GLQX
(2) t
EHQZ
2) t
GHQZ
(2) t
AXQX
READ cycle time
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
100
10
5
5
100
100
50
50
40
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. C
L
= 30 pF
Unit ns ns ns ns ns ns ns ns ns
3.2
6/18
WRITE mode
The M48Z08/18 is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E.
A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t
EHAX
from chip enable or t
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t
WLQZ
after
W falls.
DocID02424 Rev 9
M48Z08, M48Z18
A0-A12
Operation modes
Figure 5. WRITE enable controlled, WRITE AC waveform tAVAV
VALID tAVWH tAVEL tWHAX
E tWLWH tAVWL
W tWLQZ tWHQX
DQ0-DQ7 tWHDX
DATA INPUT tDVWH
AI01386
A0-A12
Figure 6. Chip enable controlled, WRITE AC waveforms tAVEL tAVAV
VALID tAVEH tELEH tEHAX
E tAVWL
W tEHDX
DQ0-DQ7 DATA INPUT tDVEH
AI01387B
DocID02424 Rev 9 7/18
18
Operation modes M48Z08, M48Z18
Symbol
Table 4. WRITE mode AC characteristics
M48Z08/M48Z18
Parameter
(1)
Min Max t
DVEH t
WHDX t
EHDX t
WLQZ
(2)(3) t
AVWH t
AVEH t
WHQX
(2)(3) t
AVAV t
AVWL t
AVEL t
WLWH t
ELEH t
WHAX t
EHAX t
DVWH
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable 1 low
WRITE enable pulse width
Chip enable low to chip enable 1 high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
100
0
0
80
80
10
10
50
30
5
5
80
80
10
50
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. C
L
= 30 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.3
Note:
8/18
Data retention mode
With valid V
CC
applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs become high impedance, and all inputs are treated as “don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the user can be assured the memory will be in a write protected state, provided the V
CC
fall time is not less than t
F
. The M48Z08/18 may respond to transient noise spikes on V
CC that reach into the deselect window during the time the device is sampling V
CC of the power supply lines is recommended.
. Therefore, decoupling
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z08/18 for an accumulated period of at least 11 years when V
CC
is less than V
SO
.
As system power returns and V
CC
rises above V
SO
, the battery is disconnected, and the power supply is switched to external V
CC
. Write protection continues until V
CC
reaches
V
PFD
(min) plus t rec
(min). E should be kept high as V
CC
rises past V
PFD
(min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume t rec after V
CC
exceeds V
PFD
(max). For more information on battery storage life refer to the application note AN1012.
DocID02424 Rev 9
M48Z08, M48Z18
3.4
Operation modes
V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 7 ) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
SS
). recommended for surface mount.
Figure 7. Supply voltage protection
VCC
VCC
0.1µF DEVICE
VSS
AI02169
DocID02424 Rev 9 9/18
18
Maximum ratings
4 Maximum ratings
M48Z08, M48Z18
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 5. Absolute maximum ratings
Parameter Value Unit
T
A
T
STG
T
SLD
(1)
V
IO
V
CC
I
O
P
D
Ambient operating temperature
Storage temperature (V
CC
off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
Output current
Power dissipation
Grade 1 0 to 70
–40 to 85
260
–0.3 to 7
–0.3 to 7
20
1
°C
°C
°C
V
V mA
W
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
10/18 DocID02424 Rev 9
M48Z08, M48Z18
5 DC and AC parameters
Note:
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC measurement conditions
Parameter M48Z08 M48Z18
Supply voltage (V
CC
)
Ambient operating temperature (T
A
)
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
Grade 1
4.75 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
4.5 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
Unit
V
°C pF ns
V
V
Output Hi-Z is defined as the point where data is no longer driven.
Figure 8. AC testing load circuit
5V
DEVICE
UNDER
TEST
1k Ω
1.8k
Ω
OUT
CL = 100pF or 30pF
CL includes JIG capacitance
Symbol
Table 7. Capacitance
Parameter
(1)(2)
Min Max
C
IN
C
IO
(3)
Input capacitance
Input / output capacitance -
10
10
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
DocID02424 Rev 9
AI01398
Unit pF pF
11/18
18
DC and AC parameters M48Z08, M48Z18
Symbol Parameter
Table 8. DC characteristics
Test condition
(1)
Min Max
I
LI
I
LO
(2)
I
CC
I
CC1
I
CC2
V
IL
V
V
V
IH
OL
OH
Input leakage current
Output leakage current
Supply current
Supply current (standby) TTL
Supply current (standby) CMOS
Input low voltage
Input high voltage
Output low voltage
Output high voltage
0V
≤
V
IN
≤
V
CC
0V ≤ V
OUT
≤ V
CC
Outputs open
E = V
E
=
V
CC
IH
– 0.2 V
I
OL
= 2.1 mA
I
OH
= –1 mA
–0.3
2.2
2.4
±1
±1
80
3
3
0.8
V
CC
+ 0.3
0.4
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. Outputs deselected.
Unit mA
V
V
V
V
µA
µA mA mA
Figure 9. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO tPD tF tFB tDR tRB
DON'T CARE tR tREC
RECOGNIZED INPUTS RECOGNIZED NOTE
Note:
HIGH-Z
OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as
V
CC
rises past V
PFD
(min). Some systems may perform inadvertent WRITE cycles after V
CC rises above V
PFD
(min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running.
12/18 DocID02424 Rev 9
M48Z08, M48Z18 DC and AC parameters
Symbol
Table 9. Power down/up AC characteristics
Parameter
(1)
Min.
Max.
Unit t
PD t
F
(2) t
FB
(3) t
R t
RB t
REC
E or W at V
V
PFD
V
PFD
V
PFD
V
SS
to V
E or W at V
IH
PFD
IH
before power down
(max) to V
PFD
(min) to V
SS
(min) to V
PFD
(min) V
(min) V
CC
V
CC
CC
fall time
(max) V
CC
before power up
fall time
rise time
rise time
0
300
10
0
1
2 -
-
-
-
-
µs
µs
µs
µs
µs ms
1. Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2. V
PFD
(max) to V
PFD
(min) fall time of less than t until 200 µs after V
CC
passes V
PFD
(min).
F
may result in deselection/write protection not occurring
3. V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
Symbol
Table 10. Power down/up trip points DC characteristics
Parameter
(1)(2)
Min.
Typ.
Max.
Unit
M48Z08 4.5
4.6
4.75
V
V
PFD
Power-fail deselect voltage
M48Z18 4.2
4.3
4.5
V
V
SO t
DR
(3)
Battery backup switchover voltage
Expected data retention time 11
3.0
V
YEARS
1. All voltages referenced to V
SS
.
2. Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
3. At 25 °C, V
CC
= 0 V.
DocID02424 Rev 9 13/18
18
Package mechanical data
6 Package mechanical data
M48Z08, M48Z18
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
Figure 10. PDIP 28.7 – 28-pin plastic DIP, battery CAPHAT™, package outline
Note:
A2 A
B1 e3
B
D
A1 e1
L eA
C
N
E
1
PCDIP
Drawing is not to scale.
Table 11. PDIP 28.7 – 28 pin plastic DIP, battery CAPHAT™, package mech. data mm inches
Symb
Typ.
Min.
Max.
Typ.
Min.
Max.
B1
C
D
E
A
A1
A2
B e1 e3 eA
L
N
33.02
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
15.24
3.05
28
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
16.00
3.81
1.3
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
0.630
0.150
14/18 DocID02424 Rev 9
M48Z08, M48Z18
7 Part numbering
Part numbering
Order code
M48Z08-100PC1
M48Z18-100PC1
Package
PDIP 28.7
Table 12. Ordering information
Temperature range
Speed
0 to 70 °C -100
Supply voltage
V
CC
= 4.75 to 5.5 V; V
PFD
= 4.5 to 4.75 V
V
CC
= 4.5 to 5.5 V; V
PFD
= 4.2 to 4.5 V
DocID02424 Rev 9 15/18
18
Environmental information
8 Environmental information
Figure 11. Recycling symbols
M48Z08, M48Z18
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
16/18 DocID02424 Rev 9
M48Z08, M48Z18
9 Revision history
Revision history
Date
Mar-1999
19-Jul-2001
19-Dec-2001
21-Dec-2001
20-May-2002
10-Sep-2002
01-Apr-2003
28-Aug-2004
14-Dec-2005
24-Mar-2009
27-May-2010
07-Jun-2011
23-Sep-2020
Table 13. Document revision history
Revision Changes
1
2
3
4
5
2.1
2.2
2.3
2.4
6
7
8
9
First issue
2-socket SOH and 2-pin SH packages removed; reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9, 10).
Remove all references to “clock”.
Changes to text to reflect addition of M48Z08Y option.
Modify reflow time and temperature footnotes (Table 5).
Remove all references to “SNAPHAT” and M48Z08Y part (Figure
1; Table 5, 6, 3, 4, 10, 12) v2.2 template applied; updated test condition (Table 10).
Reformatted; removed references to ‘crystal’ (Figure 1).
Updated template, Lead-free text, removed footnote (Table 8, 12).
Reformatted document; added text to Section 5: Package mechanical data; added Section 7: Environmental information.
Updated Section 3: Maximum ratings, Table 11; reformatted document; minor textual changes.
Updated footnote of Table 5: Absolute maximum ratings; updated
Section 7: Environmental information.
Added Table 12: Ordering information .
Updated package name.
DocID02424 Rev 9 17/18
18
M48Z08, M48Z18
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
18/18 DocID02424 Rev 9
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