STMicroelectronics N-channel 150 V - 0.085 Ohm - 10 A TO-220FP MESH OVERLAY Power MOSFET Datasheet
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विज्ञापन
STP30NS15LFP
N-channel 150V - 0.085
Ω
- 10A - TO-220FP
MESH OVERLAY™ II Power MOSFET
General features
Type V
DSS
STP30NS15LFP 150V
R
DS(on)
<0.1
Ω
■
■
■
Extremely high dv/dt capability
Application oriented characterization
100% avalanche tested
I
D
10A
Description
Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics.
Applications
■ Switching application
TO-220FP
1
2
3
Internal schematic diagram
Order codes
Obsolete Product(s) - Obsolete Product(s)
Part number Marking Package Packaging
STP30NS15LFP P30NS15LFP@ TO-220FP Tube
August 2006 Rev 3 1/12 www.st.com
12
Contents
Contents
STP30NS15LFP
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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STP30NS15LFP Electrical ratings
Table 1.
Symbol
Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
I
D
(1)
I
DM
(1)
P tot
Drain-source voltage (V
Gate- source voltage
GS
= 0)
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
= 25°C
= 100°C
Total dissipation at T
C
= 25°C
Derating factor
E
AS
(2) dv/dt
(3)
Single pulse avalanche energy
V
ISO
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all three leads to external heat sink
(t = 1s; Tc = 25°C)
T stg
T j
Storage temperature
Max. operating junction temperature
1.
Pulse width limited by safe operating area.
2.
Starting T j
= 25 o
C, I
D
= 15A, V
DD
= 75V
3.
I
SD
≤ ≤
300A/µs, V
DD
V
(BR)DSS
, T j
T
JMAX
Table 2.
Thermal data
Rthj-case Thermal resistance junction-case max
Rthj-amb Thermal resistance junction-ambient max
T
J
Maximum lead temperature for soldering purpose
Value
150
± 15
10
7
40
30
0.2
300
2.4
2500
-55 to 175
5
62.5
300
°C/W
°C/W
°C
Unit
V
V
A
A
A
W
W/°C mJ
V/ns
V
°C
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Electrical characteristics STP30NS15LFP
(T
CASE
=25°C unless otherwise specified)
Table 3.
Symbol
On/off states
Parameter
V
(BR)DSS
Drain-source breakdown voltage
V
I
I
DSS
GSS
GS(th)
R
DS(on)
Zero gate voltage drain current (V
GS
= 0)
Gate-body leakage current (V
DS
= 0)
Gate threshold voltage
Static drain-source on resistance
Test conditions
I
D
= 250µA, V
GS
=0
V
DS
= max ratings
V
DS
= max ratings,
T
C
= 125°C
V
GS
= ± 15V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 5A
V
GS
= 5V, I
D
= 5A
Min.
150
1
Typ.
Max.
Unit
V
1
10
µA
µA
2
0.85
0.1
±100
3
0.1
0.112
nA
V
Ω
Ω
Table 4.
Symbol
Dynamic
Parameter Test conditions Min.
Typ.
Max.
Unit g fs
(1)
C iss
C oss
C rss
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer capacitance
V
DS
= 20V
,
I
D
= 7A
V
DS
= 25V, f = 1MHz,
V
GS
= 0
6
1080
170
105 t d(on) t r t d(off) t f
Q g
Q gs
Q gd
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 15V, I
D
= 5A
R
G
= 4.7
Ω V
GS
= 4.5V
)
V
DD
= 120V, I
D
= 10A,
V
GS
= 5V
)
25
95
55
30
40
7.5
20
54
1.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
Obsolete Product(s) - Obsolete Product(s) nC nC nC ns ns ns ns
S pF pF pF
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STP30NS15LFP Electrical characteristics
Table 5.
Symbol
Source drain diode
Parameter Test conditions
I
I t
SD
I
SDM
V
SD
Q rr rr
(1)
(2)
RRM
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 10A, V
GS
= 0
I
SD
= 10A, di/dt = 100A/µs,
V
DD
= 30V, T j
= 150°C
(see
1.
Pulse width limited by safe operating area.
2.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Min.
Typ.
Max.
Unit
10
40
1.3
160
950
12
A
A
V ns nC
A
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Electrical characteristics
Figure 1.
Safe operating area Figure 2.
Thermal impedance
STP30NS15LFP
Figure 3.
Output characterisics Figure 4.
Transfer characteristics
Figure 5.
Transconductance Figure 6.
Static drain-source on resistance
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STP30NS15LFP Electrical characteristics
Figure 7.
Gate charge vs gate-source voltage Figure 8.
Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Normalized B
VDSS
vs temperature Figure 12. Source-drain diode forward characteristics
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Test circuit
3 Test circuit
Figure 13. Switching times test circuit for resistive load
STP30NS15LFP
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped Inductive load test circuit
Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform
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STP30NS15LFP
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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Package mechanical data STP30NS15LFP
DIM.
G1
H
L2
L3
F
F1
F2
G
A
B
D
E
L4
L5
L6
L7
Ø
0.75
1.15
1.15
4.95
2.4
10
MIN.
4.4
2.5
2.5
0.45
28.6
9.8
2.9
15.9
9
3
TO-220FP MECHANICAL DATA mm.
TYP
16
1
1.7
1.7
5.2
2.7
10.4
MAX.
4.6
2.7
2.75
0.7
30.6
10.6
3.6
16.4
9.3
3.2
MIN.
0.173
0.098
0.098
0.017
0.030
0.045
0.045
0.195
0.094
0.393
1.126
.0385
0.114
0.626
0.354
0.118
inch
TYP.
0.630
MAX.
0.181
0.106
0.108
0.027
0.039
0.067
0.067
0.204
0.106
0.409
1.204
0.417
0.141
0.645
0.366
0.126
L6
L7
L3
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L5
1 2 3
L2 L4
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STP30NS15LFP
Table 6.
Date
Revision history
Revision
09-Sep-2004
16-Aug-2006
2
3
Changes
Complete document
New template, no content change
Revision history
Obsolete Product(s) - Obsolete Product(s)
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STP30NS15LFP
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